KR20020001248A - Method of manufacturing and erasing a flash memory device - Google Patents

Abstract

PURPOSE: A method for manufacturing a flash memory device is provided to improve reliability, by forming an erase gate on a source line as well as a drain line so that an insulation layer over the source line is not damaged when a voltage is applied during an erase operation. CONSTITUTION: A tunnel oxide layer(202) and the first polysilicon layer(203) are sequentially formed on the semiconductor substrate(201), and are patterned. The source line(204) and the drain line(205) are formed on the substrate by an impurity ion implantation process. After the insulation layer(206) is formed on the resultant structure, a predetermined region of the insulation layer is etched to form a contact hole exposing a predetermined region of the first polysilicon layer. A conductive layer is filled in the contact hole to form a plug(207). The second polysilicon layer(208) is formed on the resultant structure, and is patterned to be in contact with the plug. A dielectric layer(209), the third polysilicon layer(210) and an oxide layer(211) are sequentially formed on the resultant structure, and are patterned to form a control gate. After a spacer(212) is formed on the sidewall of the control gate, the fourth polysilicon layer(213) is formed on the resultant structure. The fourth polysilicon is blank-etched to form the erase gate.

Description

Method of manufacturing and erasing a flash memory device {Method of manufacturing and erasing a flash memory device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing and erasing a flash memory device. In particular, the erase gate is formed to remain on top of a source line and a top of a drain line, and erase is performed at the drain as well as at the source. The present invention relates to a method of manufacturing and erasing a flash memory device capable of improving the performance.

1 is a cross-sectional view of a device for explaining a method of manufacturing a conventional flash memory device.

The tunnel oxide film 102 and the first polysilicon film 103 are sequentially formed on the semiconductor substrate 101. The first polysilicon film 103 and the tunnel oxide film 102 are patterned by a mask and an etching process. The source line 104 and the drain line 105 are formed on the exposed semiconductor substrate 101 by an impurity ion implantation process. After the insulating film 106 is formed over the entire structure, a predetermined region of the insulating film 106 is etched to form a contact hole through which the first polysilicon film 103 exposes the predetermined region. A conductive film is embedded in the contact hole to form a plug 107. The second polysilicon film 108 is formed on the entire structure and then patterned. The second polysilicon film 108 is patterned to contact the plug 107. After the dielectric film 109, the third polysilicon film 110, and the oxide film 111 are sequentially formed on the entire structure, they are patterned to form a control gate. After the oxide film is formed on the entire structure, the entire surface is etched to form a spacer 112 on the sidewall of the control gate. After the fourth polysilicon layer 113 is formed on the entire structure, the fourth polysilicon layer 113 is formed to remain only on the drain line 105, and is patterned to be removed on the source line 104 to form an erase gate.

In the flash memory device formed by the above process, there is one erase gate per two cells. For this purpose, the fourth polysilicon film used as the erase gate on the source line must be completely removed. However, when the etching time for removing the fourth polysilicon film is short, the polysilicon film is not completely removed and polysilicon residues remain. On the other hand, if the etching time is long, the polysilicon residue can be completely removed, but the insulating film formed on the source line is etched. Accordingly, when a voltage of 17 to 20 V is applied to the erase gate and 0 V to the source and the substrate to erase the cell, the insulating film is damaged. In addition, since the erasing operation is performed only on the source side, the uniformity of the element is lowered and the formation of the peripheral circuit becomes difficult because of the use of a high voltage.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a flash memory device in which an insulating film of a source line is not etched and no polysilicon residue remains in a process of forming an erase gate.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a flash memory device capable of improving the uniformity of devices by enabling erasing not only at the source but also at the drain.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of erasing a flash memory device capable of performing erasing not only at the source but also at the drain, and performing erasing by applying a relatively lower voltage than the prior art.

1 is a cross-sectional view of a device for explaining a method of manufacturing a conventional flash memory device.

2 is a cross-sectional view of a device for describing a method of manufacturing a flash memory device according to an embodiment of the present invention.

3 is a cross-sectional view of a device for describing a method of manufacturing a flash memory device according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

101, 201, and 301: semiconductor substrates 102, 202, and 302: tunnel oxide film

103, 203, and 303: first polysilicon film

104, 204, and 304: source lines 105, 205, and 305: drain lines

106, 206, and 306: insulating film 107, 207, and 307: plug

108, 208, and 308: second polysilicon film

109, 209, and 309: dielectric film

110, 210 and 310: third polysilicon film

111, 211, and 311: oxide films 112, 212, and 312: spacer

113, 213, and 313: fourth polysilicon film

In the method of manufacturing a flash memory device according to the present invention, a tunnel oxide film and a first polysilicon film are sequentially formed on a semiconductor substrate, and then patterned, and a source line and a drain line are formed on the semiconductor substrate by an impurity ion implantation process. And an insulating layer is formed over the entire structure, and then a predetermined region of the insulating layer is etched to form a contact hole for exposing the predetermined region of the first polysilicon layer, and then a conductive layer is formed to fill the contact hole. And forming a second polysilicon film on the entire structure, and then patterning the second polysilicon film to contact the plug, and subsequently forming a dielectric film, a third polysilicon film, and an oxide film on the entire structure, and then patterning the control gate. Forming a space on the sidewall of the control gate; After the entire structure above the fourth step and the polysilicon film, and the fourth polysilicon film is formed over the etch it is characterized in that made in a step that forms the erase gate.

In the erase method of the flash memory device according to the present invention, a voltage of 12 to 14 V is applied to the erase gate of the flash memory device manufactured by the above process, and a voltage of -5 V is applied to the drain line, the substrate and the source line. It is characterized in that the implementation.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a cross-sectional view of a device for describing a method of manufacturing a flash memory device according to an embodiment of the present invention.

The tunnel oxide film 202 and the first polysilicon film 203 are sequentially formed on the semiconductor substrate 201. The first polysilicon film 203 and the tunnel oxide film 202 are patterned by a mask and an etching process. The source line 204 and the drain line 205 are formed on the exposed semiconductor substrate 201 by an impurity ion implantation process. After the insulating film 206 is formed over the entire structure, a predetermined region of the insulating film 206 is etched to form a contact hole through which the first polysilicon film 203 exposes the predetermined region. A conductive film is embedded in the contact hole to form a plug 207. The second polysilicon film 208 is formed on the entire structure and then patterned. The second polysilicon film 208 is patterned to contact the plug 207. After the dielectric film 209, the third polysilicon film 210, and the oxide film 211 are sequentially formed on the entire structure, they are patterned to form a control gate. After the oxide film is formed on the entire structure, the entire surface is etched to form a spacer 212 on the sidewall of the control gate. The fourth polysilicon layer 213 is formed on the entire structure, and then patterned to remain between the flash memory cells by a front surface etching process to form an erase gate.

3 is a cross-sectional view of a device for describing a method of manufacturing a flash memory device according to another embodiment of the present invention.

The tunnel oxide film 302 and the first polysilicon film 303 are sequentially formed on the semiconductor substrate 301. The first polysilicon layer 303 and the tunnel oxide layer 302 are patterned by a mask and an etching process. The source line 304 and the drain line 305 are formed on the exposed semiconductor substrate 301 by an impurity ion implantation process. After the insulating film 306 is formed over the entire structure, a predetermined region of the insulating film 306 is etched to form a contact hole through which the first polysilicon film 303 exposes the predetermined region. A conductive film is embedded in the contact hole to form a plug 307. The second polysilicon film 308 is formed on the entire structure and then patterned. The second polysilicon film 308 is patterned to contact the plug 307. After the dielectric film 309, the third polysilicon film 310, and the oxide film 311 are sequentially formed on the entire structure, they are patterned to form a control gate. After the oxide film is formed on the entire structure, the entire surface is etched to form a spacer 312 on the sidewall of the control gate. The fourth polysilicon layer 313 is formed on the entire structure, and then patterned by a mask and an etching process using an erase gate mask to form an erase gate. The fourth polysilicon layer 313 is completely embedded between the flash memory cells and patterned to have a predetermined height to form an erase gate.

In the two embodiments according to the present invention, a voltage of 12 to 14 V is applied to the erase gate and a low voltage of −5 V is applied to the drain, the substrate, and the source, respectively, to perform the erase operation.

As described above, according to the present invention, since the erase gate is formed not only on the drain line but also on the source line, the insulating film on the source line is not etched, and thus the insulating film on the source line is not damaged even at a voltage applied when the erase operation is performed. The reliability of the device can be improved. In addition, uniformity can be improved by erasing only on the drain side instead of only on the source side per cell.

Claims (3)

A tunnel oxide film and a first polysilicon film are sequentially formed on the semiconductor substrate and then patterned; Forming a source line and a drain line on the semiconductor substrate by an impurity ion implantation process; Forming a contact hole after the insulating layer is formed over the entire structure, and forming a contact hole through which a predetermined region of the insulating layer is etched to expose the predetermined region of the first polysilicon layer, and then a conductive layer is formed to fill the contact hole; Forming a second polysilicon layer on the entire structure and patterning the second polysilicon layer to be in contact with the plug; A dielectric film, a third polysilicon film, and an oxide film are sequentially formed on the entire structure, and then patterned to form a control gate; Forming a fourth polysilicon layer on the entire structure after the spacing is formed on the sidewalls of the control gate; And etching the entire surface of the fourth polysilicon layer to form an erase gate. The flash memory of claim 1, wherein the erase gate is patterned and formed by a lithography process and an etching process using an erase gate mask so that the fourth polysilicon layer remains on the source line and the drain line. Method of manufacturing the device. A tunnel oxide film and a first polysilicon film are sequentially formed on the semiconductor substrate and then patterned; Forming a source line and a drain line on the semiconductor substrate by an impurity ion implantation process; Forming a contact hole after the insulating layer is formed over the entire structure, and forming a contact hole through which a predetermined region of the insulating layer is etched to expose the predetermined region of the first polysilicon layer, and then a conductive layer is formed to fill the contact hole; Forming a second polysilicon layer on the entire structure and patterning the second polysilicon layer to contact the plug; A dielectric film, a third polysilicon film, and an oxide film are sequentially formed on the entire structure, and then patterned to form a control gate; Forming a fourth polysilicon layer on the entire structure after the spacing is formed on the sidewalls of the control gate; A voltage of 12 to 14 V is applied to the erase gate of the flash memory device manufactured by the fourth polysilicon layer is etched to form an erase gate, and a voltage of −5 V is applied to the drain line, the substrate, and the source line. The erase method of the flash memory device, characterized in that the erase is performed.