KR100595119B1 - Nonvolatile memory device and method for manufacturing the same - Google Patents

Abstract

According to the present invention, a dielectric film formed to have a gate oxide film formed on a semiconductor substrate, a floating gate formed on the gate oxide film, and a form formed on the floating gate and undercut inward with respect to an upper surface edge of the floating gate. And a first erase gate formed on the dielectric layer and having an undercut top, a second erase gate formed on the first erase gate, and a periphery of the first erase gate and the second erase gate. And a control gate formed on the insulating layer to cover the first and second erase gates.

Nonvolatile Memory, Floating Gate, Erase Gate, Control Gate

Description

Nonvolatile memory device and method for manufacturing same             

1 and 2 are cross-sectional views illustrating a conventional EPROM cell manufacturing method.

3 is a layout diagram of a nonvolatile memory device according to an exemplary embodiment of the present invention.

4 to 10 are cross-sectional views when cut along the line II ′ of FIG. 3.

FIG. 11 is a cross-sectional view taken along the line II-II ′ of FIG. 3.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 102 gate oxide film

104a: floating gate 106a: dielectric film

110: source / drain 112: field oxide film

114a: first erase gate 116a: second erase gate

120: insulating film 122: control gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device and a method of manufacturing the same, which can be programmed at a low voltage and a transient erase phenomenon can be suppressed.

Erasable Programmable Read Only Memory (EPROM) is a type of ROM (Read Only Memory) that allows a user to erase or reinsert information stored in the memory. It is a PROM (Programmable Read Only Memory) which can write the memory contents electrically and can be erased by irradiating ultraviolet rays.

1 and 2 are cross-sectional views illustrating a conventional EPROM cell manufacturing method. 1 shows a cross section of the cell in the width direction, and FIG. 2 shows a cross section of the cell in the longitudinal direction.

1 and 2, after forming the isolation layer 12 on the semiconductor substrate 10, the gate oxide layer 14 is formed on the semiconductor substrate 10 on which the isolation layer 12 is formed. On the gate oxide film 14, a polysilicon film 16 to be used as a floating gate, a dielectric film 18 made of an oxide film / nitride film / oxide film, and a polysilicon film 20 to be used as a control gate are sequentially formed, and then selectively Etching is performed to form a gate electrode. Subsequently, impurities are ion implanted using the gate electrode as a mask to form the source / drain 22.

On the other hand, EEPROM (Electrically Erasable Programmable Read Only Memory, hereinafter referred to as "EEPROM") is a memory that can be erased and written electrically and data is preserved even when the power supply voltage is off (Off). The EEPROM can be electrically erased and programmed using tunneling, allowing the user to change information.

In the conventional EEPROM cell, a voltage of 12.0 V is applied to a word line (control gate) and 7.5 V is applied to a bit line to trap hot electrons generated in a source region in a dielectric film. Do this.

By selectively programming the EEPROM cell, the programmed cell is recognized as having a high threshold voltage (Vt) (5 V or more), but the unprogrammed cell is recognized as having a low threshold voltage (5 V or less) and it can be confirmed that it is selectively programmed. have.

However, since the device isolation layer is formed in a LOCOS structure, cell density increases.

In addition, in the case of a stack gate type structure, two polysilicon film forming processes are applied to form a floating gate and a control gate, and as a result, a step between the logic area occurs and a post process is performed. Unbalance of the gate critical dimension (CD) may occur or residues of the polysilicon film may occur.

In addition to the thickness of the dielectric film in the EEPROM program, the more the dielectric film area occupies in the EEPROM cell, the better the EEPROM program characteristics, but there is a limit to increasing it.

In addition, a characteristic in which electrons trapped in the dielectric film are retained due to hot electron generation is a data retention characteristic, and there is a limit in improving data retention characteristics due to the dielectric film characteristics.

When implementing EEPROM or flash memory cells, it is difficult to realize stable erase characteristics due to over erase.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a nonvolatile memory device which can be programmed with a low voltage and suppresses excessive erase.

Another object of the present invention is to provide a method of manufacturing a nonvolatile memory device which can be programmed with a low voltage and a transient erase phenomenon can be suppressed.

According to the present invention, a dielectric film formed to have a gate oxide film formed on a semiconductor substrate, a floating gate formed on the gate oxide film, and a form formed on the floating gate and undercut inward with respect to an upper surface edge of the floating gate. And a first erase gate formed on the dielectric layer and having an undercut on the dielectric layer, a second erase gate formed on the first erase gate, the first erase gate and the second erase gate. A nonvolatile memory device including an insulating film surrounding a periphery and a control gate formed on the insulating film to cover the first and second erase gates.

In addition, the present invention comprises the steps of sequentially forming a gate oxide film, a floating gate material film and a dielectric film on the semiconductor substrate, and after forming a first mask pattern defining a region in which the floating gate is to be formed on the dielectric film, Selectively wet etching the dielectric layer with the first mask pattern using an etch mask to undercut the lower portion of the first mask pattern to trim the dielectric layer, and using the first mask pattern as an etch mask for the floating gate. Dry etching the material film to form a floating gate, implanting impurities to form a source / drain, depositing an oxide film on the resultant, and then planarizing the surface of the dielectric film to form a field oxide film. And a doped polysilicon film and an undoped pole for forming an erase gate on the resultant. Sequentially forming a silicon film, forming a second mask pattern defining a region in which an erase gate is to be formed, and selectively dry-etching the undoped polysilicon film using the second mask pattern as an etch mask. Partially wet etching the doped polysilicon layer using an etch mask as an etch mask to form an undercut under the undoped polysilicon layer, and selectively selecting the doped polysilicon layer using the second mask pattern as an etch mask. Dry etching, forming an insulating film around the doped polysilicon film and the undoped polysilicon film, depositing a control gate material film, and then patterning to form a control gate. A method of manufacturing a nonvolatile memory device is provided.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the following embodiments are provided to those skilled in the art to fully understand the present invention, and may be modified in various forms, and the scope of the present invention is limited to the embodiments described below. It doesn't happen. In the following description, when a layer is described as being on top of another layer, it may be present directly on top of another layer, with a third layer interposed therebetween. In the drawings, the thickness and size of each layer are exaggerated for clarity and convenience of explanation. Like numbers refer to like elements in the figures.

3 to 11 are cross-sectional views illustrating a nonvolatile memory device and a method of manufacturing the same according to an exemplary embodiment of the present invention. 3 is a layout diagram of a nonvolatile memory device. 4 to 10 are cross-sectional views when cut along the line II ′ of FIG. 3, and FIG. 11 is a cross-sectional view when cut along the line II-II ′ of FIG. 3.

Referring to FIG. 4, a buffer oxide film (not shown) is formed on the semiconductor substrate 100. Ion implantation is performed on the semiconductor substrate 100 to adjust the threshold voltage Vt. In this case, the buffer oxide film serves as a buffer layer to mitigate damage to the semiconductor substrate 100 by ion implantation. Subsequently, the buffer oxide film is removed.

A gate oxide layer 102 is formed on the semiconductor substrate 100 through a gate oxide process. The gate oxide film 102 may be formed using a wet oxidation method, for example, may be formed by performing wet oxidation at a temperature of about 750 ° C to 900 ° C.

A doped polysilicon film 104 for depositing a floating gate is deposited on the gate oxide film 102. The polysilicon layer 104 is a low pressure-chemical vapor deposition using a silicon source (eg, SiH ₄ , Si ₂ H _6, etc.) gas and an impurity source (eg, POCl ₃ , PH _3, etc.) gas. It can be formed at a temperature of about 580 to 620 ℃ and a pressure of about 0.1 to 3 Torr.

The dielectric film 106 is formed on the polysilicon film 104. The dielectric layer 106 may be formed in an oxide / nitride / oxide structure, that is, in an ONO (SiO ₂ / Si ₃ N ₄ / SiO ₂ ) structure. The oxide film of the dielectric film 106 may be formed of high temperature oxide (HTO) using SiH ₂ Cl ₂ (dichlorosilane; DCS) and H ₂ O gas as a source gas. The nitride film of the dielectric film 106 uses NH ₃ and SiH ₂ Cl ₂ (dichlorosilane; DCS) gas as a reaction gas, and is formed by LP-CVD at a pressure of about 0.1 to 3 Torr and a temperature of about 650 to 800 ° C. can do.

A photoresist pattern 108 is formed on the dielectric film 106 to define the region where the floating gate is to be formed.

Referring to FIG. 5, the dielectric layer 106 may be selectively wet-etched using the photoresist pattern 108 as an etch mask to trim the dielectric layer 106. The wet etching may form a dielectric film 106a having an undercut shape inward with respect to the top edge of the polysilicon film 104. Since the wet etching is isotropic etching, undercut is generated below the photoresist pattern 108, and the dielectric layer 106 is trimmed smaller than the photoresist pattern 108. The wet etching uses an etching condition having a large etching selectivity with respect to the polysilicon film 104.

The floating gate 104a is formed by selectively dry etching the polysilicon layer 104 using the photoresist pattern 108 as an etching mask. Since the dry etching is anisotropic dry etching, the polysilicon layer 104 may be selectively etched along the profile of the photoresist pattern 108.

Referring to FIG. 6, the photoresist pattern 108 is removed. Subsequently, impurities are ion implanted to form the source / drain 110. The impurity may be an impurity such as arsenic (As) or phosphorus (P) when the channel to be formed is an N-type channel. A buried channel region is formed under the gate oxide layer 102 between the source / drain 110.

An oxide film 112 is formed on the resultant. The oxide film 112 may be formed using an HLD film, a high density plasma (HDP) film, a boro phosphorus silicate glass (BPSG) film, a tetra ethyl ortho silicate (TEOS) film, a spin on glass (SOG) film, or the like. . The oxide film 112 is planarized so that the surface of the dielectric film 106a is exposed. The planarization may use a chemical mechanical polishing (CMP) process. The oxide layer 112 serves as a field oxide layer that separates the floating gates 104a.

Referring to FIG. 7, a polysilicon film 114 doped (highly doped with impurities) for forming a first erase gate is deposited on the resultant. The doped polysilicon layer 114 is a low pressure-chemical compound (LP-CVD) using a silicon source (eg, SiH ₄ , Si ₂ H _6, etc.) gas and an impurity source (eg, POCl ₃ , PH _3, etc.) gas. Vapor Deposition) may be formed at a temperature of about 580 to 620 ℃ and a pressure of about 0.1 to 3 Torr.

An undoped (non-doped) polysilicon film 116 is formed on the doped polysilicon film 114 to form a second erase gate. The undoped polysilicon film 116 is a low pressure-chemical vapor deposition (LP-CVD) method using a silicon source (eg, SiH ₄ , Si ₂ H _6, etc.) gas and has a temperature of about 580 to 620 ° C. and about 0.1 ° C. It can be formed under pressure conditions of about 3 Torr.

A photoresist pattern 118 is formed defining a region where an erase gate is to be formed.

Referring to FIG. 8, the undoped polysilicon layer 116 is selectively dry etched using the photoresist pattern 118 as an etching mask.

The doped polysilicon layer 114 is wet etched using the photoresist pattern 118 as an etching mask to form an undercut under the undoped polysilicon layer 116. The wet etching is isotropically etched, and the upper portion of the polysilicon layer 114 doped with impurities at a high concentration is selectively etched to form an undercut.

Referring to FIG. 9, the doped polysilicon layer 114 is selectively dry-etched using the photoresist pattern 118 as an etching mask. Since the dry etching is anisotropic dry etching, the doped polysilicon layer 114 may be selectively etched along the profile of the photoresist pattern 118. The undoped polysilicon film 116 used as the first erase gate and the doped polysilicon film 114 used as the second erase gate are formed to have the same maximum width. The photoresist pattern 118 is removed.

Anneal process is performed. The dopant doped in the doped polysilicon film 114 is diffused into the undoped polysilicon film 116 by the annealing process. In addition, an insulating film (natural oxide film) 120 is formed around the doped polysilicon 114 and the undoped polysilicon film 116. That is, the native oxide film 120 is formed along the periphery of the first erase gate 114a having the upper cut portion and the second erase gate 116a formed on the first erase gate 114a. Of course, the insulating film 120 may be formed using an oxidation process.

The insulating layer 120 insulates the control gate and the first and second erase gates 114a and 116a to be formed in a subsequent process.

10 and 11, a polysilicon film for forming the control gate is deposited on the insulating layer 120, and then patterned to form the control gate 122. The control gate 122 is formed on the insulating film 120 to cover the first and second erase gates 114a and 116a.

Hereinafter, program, erase, and read operations of a nonvolatile memory device according to an exemplary embodiment of the present invention will be described.

The program operation can be made as follows. A high voltage of about 12V is applied to the erase gates 116a and 114a to invert the channel. When a voltage of 7 V is applied to the drain 110 and the source 110 and the semiconductor substrate 100 are grounded, a hot carrier may be applied from the drain 110 to the floating gate 104a by CHE injection. (Electrons) are injected and programmed. The injected hot carrier is trapped in the insulating film 120 between the dielectric film 106a and the erase gates 116a and 114a and the control gate 122.

The erase operation may be performed as follows. When a nonvolatile memory device is used as an EPROM cell, an erasing method using ultraviolet rays is used to emit a carrier (electron) charged in the floating gate 104a. When a nonvolatile memory device is used as an EEPROM or a flash memory cell, a dielectric may be applied by applying a weak voltage of 3V or more to the erase gates 116a and 114a to release a carrier (electron) charged in the floating gate 104a. Electrons trapped in the insulating film 120 between the film 106a and the erase gates 116a and 114a and the control gate 122 are emitted. Since there is no over erase characteristic by the erase gates 116a and 114a, there is no restriction on the erase time. In other words, since the erasing can be performed in a very short time, the life time of the cell is increased.

The read operation may be performed as follows. By reading the threshold voltage Vt of the cell transistor, the on / off state of the cell is determined and read. For this purpose, if a voltage of 5V is applied to the erase gates 116a and 114a and a voltage of 1V is applied to the drain 110, the program cell is turned off due to a high threshold voltage (greater than 5V) and the erase cell is thresholded. The voltage is low and is determined to be On.

According to the nonvolatile memory device and the manufacturing method thereof according to the present invention, it is possible to program at a low voltage and suppress the excessive erase phenomenon. In addition, the stack gate structure has the advantage of minimizing the step difference of the memory cell.

Although the erase gate is located under the control gate, the contact area is high, and thus, there is an advantage in that it can be programmed without affecting the coupling ratio at all.

As a trap source of CHE (Channel Hot Election), an insulating film between the dielectric film, the erase gate, and the control gate can be used, so that the program duration time (or life time) of the programmed cell is changed. Can be increased.

Due to the use of a buried channel, higher integration is possible compared to the conventional LOCOS method.

As mentioned above, although preferred embodiment of this invention was described in detail, this invention is not limited to the said Example, A various thing by the person of ordinary skill in the art within the range of the technical idea of this invention. Modifications are possible.

Claims (12)

A gate oxide film formed on the semiconductor substrate; A floating gate formed on the gate oxide film; A dielectric film formed on the floating gate and having a shape undercut inward with respect to an edge of an upper surface of the floating gate; A first erase gate formed on the dielectric layer and having an upper portion undercut; A second erase gate formed on the first erase gate; An insulating layer surrounding the periphery of the first erase gate and the second erase gate; And And a control gate formed on the insulating layer to cover the first and second erase gates. The nonvolatile memory device of claim 1, wherein each of the first erase gate and the second erase gate is formed to have the same maximum width. The nonvolatile memory device of claim 1, further comprising a source / drain region formed in the semiconductor substrate between the floating gates. The nonvolatile memory device of claim 1, further comprising a field oxide layer formed on the semiconductor substrate between the floating gate and the dielectric layer. Sequentially forming a gate oxide film, a floating gate material film, and a dielectric film on the semiconductor substrate; After forming a first mask pattern defining a region in which a floating gate is to be formed on the dielectric layer, selectively wet etching the dielectric layer to partially undercut the first mask pattern using the first mask pattern as an etch mask. Trimming the dielectric film; Forming a floating gate by dry etching the material layer of the floating gate using the first mask pattern as an etching mask; Implanting impurities to form a source / drain; Depositing an oxide film on the resultant, and then planarizing the surface of the dielectric film to form a field oxide film; Sequentially forming a doped polysilicon film and an undoped polysilicon film for forming an erase gate on the resultant; After forming a second mask pattern defining a region in which an erase gate is to be formed, selectively dry-etch the undoped polysilicon layer using the second mask pattern as an etch mask, and dope the second mask pattern with an etch mask. Partially wet etching the polysilicon film to form an undercut under the undoped polysilicon film; Selectively dry etching the doped polysilicon layer using the second mask pattern as an etching mask; Forming an insulating film around the doped polysilicon film and the undoped polysilicon film; And And depositing a control film material layer and then patterning the control gate to form a control gate. The method of claim 5, wherein before forming the gate oxide film, Forming a buffer oxide film; Performing ion implantation for adjusting the threshold voltage; And And removing the buffer oxide layer. The method of claim 5, wherein the floating gate material layer is formed of a doped polysilicon layer. 6. The method of claim 5, wherein the dielectric film is formed of a film in which oxide films, nitride films, and oxide films are sequentially stacked. The method of claim 5, wherein the control gate material layer is formed of a doped polysilicon layer. The method of claim 5, wherein the partial wet etching of the dielectric layer is performed under an etching condition having a high etching selectivity with respect to the floating gate material layer. The method of claim 5, wherein the doped polysilicon film is a polysilicon film doped with a high concentration of impurities, and the partial wet etching of the doped polysilicon film to selectively etch such that the upper portion of the doped polysilicon film is an undercut A method of manufacturing a nonvolatile memory device, characterized in that. The method of claim 5, wherein the forming of the insulating layer uses an annealing process, and the doped polysilicon layer diffuses impurities doped into the doped polysilicon layer by the annealing process. And forming a natural oxide film around the film and the undoped polysilicon film.

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