KR20020001017A - Decoupling capacitor of semiconductor device and forming mothed thereof - Google Patents
Decoupling capacitor of semiconductor device and forming mothed thereof Download PDFInfo
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- KR20020001017A KR20020001017A KR1020000034901A KR20000034901A KR20020001017A KR 20020001017 A KR20020001017 A KR 20020001017A KR 1020000034901 A KR1020000034901 A KR 1020000034901A KR 20000034901 A KR20000034901 A KR 20000034901A KR 20020001017 A KR20020001017 A KR 20020001017A
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- Prior art keywords
- decoupling capacitor
- region
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- semiconductor device
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- 239000003990 capacitor Substances 0.000 title claims abstract description 47
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 4
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 238000002955 isolation Methods 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 239000002019 doping agent Substances 0.000 abstract 2
- 238000004519 manufacturing process Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
Abstract
Description
본 발명은 반도체소자의 디커플링 캐패시터 및 그 제조방법에 관한 것으로서, 특히 디커플링 캐패시터를 기판 상에 형성된 연속적인 pn 접합을 병렬로 연결시켜 형성하여 고집적화에 유리한 반도체소자의 디커플링 캐패시터 및 그 제조방법에 관한 것이다.The present invention relates to a decoupling capacitor of a semiconductor device and a method of manufacturing the same, and more particularly, to a decoupling capacitor of a semiconductor device, which is advantageous for high integration by forming a decoupling capacitor by connecting a continuous pn junction formed on a substrate in parallel, and a method of manufacturing the same. .
종래 일반적인 디커플링 캐패시터는 전압의 안정화를 위하여 입력패드나 전원전압단자등에 형성되는데, 주로 반도체기판-게이트산화막-게이트층으로 구성되는 캐패시터를 사용하는데, 큰 정전용량을 확보하기 위하여 소자의 일측에 비교적 널게 형성되어, 소자의 고집적화를 방해하는 문제점이 있다.Conventional decoupling capacitors are formed on input pads or power supply voltage terminals for stabilizing voltage, and mainly use capacitors composed of semiconductor substrate-gate oxide film-gate layers, and are relatively large on one side of the device to secure large capacitance. Formed, there is a problem of preventing the high integration of the device.
이러한 문제점은 소자가 고집적화 될수록 더욱 증가되어 디커플링 캐패시터가 차지하는 면적 비중이 더 커지게 되어 웨이퍼의 넷다이수가 감소되어 결과적으로 소자의 생산수율이 떨어지는 문제점이 있다.This problem increases as the device becomes more integrated, so that the proportion of the area occupied by the decoupling capacitor becomes larger, and thus the number of net dies of the wafer is reduced, resulting in a decrease in production yield of the device.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 작은 면적에 큰 정전용량의 디커플링 캐패시터를 형성하여 디커플링 캐패시터가 차지하는 면적을 감소시켜 소자의 고집적화를 유리하게 하여 생산수율을 증가시킬 수 있는 반도체소자의 디커플링 캐패시터 및 그 제조방법을 제공함에 있다.The present invention is to solve the above problems, an object of the present invention is to form a large capacitance decoupling capacitor in a small area to reduce the area occupied by the decoupling capacitor to increase the production yield by favoring high integration of the device The present invention provides a decoupling capacitor of a semiconductor device and a method of manufacturing the same.
도 1은 본 발명에 따른 디커플링 캐패시터의 레이아웃도.1 is a layout diagram of a decoupling capacitor according to the invention.
도 2a 내지 도 2c는 본 발명에 따른 디커플링 캐패시터의 제조공정도.2a to 2c is a manufacturing process diagram of the decoupling capacitor according to the present invention.
도 3은 본 발명에 따른 디커플링 캐패시터의 등가회로도.3 is an equivalent circuit diagram of a decoupling capacitor according to the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
10 : 반도체기판 12 : p형 영역10 semiconductor substrate 12 p-type region
14 : n형 영역 16 : 소자분리산화막14 n-type region 16: device isolation oxide film
18,20 : 감광막 패턴 22 : 층간절연막18, 20: photosensitive film pattern 22: interlayer insulating film
24 : 콘택홀 26 : 배선24: contact hole 26: wiring
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자의 디커플링 캐패시터의 특징은,Features of the decoupling capacitor of the semiconductor device according to the present invention for achieving the above object,
반도체기판 상에 형성된 반도체소자의 Vcc와 Vss의 사이에 형성되어 전압을 안정화시키는 디커플링 캐패시터에 있어서,In the decoupling capacitor formed between the Vcc and Vss of the semiconductor element formed on the semiconductor substrate to stabilize the voltage,
반도체기판의 주변회로영역 일측에 구비되어있는 디커플링 캐패시터 영역에 다수개의 서로 인접한 pn 접합을 형성하고, 각 p 와 n 영역을 Vss 및 Vcc 단자와 연결시키는 것에 있다.A plurality of adjacent pn junctions are formed in a decoupling capacitor region provided on one side of a peripheral circuit region of a semiconductor substrate, and the respective p and n regions are connected to the Vss and Vcc terminals.
또한 상기 p 및 n영역을 반복되는 직사각띠 형상으로 형성하는 것을 특징으로 한다.In addition, the p and n region is characterized in that to form a repeating rectangular band shape.
본 발명에 따른 반도체소자의 디커플링 캐패시터 제조방법의 특징은,A feature of the method for manufacturing a decoupling capacitor of a semiconductor device according to the present invention,
반도체기판에서 주변회로 영역의 디커플링 캐패시터영역으로 예정되어있는 부분을 감싸는 소자분리산화막을 형성하는 공정과,Forming a device isolation oxide film surrounding the predetermined portion of the semiconductor substrate as the decoupling capacitor region of the peripheral circuit region;
상기 디커플링 캐패시터 영역 내에 서로 인접하게 p 및 n 영역을 형성하는 공정과,Forming p and n regions adjacent to each other in the decoupling capacitor region;
상기 p 및 n영역과 접촉되는 Vss 및 Vcc 단자를 형성하는 공정을 구비함에 있다.And forming a Vss and Vcc terminal in contact with the p and n regions.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체소자의 디커플링 캐패시터 및 그 제조방법에 관하여 상세히 설명을 하기로 한다.Hereinafter, a decoupling capacitor of a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명의 실시 예에 따른 디커플링 캐패시터의 레이아웃도로서, 반도체기판(10)의 주변회로영역중 디커플링 캐패시터 영역으로 예정되어있는 부분 상에 서로 연접한 직사각띠 형상의 p 및 n형 영역(12,14)이 반복형성되어있다.1 is a layout view of a decoupling capacitor according to an exemplary embodiment of the present invention, wherein p and n-type regions having a rectangular band shape connected to each other on a portion of the peripheral circuit region of the semiconductor substrate 10 that is intended as a decoupling capacitor region (FIG. 12,14) is repeated.
상기에서 p 및 n 영역들을 직사각띠 형상으로 형성하였으나, 이는 작은 면적에 넓은 접촉 면적을 가지는 디커플링 캐패시터를 형성하기 위한 것으로서, 스트라이프 형상이나 원형 등과 같은 기타 다른 형상으로 형성할 수도 있다.Although the p and n regions are formed in a rectangular band shape as described above, this is to form a decoupling capacitor having a large contact area in a small area, and may be formed in other shapes such as a stripe shape or a circular shape.
도 2a 내지 도 2c는 본 발명에 따른 디커플링 캐패시터의 제조 공정도이다.2A to 2C are manufacturing process diagrams of the decoupling capacitor according to the present invention.
먼저, 실리콘 웨이퍼 등의 반도체기판(10)에서 사각 형상의 디커플링 캐패시터 영역으로 예정되어있는 부분을 외부 소자와 격리시키기 위한소자분리산화막(16)을 형성하고, 상기 디커플링 캐패시터 영역에서 n형 영역으로 예정되어있는 부분을 노출시키는 제1 감광막 패턴(18)을 형성한 후, 인등과 같은 n형 불순물을 고농도로 이온 주입하여 n형 영역(14)을 형성한다. (도 2a 참조).First, an element isolation oxide film 16 is formed to isolate a portion of the semiconductor substrate 10 such as a silicon wafer, which is supposed to be a square decoupling capacitor region, from an external element, and to be an n-type region in the decoupling capacitor region. After forming the first photosensitive film pattern 18 exposing the portion, the n-type region 14 is formed by ion implantation of n-type impurities such as phosphorous at a high concentration. (See FIG. 2A).
그다음 상기 제1 감광막 패턴(18)을 제거하고, 다시 p형 영역으로 예정되어있는 부분을 노출시키는 제2 감광막 패턴(20)을 형성한 후, 보론 등의 p형 불순물을 고농도 이온 주입하여 p형 영역(12)들을 형성한다. 이때 상기 n 및 p형 영역(14,12)들은 서로 맞닿도록 형성된다. (도 2b 참조).Thereafter, the first photoresist pattern 18 is removed, and a second photoresist pattern 20 is formed to expose a predetermined portion of the p-type region, and then p-type impurities such as boron are implanted at a high concentration to form a p-type. Areas 12 are formed. In this case, the n and p-type regions 14 and 12 are formed to abut each other. (See FIG. 2B).
그후 상기 제2 감광막 패턴(20)을 제거하고, 상기 구조의 전표면에 층간절연막(22)을 형성한 후, 상기 n 및 p형 영역(14,12)들 상의 층간절연막(22)을 제거하여 콘택홀(24)을 형성하고, 상기 콘택홀(24)을 통하여 Vcc 나 Vss의 전원전압과 연결되는 배선(26)을 형성한다. 이때 상기 n 및 p형 영역(14,12)들은 각각 하나의 배선(26)과 연결되어 있다. (도 2c 참조).Thereafter, the second photoresist layer pattern 20 is removed, an interlayer dielectric layer 22 is formed on the entire surface of the structure, and then the interlayer dielectric layer 22 on the n and p-type regions 14 and 12 is removed. A contact hole 24 is formed, and a wire 26 connected to a power supply voltage of Vcc or Vss is formed through the contact hole 24. In this case, the n and p-type regions 14 and 12 are connected to one wire 26, respectively. (See FIG. 2C).
상기와 같이 형성된 디커플링 캐패시터는 도 3에 도시되어있는 바와 같이 n형 영역(14)이 Vcc와 연결되고, p형 영역(12)이 Vss와 연결되어 다수개의 병렬 연결된 디커플링 캐패시터를 구성하게 된다.As illustrated in FIG. 3, the decoupling capacitor formed as described above has an n-type region 14 connected to Vcc and a p-type region 12 connected to Vss to form a plurality of parallel-coupled decoupling capacitors.
이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 디커플링 캐패시터는 기판-게이트산화막-게이트전극으로 구성되는 종래 디커플링 캐패시터를 pn 접합형으로 구성하되, 각각의 영역이 인접하고, p 및 n형 영역이 각각 Vss 및 Vcc로 연결되며, 각각의 디커플링 캐패시터가 병렬 연결되도록 하였으므로, 적은 면적에큰 정전용량의 디커플링 캐패시터를 형성할 수 있어, 소자의 고집적화에 유리하고, 웨이퍼상의 넷다이수가 증가되어 생산 수율도 향상시킬 수 있는 이점이 있다.As described above, the decoupling capacitor of the semiconductor device according to the present invention comprises a conventional decoupling capacitor composed of a substrate-gate oxide film-gate electrode in a pn junction type, wherein each region is adjacent to each other, and the p and n-type regions are adjacent to each other. Each decoupling capacitor is connected in parallel, and each decoupling capacitor is connected in parallel, so that a large capacitance decoupling capacitor can be formed in a small area, which is advantageous for high integration of the device, and the number of net dies on the wafer is increased, thereby increasing the production yield. There is an advantage that can be improved.
Claims (4)
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| KR1020000034901A KR20020001017A (en) | 2000-06-23 | 2000-06-23 | Decoupling capacitor of semiconductor device and forming mothed thereof |
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| KR1020000034901A KR20020001017A (en) | 2000-06-23 | 2000-06-23 | Decoupling capacitor of semiconductor device and forming mothed thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100675281B1 (en) * | 2005-09-05 | 2007-01-29 | 삼성전자주식회사 | Semiconductor device having decoupling capacitor and method of fabricating the same |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100675281B1 (en) * | 2005-09-05 | 2007-01-29 | 삼성전자주식회사 | Semiconductor device having decoupling capacitor and method of fabricating the same |
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