KR20020000488A - Trench field shield in trench isolation - Google Patents

Abstract

PURPOSE: Provided is a structure and method for a semiconductor device which includes a substrate comprising trenches, a plurality of devices on the substrate isolated by the trenches, conductive sidewall spacers within the trenches, and an insulator filling the trenches between the conductive sidewall spacers. CONSTITUTION: A method of fabricating a semiconductor device includes forming a plurality of trenches in a substrate, forming a plurality of devices on a substrate, forming an insulating layer on the surface of the trenches, filling the trenches with a conductor, and etching the conductor from the trench to form conductive side wall spacers. Each of the sidewall spacers is individually capacitively coupled to an adjacent device.

Description

Trench field shield in trench isolation {TRENCH FIELD SHIELD IN TRENCH ISOLATION}

The present invention generally relates to independent isolation biasing of field shields in shallow trench isolation and actively isolated devices on a semiconductor chip.

Conventional electronic and computer systems use silicon wafers in which devices such as capacitors, resistors, and transistors are complexly arranged for microprocessing. The devices are placed on the surface of the silicon wafer, which is itself a conductor. Therefore, there is a need to separate regions of the wafer to prevent undesirable parasitic currents between adjacent devices.

Isolation is typically performed using a technique called shallow trench isolation (STI). STI involves identifying a region of the substrate 10 (eg, silicon) where no current is desired to flow. Then, a hole or shallow trench 13 is created as shown in Fig. 1A. Next, as shown in FIG. 1B, the trench is filled with an STI liner 1 and an insulator STI fill 2 (for example an oxide). The surface of the substrate 10 is planarized as shown in Fig. 1C. Devices (eg, transistor 15) are formed on the substrate 10. As shown in FIG. 1D, each device 15 includes a device gate 3, a device gate sidewall dielectric 4, and a device source / drain diffusion layer 5.

STI separates adjacent devices, but does not allow the electrical behavior of individual MOSFETs to be varied independently. Therefore, STI does not allow independent adjustment of the current-voltage characteristics of the individual devices.

As practiced in the prior art, the STI does not provide an electrical control element in the isolation region that can be used to selectively adjust the electrical characteristics of the individual MOSFETs. To achieve optimal performance in typical CMOS applications, a unique threshold voltage (Vt) is desirable for a particular device. For example, in DRAM applications, a relatively low threshold voltage (eg 0.4V) is desirable for certain high performance MOSFETs (eg, sense amplifiers, wordline drivers) that support (connected to) the actual memory array. . However, the memory array itself requires a MOSFET with a relatively high threshold voltage to prevent excessively large sub-Vt leakage. Large sub-Vt leakage currents degrade the data retention time of the storage capacitors in the array.

In addition, due to manufacturing tolerances, the threshold voltage may vary from chip to chip or from wafer to wafer. This variation is somewhat predictable due to the well-known spatial variation pattern of the processing means (ie implantation, etching, deposition). It is desirable to minimize this spatial variation in the threshold voltage.

Because of the need to selectively adjust individual threshold voltages, techniques such as selective ion implantation of dopant impurities and / or selective gate oxide thickness have been employed. These conventional means of adjusting the threshold voltage are expensive due to the additional mask and / or processing complexity.

Therefore, it is necessary to provide an isolation scheme between adjacent MOSFETs that can selectively adjust the threshold voltages of adjacent MOSFETs by using the built-in electric control element.

Another problem with STI is gap fill. Normally, the oxide is disposed in the STI region, but a gap may occur in the oxide that is a problem for semiconductor functions.

Therefore, there is a need for improved isolation that can independently control active devices on silicon wafers and reduce gap fill problems.

It is therefore an object of the present invention to provide a method and structure for a semiconductor device comprising a substrate comprising a trench, a plurality of devices on the substrate separated by the trench, conductive sidewall spacers in the trench, and insulators filling the trench between the conductive sidewall spacers. It is.

The invention also further includes a contact on the surface of the substrate, electrically connected to one of the conductive sidewall spacers, and a voltage source electrically connected to the contact. The voltage source can independently bias one of the plurality of devices.

In addition, the present invention provides a semiconductor device comprising: a first contact electrically connected to a first conductive sidewall spacer; And a second contact electrically connected to the second conductive sidewall spacer. By applying different voltages to the first conductive sidewall spacer and the second conductive sidewall spacer, one or more of the plurality of devices may be independently biased.

Insulators also separate conductive sidewall spacers. The first and second conductors can be field shields and can be under the top surface of the substrate.

The first contact may be equidistant between the first conductor and the second conductor.

The present invention also provides a method of forming a plurality of trenches in a substrate, forming a plurality of devices on the substrate, forming an insulating layer on the surface of the trench, filling the trench with a conductor; And etching the conductor from the trench to form conductive sidewall spacers. Each of the sidewall spacers is individually capacitively coupled to an adjacent device.

These and other objects, aspects, and advantages will be better understood through embodiments of the invention described below with reference to the drawings.

1A-1D are schematic diagrams illustrating passive STIs.

2 is a schematic diagram illustrating a shallow trench in a semiconductor substrate.

3 is a schematic diagram illustrating an STI liner and conductor fill.

4 is a schematic diagram illustrating field shield formation.

5 is a schematic diagram illustrating an STI fill.

6 is a schematic diagram illustrating the planarization process of the present invention.

7 is a schematic diagram illustrating devices of the present invention.

8A-8D are schematic diagrams illustrating variations in the contact field shield structure.

9A and 9B are top views of independent biasing of the present invention.

<Brief description of the main parts of the drawing>

1: STI liner

2: STI fill

3: device gate

4: sidewall dielectric

5: source / drain diffusion layer

10: substrate

13: trench

15: device

107: field shield (side wall spacer)

108: Contact

As described above, STIs are used to isolate regions of a silicon wafer and to prevent parasitic currents between active devices on the wafer. As such, the STI functions passively. A trench of nonconductive material is disposed between the areas of the wafer that need to be separated. Meanwhile, the present invention uses a shallow trench for active isolation of active devices on a silicon wafer.

As shown in FIG. 8A, the final structure of the present invention includes a substrate 100 (eg, silicon) that includes a trench 113. Each trench 113 is disposed side by side with an insulated STI liner 101. Field shields 107 (eg conductive sidewall spacers) are disposed on each sidewall of trench 113 and are separated by an insulator STI fill 116 (eg oxide).

The field shield 107 offers several advantages over the prior art, in particular the conventional passive STI. First of all, unlike passive STI, the present invention allows independent voltage control in areas within the substrate that provide several advantages. Devices on the substrate surface may be independently biased with independent threshold voltage control by receiving different voltages. Since passive STI lacks the field shield 107, it is not possible to provide selective control of this threshold voltage.

Independent biasing also reduces the sub-Vt leakage of devices that require maintaining data on the storage capacitor. In addition, the field shield 107 may bias the devices 115 independently of well doping. The field shield also allows for parasitic current control without high concentrations of doping. The field shield 107 may also be used as a local interconnect within the trench 115 or the field shield 107 itself.

The structure according to the invention further comprises a contact connected to the conductive field shield 107. The contacts may be in other forms. As shown in FIGS. 8A and 8B, the surface contact 108 may be disposed above the substrate 100, and the lower contact 109 may be disposed below the substrate 100. Depending on the structure of the trench 113, the field shields 107 may or may not be in contact with each other. When the field shields are in contact with each other, as shown in FIG. 8C, the center contact 111 may be disposed in the trench 113. If the shape of the trench 113 does not allow the field shields to contact each other, as shown in FIG. 8D, the direct contact 112 may be disposed on either side of the trench, and the field shield 107 may be in contact with the field shield 107. It may also be in direct contact. Although not shown, either the direct contact 112 or the center contact 112 may be disposed above or below the surface of the substrate 100.

Contacts 108, 109, 111, and 112 electrically capacitively coupled to devices 115 (eg, transistors) on substrate 100 have separate electrical connections to each of the field shields 107 from ground or other potential. To provide. As in the passive STI of FIG. 7, each device has a device gate 103, a device gate sidewall dielectric 104, and a source / drain diffusion layer 114. The independent connection between ground or potential and each field shield 107 and devices is made in such a way that one field shield is connected to one potential or ground and the other field shield is connected to another potential or ground. Each field shield 107 is then independently capacitively coupled to each device 115 (eg, via STI liner 101). Different potentials are placed on each field shield 117 and associated device 115 due to the independent connection of each potential or ground to the field shield 107 and the device 115, thereby resulting in independent biasing of the device 115. Is performed.

The present invention can be manufactured as one of several processes as is well known to those skilled in the art. For example, as shown in FIG. 2, as in the passive STI described above, the trench 115 is etched into the substrate 100 (eg, silicon), and the trenches 113 are insulated from the insulating STI liner 101. It is filled with laminations. However, in the present invention, unlike passive STI, instead of insulating fill 102, conductive fill 106 is deposited on STI liner 101 and trench 115. Conductor 106 may be one of conventional materials, such as doped polysilicon, tungsten silicide or titanium silicide or other materials well known to those skilled in the art. The conductor 106 is then etched and remains on both sidewalls of the trench 115 and is in contact with the sidewalls of the trench 115. Residual conductor 106 forms a conductive field shield 107 (eg, sidewall spacers). An insulator STI fill 116 (eg, oxide) is now deposited in the trench to cover the field shield 107, the trench 115, and the substrate 100.

Next, the upper surface of the device is planarized using chemical mechanical polishing (CMP) or other removal processes well known to those skilled in the art. The portion of the STI fill 116 disposed on the trench 113 is likewise removed.

As shown in FIGS. 9A and 9B, the device 115 is built on the surface of the substrate 100, and the contact 108 is deposited at a location in the trench 113 as described above, so that the contacts 108 are formed. Enable independent biasing of active devices. As will be apparent to those skilled in the art, the contacts may be formed in various structures based on the present invention. For example, contacts may be disposed on both sides of the trench 113 to contact each field shield 107 and extend over the surface of the substrate 100. In addition, the contacts may also extend below the trench, providing an electrical connection between the field field and the devices 110 below the surface of the substrate 100. The contacts may be equidistant from the field shields 107 or may contact the field shield 107 and the device 115.

Note that field shield contact 108 may be utilized by using several techniques, including forming a base contact, releasing the STI round rule, or holding a nitride pad on active region 114 until a contact is made. Shorting to the active silicon region may be prevented.

The present invention provides several advantages over the prior art, in particular the conventional passive STI. First of all, unlike passive STI, the present invention provides several advantages by enabling independent voltage control within substrate regions. Devices on the substrate surface receive different voltages and thus can be biased independently. For example, the voltage V1 may be applied to the first field shield 107 connected to the first device, and the voltage V2 may be applied to the second field shield 107 and the second device 115. In passive STI, this biasing is not possible due to the lack of field shield.

Independent biasing also reduces the sub-Vt leakage of the device connected to the data storage capacitor. The field shield 107 enables the voltage Va to be selectively applied only to the field shield adjacent to the transistor where threshold voltage adjustment is desired. When Va is applied to the field shield adjacent to the transistor, the threshold voltage of that transistor is suitable for the particular application. For example, when sufficient negative voltage is applied to the field shield adjacent to the NMOSFET, Vt is increased and leakage from the capacitor is reduced.

In addition, the field shield 107 may bias the device 115 independently of well doping. As the minimum feature size F of a DRAM array MOSFET is reduced, progressively higher channel doping concentrations are required to obtain a threshold voltage that ensures that off-current objectives (typically 1 fA / device) are met. However, experimentally peak channel topping concentrations above about 6.0 × 10 ¹⁷ cm ⁻³ eventually lead to a significant drop in retention time tail by the defect generation junction leakage mechanism. Therefore, it is desirable not to use peak channel topping concentrations greater than 6.0 × 10 ¹⁷ cm ⁻³ . In conventional STI, there was no way to avoid this high channel doping concentration while using zero volts for the word line low level. In the active isolation described herein, the field shield adjacent to the selected device (e.g., array MOSFET) is biased at sufficient negative potential, so that the threshold voltage is increased and the off-current is desired without exceeding the maximum allowable doping concentration. Is reduced to the level. Since the conductive field shield spacers adjacent to the NMOSFETs (formed in the P-wells) are biased with increasing negative potentials, the main carrier concentration (holes in the P-wells) in the MOSFET wells increases. In determining the threshold voltage of the MOSFET, the increase in the main carrier concentration is electrically equivalent to the increase in channel doping concentration. However, since the actual well doping has not been increased, increasing the main carrier concentration does not increase the bond induced junction leakage.

The present invention is very versatile and works with vertical devices, P-FETs, and N-FETs, although not specifically shown. In addition, as described above, the present invention has various contact structures. The field shield 107 may be made of many different materials.

The present invention allows for parasitic control without high concentration doping. One of the problems faced by STI is the parasitic MOSFET conduction at the silicon corners adjacent to the STI ("The Current-Carrying Corner Inherent to" by A. Bryant et al. In IEEE Eletron Device Letters, Vol. 14, No. 8, Aug. 1993). Trench Isolation ". Around the gate conductor at the silicon corner of a small radius of curvature (e.g. 5-20 nm) causes an increase in the gate field at the corner and a decrease in the corner threshold voltage relative to the threshold voltage away from the corner. This corner conduction is equivalent to a low Vt MOSFET in parallel with the MOSFET with the desired Vt. Isolation described herein may be used to reduce corner conduction phenomena. By selectively biasing the conductive spacer field shield adjacent to the channel edge of the MOSFET with parasitic corner conduction with sufficient negative potential, the Vt of the parasitic MOSFET may be increased than the Vt elsewhere in the device. This application of conductive spacer field shield isolation is particularly useful for MOSFETs with channel widths greater than 0.5 μm. For these relatively wide MOSFETs, corner Vt is substantially decoupled from Vt elsewhere in the channel, thereby allowing corner Vt to be increased without severely affecting Vt of the remaining device. For this application a minimal recess in the top of the conductive spacer below the top surface of the silicon substrate is desirable.

Field shield 107 may be used as a local interconnect within trench 115 or field shield 107 itself. Conductive spacers on the sidewalls of shallow trenches may be used to connect a plurality of relatively closely spaced structures to each other by providing additional wiring levels. For example, contacts to a portion of the conductive spacer can be made at multiple locations on the spacer. Each of the contacts may also be wired to a different structure. These contacts may be connected to the diffusion layer, the well region of the semiconductor substrate on which the MOSFET is formed, the gate conductor, or a higher metallization level.

Separation electrode formation of the field shield 107 reduces device shorts as compared to full metal filled with the field shield. In addition, the problem of gap fill is reduced, and the conductive material used as the field shield includes a metal and is of much more the same nature than other materials in conventional treated places in trenches. As a result, the gaps in the silicon substrate created by the trench etching are more easily filled.

Although the present invention has been described with reference to the preferred embodiments, it is obvious to those skilled in the art that the present invention can be modified without departing from the spirit and scope of the appended claims.

Claims (17)

In a semiconductor device, A substrate comprising a trench; A plurality of devices on the substrate, separated by the trenches; An insulating liner on the trench surface; Conductive sidewall spacers in the trench; And An insulator filling the trench between the conductive sidewall spacers A semiconductor device comprising a. The method of claim 1, A contact on the surface of the substrate, electrically connected to one of the conductive sidewall spacers; And A voltage source electrically connected to the contact More, And the voltage source is capable of independently biasing one of the plurality of devices. The method of claim 1, A first contact electrically connected to the first conductive sidewall spacer; And A second contact electrically connected to a second conductive sidewall spacer More, At least one of the plurality of devices is independently biased by applying different voltages to the first conductive sidewall spacer and the second conductive sidewall spacer. In a semiconductor device, A substrate comprising a trench; A plurality of devices on the substrate separated by the trenches; An insulating liner on the surface of the trench; Conductive sidewall spacers; And An insulator filling the trench between the conductive sidewall spacers Including, A first conductive sidewall spacer is electrically connected to a first one of the plurality of devices, a second conductive sidewall spacer is electrically connected to a second one of the plurality of devices, and the first device is connected to the second device; Is a semiconductor device that can be biased independently. The semiconductor device of claim 4, further comprising a first contact extending over the surface of the substrate. The semiconductor device according to claim 5, wherein the first contact makes a first device of the plurality of devices contact the first conductive sidewall spacer. The semiconductor device according to claim 1 or 4, wherein the insulator separates the conductive sidewall spacers. The semiconductor device of claim 1, wherein the conductive sidewall spacer comprises a field shield. The semiconductor device of claim 1, wherein the conductive sidewall spacer is below an upper surface of the substrate. The semiconductor device of claim 1, further comprising a first contact in contact with one of the conductive sidewall spacers. In the method of manufacturing a semiconductor device, Forming a plurality of trenches in the substrate; Forming a plurality of devices on the substrate; Forming an insulating liner on the surface of the trench; Filling the trench with a conductor; And Etching the conductor from the trench to form conductive sidewall spacers Including, Each of the sidewall spacers is individually connected to an adjacent device of the device. 12. The method of claim 11, further comprising forming a first contact on a surface of the substrate that is connected to one of the conductive sidewall spacers. The method of claim 12, wherein the first contact is formed to contact a first device of the plurality of devices and one of the conductive sidewall spacers. 12. The method of claim 11, further comprising forming an insulator in the trench between the conductive sidewall spacers. 12. The method of claim 11 wherein the conductive sidewall spacer comprises a field shield. 12. The method of claim 11, wherein the conductive sidewall spacer is below an upper surface of the substrate. The method of claim 12, wherein the first contact is between the conductive sidewall spacers.