KR0175328B1 - Semiconductor device and its fabrication - Google Patents

Abstract

Forming a plurality of conductive layers and a dielectric layer in the trench in which the insulating layer is formed; Providing insulating spacers on sidewalls of the conductive layers and the dielectric layers in trench depth directions to connect the spaced dielectric layers; And installing the conductive side spacers next to the insulating spacers so as to connect the plurality of spaced conductive layers to each other so that the charge accumulation electrode and the plate electrode for the capacitor are formed around the dielectric layer formed according to the trench. It relates to a semiconductor device manufacturing method.

Description

Semiconductor device and manufacturing method thereof

1A to 1E are manufacturing process diagrams showing a conventional method for manufacturing a semiconductor memory device.

2 (a) to 2 (f) are process drawings showing the manufacturing procedure of the semiconductor capacitor device according to the present invention.

3 (a) to 3 (f) are cross-sectional views of an increased capacitance semiconductor capacitor device according to the present invention.

4 is a cross-sectional structure diagram of a semiconductor memory device including the capacitor of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor capacitor and a fabrication having a stacked trench structure according to trench formation.

The semiconductor memory device uses a semiconductor capacitor as information storage means and constitutes one memory cell together with a switching receiver which is a controlled signal transmission means connected thereto. Many proposals have been made for the improvement of the capacitor's storage capacity due to the high integration of the circuit and the reduction of the device.

In order to increase the density of memory devices such as DRAM (dynamic-RAM), it is necessary to obtain a sufficient storage capacity in a small cell area. Accordingly, three-dimensionalization of the memory cell structure, that is, three-dimensional accumulation electrode represented by trench type or stack type Is being tried.

In order to increase the accumulation capacity in stack type cells having high soft error resistance or diversity of the shape of the storage electrode, there is a method of using the electrode side by increasing the storage electrode. Is a disadvantage of the photolithography process, and as a countermeasure, a structure having increased surface area by studying the shape of the storage electrode has been proposed. This structure is an effective means for lowering the height of the storage electrode, but the manufacturing process is complicated.

A series of process steps shown in FIGS. 1A to 1E illustrate a conventional stacked high-capacity semiconductor capacitor fabrication process and is shown in conjunction with memory cell fabrication.

First, as shown in FIG. 1A, the isolation region 202, the diffusion region 204, and the channel stopper 203 are formed on the P-type silicon substrate 201, and then the gate oxide layer 205 is formed. ), The gate electrode portion of the MOS transistor including the gate polysilicon 206 and the oxide spacer 207 is formed, and the oxide film 208 of 2000 과 and the silicon nitride film 209 of 500, and the first oxide film 210 of 500 Å thick are formed thereon. Laminated in turn.

Subsequently, as shown in FIG. 1 (b), contact holes are formed to connect the impurity diffusion region 204 and the capacitor, which is a capacitor formed later, and the first conductive film 211 of polysilicon is laminated to a thickness of 500 Å. A 500 nm thick second oxide film 212, a 500 mm thick second conductive film 213, and a 500 mm thick third oxide film 214 are stacked in this order.

In the step of FIG. 1 (b), the pattern 215 is formed by etching by photolithography, and as shown in FIG. 3 (c), the third oxide film 214, the second conductive film 213 and the second oxide film are formed. 212 and the first conductive film 211 are sequentially dry-etched.

Next, as shown in FIG. 1D, after removing the photoresist layer, the doped polysilicon is laminated and the poly spacer 216 is left as an etch back. Subsequently, one poly spacer is sealed by photolithography using the photoresist layer 217.

Subsequently, the opened polysilicon spacer is etched in step (d) of FIG. 1 and the open oxide film is completely removed by wet etching. Next, as shown in FIG. 1E, the surfaces of the first and second conductive films 211 and 213 are thermally oxidized to form an oxide film 218, and the doped polysilicon is filled to form a capacitor.

Information recording and reading is performed by the charge accumulation electrode, the impurity diffusion region which is the source / drain region of the MOS transistor, and the bit line connected through the contact portion and connected to the other electrode. The operation of recording and reading information is performed by charging and discharging between the cell plate electrode and the charge storage electrode to which the fixed potential is applied.

According to this conventional technology, by using polysilicon as the charge storage electrode of a multilayer stacked stacked capacitor, it is impossible to increase one layered capacitance in the same area due to the polysilicon filling property. In order to increase the capacitance, a multi-layered charge storage electrode must be used, but the terminals increase. In the case of ultra-high density semiconductor devices, since the contact size is extremely narrow, the thickness of the stack is limited and the thickness of the charge storage electrode needs to be small to increase the number of stacks. In this case, the charge storage electrode in the case of spin-drying after wet etching with oxide This too thin causes a problem in that the pattern is deformed like the hair or the original state is not adhered to the side wall. In addition, there is a problem in that the thickness of polysilicon grains increases after the dielectric film is formed by reverse oxidation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a capacitor having a stacked trench structure in order to solve the above problems and to draw a semiconductor capacitor capable of maximizing capacitance per unit area.

According to an aspect of the present invention, there is provided a method of manufacturing a high-capacity semiconductor capacitor device, including: forming a plurality of conductive layers and a dielectric layer in a trench in which an insulating layer is formed; Providing insulating spacers on sidewalls of the conductive layers and the dielectric layers in trench depth directions to connect the spaced dielectric layers; And installing the conductive layer side spacers after the insulating spacers so as to connect the plurality of spaced apart conductive layers to each other so that the charge accumulation electrode and the plate electrode for the capacitor are formed on the dielectric layer formed according to the trench. It features.

The structure of the semiconductor capacitor device of the present invention formed by the above method includes a conductive layer and a dielectric layer patterned alternately in multiple layers in a trench in which an insulating layer is formed, and a sidewall insulating spacer and a sidewall conductive layer where the dielectric layer and the conductive layer are connected at sidewalls of the pattern. Comprising a spacer of a stacked trench structure to form a capacitor, the conductive side wall spacer is characterized in that it is connected to other elements.

When the present invention is explained from the above process, when the polysilicon is used as the charge storage electrode in the trench, due to the refilling property of the polysilicon, the dielectric layer area between the electrodes is drastically reduced in the multilayered layer so that the capacitance is reduced. The problem is overcome by the use of amorphous silicon, which has a property of stacking substantially uniformly along the step, and furthermore, since it is not a particulate material, the surface is uniform and smooth. In addition, during the thermal oxidation (doped) amorphous silicon to form a silicon oxide film to be used as a dielectric film is converted to polysilicon, even after thermal oxidation, the initial stacked form is maintained.

In the conventional invention, the thickness of the charge storage electrode cannot be made very thin, which is a problem, but the terminal outside the trench is maintained within 1000 mV even after the multilayer lamination and thermal oxidation according to the thin thickness and the minimum thermal oxidation thickness that can be stacked from the process of the present invention. The problem is solved.

In addition, in the conventional case, the capacitance can be increased by the surface terminal, the number of laminations, and the thickness of the dielectric film. However, in the present invention, the capacitance can be increased by increasing the depth of the trench and does not affect the surface step during the process.

According to the present invention, the oxide film and the silicon nitride film are used in the trench, thereby contributing not only to the capacitor but also to the isolation trench isolation.

When a voltage according to the voltage difference is applied between the two electrodes of the capacitor The charge is charged to the dielectric medium in the same amount. Where ε ₁ is the dielectric constant of the dielectric medium, C is the charge amount, d is the thickness of the dielectric medium, and s is the area where the two electrodes overlap. When the voltage applied to the capacitor is removed, the charge charged in the dielectric medium is discharged. Such charge and discharge operations are repeated to be used as compensation charges for active devices or as a source of refresh charges for DRAMs. Since the amount charged in the above-mentioned formula is proportional to the area s, in the present invention, the capacitance per unit area can be dramatically increased by increasing the depth of the trench and the number of laminations.

Specific process charts for the present invention are as shown in Figs. 2 (a) to (f) as preferred embodiments. Next, the present invention will be described in detail with reference to the drawings.

First, a first relief oxide film 102 is formed on the prepared silicon substrate 10 by a thermal oxidation method, and the silicon nitride film 103 is laminated by a chemical vapor deposition (CVD) method. Next, the trench capacitor pattern T is formed by a photolithography method to form trenches defined according to the size of the capacitor, as shown in FIG. This is to etch the silicon nitride film 103 and the relief oxide film 102 by a dry etching method such as reactive ion etching (RIE) and trench etch the exposed silicon substrate 101 after patterning the photoresist layer and patterning the capacitor pattern. . The required resist layer is removed and the silicon oxide film 104 is grown by thermal oxidation on the trench inner surface.

Next, as shown in FIG. 2 (b), the silicon nitride film 103 is completely removed by etching, and the silicon nitride film 105 is laminated over the entire surface as a first insulating layer. Subsequently, a layer of doped amorphous silicon, which provides a so-called good step coverage having a property of stacking the surface and sides almost uniformly, is laminated, and the upper surface of the film is thermally oxidized to form a first dielectric film 107 and at the same time the amorphous silicon Is made of polysilicon 106 from the heat, which becomes the first conductive layer.

Similarly, the doping of amorphous silicon and thermal oxidation are repeated two more times to form the second conductive layer 108, the second dielectric layer 109, the third conductive layer 110, and the second relief oxide layer 111. The silicon nitride film 112 is laminated as the second insulating layer.

Subsequently, a pattern is formed by photolithography to form one electrode of the trench capacitor, as shown in FIG. 2 (c), and the second insulating layer 112, the relief oxide film 111, and the third conductive layer are formed by a dry etching method of RIE. The layer 110, the second dielectric film 109, the second conductive layer 108, and the second dielectric film 107 are etched. Next, the used photoresist film is removed, the silicon oxide film is laminated, and the silicon spacer 113 is left as an etch back. Subsequently, in order to open the opposite side of the trench capacitor, after the photolithography operation, the silicon nitride film 112 is etched down to the relief oxide film 102 by the RIE method and the photoresist is removed.

Subsequently, as illustrated in FIG. 2D, the silicon nitride film 112 is completely etched and the silicon oxide film 114 is entirely stacked. After the silicon oxide layer 114 is stacked, the side surface portion of the silicon oxide layer spacer 113 is etched by RIE until the second dielectric layer is exposed, leaving the spacer 115 at the same time. These two spacers 115 and 116 separate two electrodes of the trench capacitor as shown in FIG. 2E and serve as dielectric films.

Then, poly spacers 117 and 118 are formed by a doped polysilicon stack as shown in FIG. 2 (f) and dry etching such as RIE to connect the first conductive layer and the third conductive layer, and the other It is used as an electrode connecting 2 conductive layers and active element. At the same time, it is used as two electrodes of the trench capacitor. Subsequently, the silicon oxide film 119 is laminated with the third insulating layer, and the contact portion is formed and the primary metal layer 120 is formed to complete the trench capacitor by patterning.

Although connected in FIG. 2 (f), the third dielectric film 411 and the fourth conductive layer 412 in the trench are connected as shown in FIG. 3 to obtain a larger capacity for the formation of two dielectric layers in the trench. The process may be repeated to add three layers of dielectric layers. The sign of FIG. 2 and the sign of FIG. 2 (f) are equally assigned to the same configuration. However, further film formation can be formed within a given range.

As shown in FIG. 4, the semiconductor capacitor of the present invention is connected to the MOSFET (M), which is a switching element, and is used as a semiconductor memory device. The MOSFET M includes a gate electrode 340, a source / drain 360, 361, and a gate insulating layer 330.

According to the present invention, it is possible to realize a device having a maximum capacitance with a minimum area by application to a VLSI class semiconductor memory device.

Claims (8)

Forming a plurality of conductive layers and a dielectric layer in the trench in which the insulating layer is formed; Providing insulating spacers on sidewalls of the conductive layers and the dielectric layers in trench depth directions to connect the spaced dielectric layers; And installing the conductive side spacers after the insulating spacers so as to connect the plurality of spaced apart conductive layers to each other so that the charge accumulation electrode and the plate electrode for the capacitor are formed on the dielectric layer formed according to the trench. A semiconductor device manufacturing method. The method of claim 1, wherein the conductive layer and the dielectric layer formed in the trench are laminated with a doped amorphous silicon layer, and the doped amorphous silicon layer is doped polysilicon at a high temperature due to thermal oxidation. A semiconductor device manufacturing method. The method of claim 1, wherein the insulating sidewall spacer is formed on the final conductive layer formed in the trench, the silicon oxide layer is stacked, the spacer is etched, and after the removal of the silicon nitride layer, the silicon oxide layer is laminated on the entire surface. After etching by dry etching, the two dielectric layers on one side are connected to the sidewall silicon oxide layer, and the other side is such that the insulating layer inside the trench and the lower dielectric layer are connected to each other by the sidewall silicon oxide layer. A semiconductor device manufacturing method. The method of claim 1, wherein the conductive sidewall spacers are formed by laminating polysilicon doped on the entire surface of the conductive layers exposed after the insulating spacers are formed by dry etching. The method of claim 1, wherein the conductive spacer is connected to another device. 6. The method of claim 5, wherein the connection is made with a switching element to form a semiconductor memory element. A capacitor having a stacked trench structure comprising a conductive layer and a dielectric layer alternately patterned in a multi-layered trench in which an insulating layer is formed, sidewall insulating spacers and sidewall conductive spacers connecting dielectric layers and conductive layers at sidewalls of the pattern, And the sidewall spacers are connected to other elements. 8. The semiconductor capacitor device as claimed in claim 7, wherein the conductive layer and the sidewall conductive spacers in the trench are polysilicon and the dielectric layer and the sidewall insulating spacer are formed of silicon oxide.