KR100532942B1 - Semiconductor memory device having a vertical structure type transistor and method of manufacturing the same - Google Patents

Abstract

The present invention discloses a semiconductor memory device having a vertical structure transistor capable of achieving high integration, high speed, and low power, and a manufacturing method thereof. A semiconductor memory device having a vertical structured transistor of the present invention disclosed includes a base substrate; An investment oxide film disposed on the base substrate; Field oxide films formed in an upper surface of the buried oxide film; First insulating layers formed on a portion of the field oxide layer and a portion of the buried oxide layer adjacent to the buried oxide layer; A capacitor formed in the buried oxide film and having a storage node electrode having one surface exposed to an area between the first insulating layers, a dielectric layer and a plate electrode surrounding the storage node electrode; A source region formed on the exposed storage node electrode; A second insulating film formed on the first insulating film and the field oxide film to have the same thickness as the source region; A channel region formed on the source region; A gate oxide layer formed to surround a portion of an upper surface and a side of the channel region; A gate electrode formed on a side of the gate oxide film; A drain region formed on the channel region; A third insulating film formed on the gate electrode, the gate oxide film, and the second insulating film at the same height as the drain region; A fourth insulating film formed on the third insulating film and the drain region; And a word line and a bit line formed on the fourth insulating layer to be in contact with the gate electrode and the drain region, respectively.

Description

Semiconductor memory device having a vertical structure type transistor and method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a semiconductor memory device having a vertical structure transistor that forms a transistor in a vertical structure by using a selective silicon growth method, and a method of manufacturing the same.

As the demand for high integration, high speed, and low power of semiconductor memory devices increases, various researches on them are being conducted in terms of devices and circuits. By the way, in terms of devices, a conventional integrated technology using a silicon substrate made of bulk silicon has a high speed and a low power semiconductor memory device. However, there is a limitation, and as a solution thereof, SOI (Silicon On Insulator) The integration technology using a board | substrate is drawing attention.

The SOI substrate is a structure in which an investment oxide film is interposed between the base substrate supporting the whole and the semiconductor layer on which the device is formed. The device integrated on the SOI substrate (hereinafter referred to as SOI device) is a device integrated on the silicon substrate. In comparison, it has advantages such as high speed due to small junction capacitance, low voltage due to low threshold voltage, and elimination of latch-up due to complete device isolation.

However, even when using an SOI substrate, the semiconductor memory device has a limitation in obtaining high integration, high speed, and low power, based on the following reasons.

The increase in the degree of integration of the semiconductor memory device is accompanied by a decrease in the gate electrode length of the transistors formed in the cell region and the peripheral circuit region, in which case the height of the capacitor is rather increased to obtain a satisfactory capacitor capacity. In other words, the capacitance of the capacitor is inversely proportional to the distance between the capacitor electrodes called the storage node electrode and the plate electrode, and is proportional to the area of the capacitor electrode and the dielectric constant of the dielectric layer. This means that it is necessary to increase the height of the capacitor electrode to compensate for this.

However, increasing the height of the capacitor causes an increase in the step height between the cell area and the peripheral circuit area, which makes it very difficult to form contact holes in the peripheral circuit area during subsequent metallization processes. do. In addition, since the reduction of the gate electrode length, as is well known, results in a short channel effect that degrades device characteristics, an improvement in terms of device fabrication and process equipment is required to improve such short channel effects. This must be accompanied. However, at the present time, due to limitations in process equipment and difficulty in device design, it is substantially very difficult to improve the short channel effect described above. Therefore, without solving the above problems, it is not possible to achieve high integration, high speed, and low power of the semiconductor memory device.

Accordingly, the present invention has been made to solve the above problems, the vertical structure that can prevent the difficulty of the process due to the step between the cell area and the peripheral circuit area, and the deterioration of device characteristics due to the short channel effect There is provided a semiconductor memory device having a transistor and a method of manufacturing the same.

A semiconductor memory device having a vertical structured transistor of the present invention for achieving the above object is a base substrate; An investment oxide film disposed on the base substrate; Field oxide films formed in an upper surface of the buried oxide film; First insulating layers formed on a portion of the field oxide layer and a portion of the buried oxide layer adjacent to the buried oxide layer; The buried oxide layer is buried in the buried oxide layer, and a storage node electrode having one surface exposed to an area between the first insulating layers, and formed to surround the storage node electrode without being exposed by the first insulating layer in the buried oxide layer. A capacitor comprising a plate electrode and a dielectric layer formed between the storage node electrode and the plate electrode; A source region formed of a silicon epitaxial layer doped with impurities on the storage node electrode; A second insulating film formed on the first insulating film and the field oxide film to have the same thickness as the source region; A channel region formed of a silicon epitaxial layer on the source region; A gate oxide layer formed to surround a portion of an upper surface and a side of the channel region; A gate electrode formed to surround a side of the gate oxide film on the second insulating film; A drain region formed of a silicon epitaxial layer doped with impurities on the channel region; A third insulating film formed on the second insulating film at the same height as the drain region to cover the gate electrode; A fourth insulating film formed on the third insulating film and the drain region; And a word line and a bit line formed on the fourth insulating layer and contacted with the gate electrode and the drain region, respectively.

In addition, a method of manufacturing a semiconductor memory device having a vertical structured transistor of the present invention for achieving the above object comprises the steps of forming field oxide films on a silicon substrate; Forming a first insulating film on the field oxide film and a portion of the silicon substrate adjacent to the field oxide film; A storage node electrode disposed on the first insulating layer portion in contact with the exposed portion of the silicon substrate, a dielectric layer surrounding the storage node electrode, and a plate electrode disposed on the first insulating layer covering the dielectric layer Forming a capacitor consisting of; Forming a buried oxide film on the field oxide film to cover the plate electrode; Bonding a base substrate on the buried oxide film; Removing the silicon substrate to expose the storage node electrode; Growing a first silicon epitaxial layer doped with impurities on the exposed storage node electrode to a predetermined thickness; Forming a second insulating film on the field oxide film and the first insulating film to the same thickness as the first silicon epi layer; Growing a second silicon epitaxial layer doped with impurities on the first silicon epitaxial layer to a predetermined thickness; Forming a gate oxide film in a form of enclosing a side surface while exposing an upper portion of the second silicon epitaxial layer; Forming a gate electrode on the second insulating layer to surround a portion of the gate oxide layer; Forming a third insulating layer on the second insulating layer to cover the gate electrode and the gate oxide layer; Etching the third insulating layer and the gate oxide layer to expose the second silicon epitaxial layer; Growing a third silicon epi layer doped with impurities to the same height as the third insulating layer on the exposed second silicon epi layer; Forming a fourth insulating layer having a contact hole exposing the third silicon epitaxial layer and a gate electrode on the resultant; And forming a word line in contact with the gate electrode and a bit line in contact with the third silicon epitaxial layer on the fourth insulating layer.

According to the present invention, the capacitor is provided in the form buried in the buried oxide film, and because the transistor is formed in a vertical structure by using the silicon epitaxial growth method, it is possible to prevent the generation of steps between the cell region and the peripheral circuit region, In addition, the occurrence of the short channel effect due to the shortening of the gate electrode length can be prevented.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1G are cross-sectional views illustrating a method of manufacturing an SOI device according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, field oxide films 2 are formed on a silicon substrate 1 by using a known LOCOS process or a shallow trench isolation process. Then, a first insulating film 3 is formed on the silicon substrate 1 to a thickness covering the field oxide films 2, and then the first insulating film 3 is etched and patterned by a known etching process. do. At this time, the first insulating film 3 is present only on the field oxide film 2 and the portion of the silicon substrate 1 adjacent thereto so that a portion of the silicon substrate 1 therebetween is exposed.

Next, a polysilicon film doped with a predetermined impurity is deposited on the entire surface, and patterned to form the storage node electrode 4, and then the dielectric layer 5 is formed to surround the storage node electrode 5. Subsequently, a plate electrode 6 made of a polysilicon film doped with a predetermined impurity is formed next to surround the dielectric layer 5. As a result, a capacitor 10 composed of the storage node electrode 4, the dielectric layer 5, and the plate electrode 6 is formed. Then, the buried oxide film 7 which is a planarization and bonding medium is formed on the entire surface of the resultant.

Referring to FIG. 1B, a base substrate 11 for supporting the whole is provided, and the base substrate 11 is bonded onto the investment oxide film 7 described above.

Referring to FIG. 1C, a silicon substrate is subjected to grinding and chemical mechanical polishing (CMP) processes to expose the storage node electrode 4, the field oxide film 2, and the first insulating film 3. Remove it.

Referring to FIG. 1D, the first silicon epitaxial layer 12 doped with impurities is grown to a predetermined thickness on a storage node electrode 4 made of a polysilicon layer using a known selective silicon epitaxial growth method. In this case, the first silicon epitaxial layer 12 is a portion which will be a source region later. Then, the CVD oxide film is deposited on the entire upper portion with a thickness covering the first silicon epitaxial layer 12, and then the CVD oxide film is polished by a CMP process so as to have the same height as the first silicon epitaxial layer 12. A second insulating film 13 made of a CVD oxide film is formed on the side of the first silicon epitaxial layer 12.

Referring to FIG. 1E, a second silicon epitaxial layer 14 which is not doped with impurities is grown on the exposed first silicon epitaxial layer 12 using the selective silicon epitaxial growth method. In this case, the second silicon epitaxial layer 14 is a portion which will be a channel region afterwards. In addition, the second silicon epitaxial layer 14 to be a channel region is grown to have a cylindrical or square pillar shape. Subsequently, the gate oxide film 15 is formed to surround the second silicon epitaxial layer 14.

Then, a conductive film, such as a doped polysilicon film or a predetermined metal film, is deposited on top of the resultant, and then the conductive film is polished by a CMP process, and subsequently, until the gate oxide film 15 is exposed. The conductive layer is etched to form a gate electrode 16 that surrounds the gate oxide layer 15 on the side of the second silicon epitaxial layer 14. In this case, for example, when the second silicon epi layer 14 to be a channel region is cylindrical, the gate electrode 16 is formed in the same cylindrical shape, and the second silicon epi layer 14 is a square pillar. In the case it is formed in the same square pillar shape.

Referring to FIG. 1F, a third insulating layer 17 is formed on the resultant, and the third insulating layer 17 and the gate oxide layer 15 are etched by a known photolithography process to form a second silicon epitaxial layer 14. To form a hole exposing Thereafter, a third silicon epitaxial layer 18 doped with impurities for filling the holes is grown on the second silicon epitaxial layer 14 exposed by the selective silicon epitaxial growth method. Here, the third silicon epitaxial layer 18 is a portion to be a drain region.

Referring to FIG. 1G, a fourth insulating layer 19 is formed on the third insulating layer 17 and the third silicon epitaxial layer 18, and then the fourth insulating layer is etched to form the third silicon epitaxial layer ( A bit line contact hole exposing 18) is formed. Then, a metal film is formed on the fourth insulating film 19 so that the bit line contact hole is filled, and then the metal film is patterned to contact the third silicon epitaxial layer 18. By forming the semiconductor device, the semiconductor memory device having the vertical structure transistor according to the embodiment of the present invention is completed.

Although not shown, an etching for exposing the gate electrode 16 is also performed during the etching of the fourth insulating layer 19 for exposing the third silicon epitaxial layer 18 and the metal pattern 20. ) Contacts the gate electrode 16 as well as the third silicon epi layer 18.

Accordingly, the metal pattern 20 may be a word line connecting the gate electrodes and a bit line connecting the drain regions.

2 is a plan view illustrating an arrangement of memory cells in a semiconductor memory device manufactured according to an embodiment of the present invention.

As shown, the cells arranged in the form of enclosing the channel region (not shown) of the gate electrode 16 and horizontally arranged on the same line are connected to each other by the word line 21 contacted with the gate electrode 16. The cells arranged vertically on the same line are connected to each other by the bit line 22.

The semiconductor memory device according to the embodiment of the present invention having the above structure has the following advantages.

First, since the channel region is formed by the selective silicon epitaxial growth method, the defect density is smaller than that of the bulk silicon, and therefore, the mobility of the device can be increased, thereby obtaining a high speed device.

Second, since the gate electrode is provided in a form surrounding the channel region, the short channel effect is prevented due to the increase in the length of the substantially gate electrode, and the current driving force is also provided because the carrier is moved through the entire channel region. Due to being able to increase, the power consumption of the memory element can be reduced.

Third, since the transistor is provided in a vertical structure, the integration degree of the memory device can be significantly improved.

Fourth, since the capacitor is formed in a buried form, it is possible to prevent the generation of a step between the cell region and the peripheral circuit region, thereby stabilizing subsequent processes.

As described above, according to the present invention, since the transistor is formed in a vertical structure by using the silicon epitaxial growth method, it is possible to satisfy the characteristics required for high integration, high speed, and low power, and the capacitor is provided in a buried form. Therefore, it is possible to prevent the generation of steps between the cell area and the peripheral circuit area. Therefore, when using the present invention, it can be very advantageously applied to the production of high performance devices.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor memory device in accordance with an embodiment of the present invention.

2 is a plan view showing an arrangement of memory cells in a semiconductor memory device formed in accordance with an embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

1 silicon substrate 2 field oxide film

3: first insulating film 4: storage node electrode

5: dielectric layer 6: plate electrode

7: investment oxide film 10: capacitor

11: base substrate 12: first silicon epi layer

13 second insulating film 14 second silicon epi layer

15 gate oxide film 16 gate electrode

17: third insulating film 18: third silicon epi layer

19: fourth insulating film 20: metal pattern

21: word line 22: bit line

Claims (17)

A base substrate; An investment oxide film disposed on the base substrate; Field oxide films formed in an upper surface of the buried oxide film; First insulating layers formed on a portion of the field oxide layer and a portion of the buried oxide layer adjacent to the buried oxide layer; The buried oxide layer is buried in the buried oxide layer, and a storage node electrode having one surface exposed to an area between the first insulating layers, and formed to surround the storage node electrode without being exposed by the first insulating layer in the buried oxide layer. A capacitor comprising a plate electrode and a dielectric layer formed between the storage node electrode and the plate electrode; A source region formed of a silicon epitaxial layer doped with impurities on the storage node electrode; A second insulating film formed on the first insulating film and the field oxide film to have the same thickness as the source region; A channel region formed of a silicon epitaxial layer on the source region; A gate oxide layer formed to surround a portion of an upper surface and a side of the channel region; A gate electrode formed to surround a side of the gate oxide film on the second insulating film; A drain region formed of a silicon epitaxial layer doped with impurities on the channel region; A third insulating film formed on the second insulating film at the same height as the drain region to cover the gate electrode; A fourth insulating film formed on the third insulating film and the drain region; And And a word line and a bit line formed on the fourth insulating layer and contacted to the gate electrode and the drain region, respectively. The semiconductor memory device of claim 1, wherein the storage node electrode and the plate electrode are formed of a doped polysilicon film. delete 2. The semiconductor memory device of claim 1, wherein the channel region is formed of an undoped silicon epi layer. 5. The semiconductor memory device according to claim 1 or 4, wherein the channel region is cylindrical. 6. The semiconductor memory device of claim 5, wherein the gate electrode is cylindrical. 5. The semiconductor memory device of claim 1 or 4, wherein the channel region has a rectangular pillar shape. 8. The semiconductor memory device of claim 7, wherein the gate electrode has a rectangular pillar shape. The semiconductor memory device of claim 1, wherein the gate electrode is formed of a doped polysilicon film or a metal film. Forming field oxide films on the silicon substrate; Forming a first insulating film on the field oxide film and a portion of the silicon substrate adjacent to the field oxide film; A storage node electrode disposed on the first insulating layer portion in contact with the exposed portion of the silicon substrate, a dielectric layer surrounding the storage node electrode, and a plate electrode disposed on the first insulating layer covering the dielectric layer Forming a capacitor consisting of; Forming a buried oxide film on the field oxide film to cover the plate electrode; Bonding a base substrate on the buried oxide film; Removing the silicon substrate to expose the storage node electrode; Growing a first silicon epitaxial layer doped with impurities on the exposed storage node electrode to a predetermined thickness; Forming a second insulating film on the field oxide film and the first insulating film to the same thickness as the first silicon epi layer; Growing a second silicon epitaxial layer doped with impurities on the first silicon epitaxial layer to a predetermined thickness; Forming a gate oxide film in a form of enclosing a side surface while exposing an upper portion of the second silicon epi layer; Forming a gate electrode on the second insulating layer to surround a portion of the gate oxide layer; Forming a third insulating layer on the second insulating layer to cover the gate electrode and the gate oxide layer; Etching the third insulating layer and the gate oxide layer to expose the second silicon epitaxial layer; Growing a third silicon epi layer doped with impurities to the same height as the third insulating layer on the exposed second silicon epi layer; Forming a fourth insulating layer having a contact hole exposing the third silicon epitaxial layer and a gate electrode on the resultant; And Forming a word line in contact with the gate electrode and a bit line in contact with the third silicon epitaxial layer on the fourth insulating layer. The method of claim 10, wherein the storage node electrode and the plate electrode are formed of a doped polysilicon film. The method of claim 10, wherein the second silicon epitaxial layer is formed in a cylindrical shape. The method of claim 12, wherein the gate electrode is formed in a cylindrical shape. The method of claim 10, wherein the second silicon epitaxial layer has a rectangular pillar shape. 15. The method of claim 14, wherein the gate electrode is formed in a rectangular pillar shape. 11. The method of claim 10, wherein the gate electrode is formed of a doped polysilicon film or a metal film. The method of claim 10, wherein the forming of the gate electrode comprises: forming a conductive film on the first insulating film to cover the gate oxide film; Polishing the conductive film to expose the gate oxide film; And etching the polished conductive film to remain around the gate oxide film.