KR200187486Y1 - Semiconductor package - Google Patents

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Publication number
KR200187486Y1
KR200187486Y1 KR2019980005946U KR19980005946U KR200187486Y1 KR 200187486 Y1 KR200187486 Y1 KR 200187486Y1 KR 2019980005946 U KR2019980005946 U KR 2019980005946U KR 19980005946 U KR19980005946 U KR 19980005946U KR 200187486 Y1 KR200187486 Y1 KR 200187486Y1
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South Korea
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lead
chip
package
semiconductor chip
semiconductor
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KR2019980005946U
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Korean (ko)
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KR19990039617U (en
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이현일
안희영
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 고안은 반도체 패키지에 관한 것으로, 본 고안은 리드 프레임의 패들 상면에 접착제에 의해 고정된 상태로 부착되는 반도체 칩과, 상기 반도체 칩의 상면에 요입되어 형성되는 복수개의 칩패드와, 상기 칩패드와의 사이에 각각 열과 압력을 가하면 전도성 물질 끼리 연결이 되어 전기가 통하도록 이방성 전도 테이프에 의해 본딩되는 인너 리드와, 상기 반도체 칩과 패들 및 인너 리드의 일정 부분을 감싸도록 형성된 몰딩부의 외측에 각각의 인너 리드에 연장되어 일체로 돌출 형성되는 아웃 리드를 포함하여 구성된 것을 그 특징으로 한다.The present invention relates to a semiconductor package, the present invention is a semiconductor chip that is attached to the upper surface of the paddle of the lead frame fixed by an adhesive, a plurality of chip pads formed by being inserted into the upper surface of the semiconductor chip, and the chip pad When heat and pressure are respectively applied between the inner and outer leads, the inner leads bonded by the anisotropic conductive tape so as to be electrically connected to each other, and the outer side of the molding part formed to surround a portion of the semiconductor chip, the paddle and the inner lead, respectively. It characterized in that it comprises an out lead that extends to the inner lead of the integrally formed protrusion.

따라서, 본 고안에 의하면, 반도체 패키지를 제조할 때 와이어 본딩 공정을 진행하지 않고 이방성 전도 테이프를 사용하여 리드 프레임의 인너 리드와 반도체 칩의 칩패드를 직접 본딩시키므로써 종래의 패키지에서 금속 와이어의 높이만큼 패키지의 두께를 줄일수 있어서 패키지를 초박형으로 콤팩트화 할수 있으며, 종래의 플라스틱 패키지보다 더 하이 핀화가 가능하게 된다.Therefore, according to the present invention, the height of the metal wire in the conventional package by directly bonding the inner lead of the lead frame and the chip pad of the semiconductor chip using an anisotropic conductive tape without proceeding the wire bonding process when manufacturing the semiconductor package. As the thickness of the package can be reduced, the package can be made extremely compact and high pinning is possible than the conventional plastic package.

Description

반도체 패키지Semiconductor package

본 고안은 반도체 패키지에 관한 것으로서, 더욱 상세하게는 반도체 패키지의 골격을 이루는 리드 프레임의 인너 리드와 반도체 칩의 칩패드를 와이어 본딩 공정을 진행하지 않고 용이하게 연결시킬수 있도록 한 것이다.The present invention relates to a semiconductor package, and more particularly, to easily connect an inner lead of a lead frame, which forms a skeleton of a semiconductor package, and a chip pad of a semiconductor chip without performing a wire bonding process.

도 1은 종래의 반도체 패키지를 나타낸 종단면도로서, 이에 도시된 바와 같이, 종래의 반도체 패키지는 리드 프레임(1)의 패들(2) 상면에 에폭시로 된 접착제(3)에 의해 반도체 칩(4)이 고정된 상태로 부착되고, 상기 반도체 칩(4)의 상면에 형성된 칩패드(5a)와 인너 리드(6)의 사이에는 각각 반도체 칩(4)의 내부 단자와 리드 프레임(1)의 외부 단자를 전기적으로 연결하기 위한 금속 와이어(11)가 연결되며, 상기 반도체 칩(4), 패들(2), 금속 와이어(11) 및 인너 리드(6)의 일정 부분을 감싸도록 몰딩부(8)가 형성되고, 상기 몰딩부(8)의 외측에는 각각의 인너 리드(6)에 연장되어 아웃 리드(9)가 일체로 돌출된 상태로 형성되어 구성된다.FIG. 1 is a longitudinal cross-sectional view of a conventional semiconductor package. As shown therein, a conventional semiconductor package is a semiconductor chip 4 formed by an adhesive 3 made of epoxy on an upper surface of a paddle 2 of a lead frame 1. Is attached in a fixed state, and between the chip pad 5a and the inner lead 6 formed on the upper surface of the semiconductor chip 4, the inner terminal of the semiconductor chip 4 and the outer terminal of the lead frame 1, respectively. The metal wire 11 for electrically connecting the metal wire 11 is connected, and a molding part 8 is formed to surround a portion of the semiconductor chip 4, the paddle 2, the metal wire 11, and the inner lead 6. The outer lead 9 is formed on the outer side of the molding part 8 and extends to each inner lead 6 so as to protrude integrally.

상기와 같이 구성된 종래 반도체 패키지의 제조 순서를 설명하면 다음과 같다.The manufacturing procedure of the conventional semiconductor package configured as described above is as follows.

먼저, 별도의 공정인 스템핑 또는 에칭 방법으로 리드 프레임(1)을 제작하는 리드 프레임 제조 공정을 수행한 후, 상기와 같이 제조된 리드 프레임(1)의 패들(2) 상면에 에폭시로 된 접착제(3)를 이용하여 반도체 칩(4)을 고정된 상태로 부착시키는 다이 본딩 공정을 수행한다.First, after performing a lead frame manufacturing process of manufacturing the lead frame 1 by a separate process of stamping or etching, an epoxy adhesive on the upper surface of the paddle 2 of the lead frame 1 manufactured as described above Using (3), the die bonding step of attaching the semiconductor chip 4 in a fixed state is performed.

그 다음, 상기 반도체 칩(4)의 상면에 형성된 칩패드(5a)와 인너 리드(6)를 각각 금속 와이어(11)로 연결하는 와이어 본딩 공정을 수행한 후, 상기 반도체 칩(4), 패들(2), 금속 와이어(11) 및 인너 리드(6)의 일정 부분을 감싸도록 몰딩부(8)를 형성하는 몰딩 공정을 수행한 다음, 후공정인 트리밍/포밍 공정을 수행하여 반도체 패키지를 완성하게 된다.Thereafter, a wire bonding process of connecting the chip pad 5a and the inner lead 6 formed on the upper surface of the semiconductor chip 4 with the metal wire 11 is performed, and then the semiconductor chip 4 and the paddle. (2), a molding process of forming the molding part 8 to cover a portion of the metal wire 11 and the inner lead 6 is performed, and then a trimming / forming process, which is a post-process, is completed to complete the semiconductor package. Done.

그러나, 이와 같은 종래의 반도체 패키지는 반드시 와이어 본딩 공정을 해야 하므로 인해 금속 와이어(11)의 높이로 인한 패키지의 두께가 커짐에 따른 틴(thin) 패키지로 제작하는데 한계가 따르고, 리드 프레임(1)의 인너 리드(6)와 반도체 칩(4)의 칩패드(5a) 사이를 각각 금속 와이어(11)로 연결시키므로 인해 최종 아웃 리드(9) 까지의 전기적인 통로가 길어지게 됨에 따라 반도체 칩(4)의 전기적인 특성, 특히 구동 스피드가 떨어지게 되는 등의 많은 문제점이 있었다.However, such a conventional semiconductor package must be subjected to a wire bonding process, so there is a limitation in manufacturing a thin package as the thickness of the package due to the height of the metal wire 11 increases, and the lead frame 1 Because the electrical path to the final out lead 9 is lengthened by connecting the inner lead 6 and the chip pad 5a of the semiconductor chip 4 with the metal wire 11, respectively, the semiconductor chip 4 ), There are many problems such as electrical characteristics, in particular, the driving speed is lowered.

따라서, 본 고안은 상기한 제반 문제점을 해결하기 위한 것으로서, 반도체 패키지의 골격을 이루는 리드 프레임의 인너 리드와 반도체 칩의 칩패드를 와이어 본딩 공정을 진행하지 않고 용이하게 연결시킬수 있도록 하여 두께 및 볼륨을 콤팩트화시킬수 있을 뿐만 아니라, 하이 핀화 할수 있는 반도체 패키지를 제공하는데 그 목적이 있다.Accordingly, the present invention is to solve the above-mentioned problems, and the thickness and volume of the inner lead of the lead frame forming the skeleton of the semiconductor package and the chip pad of the semiconductor chip can be easily connected without the wire bonding process. The aim is to provide a semiconductor package that can be made compact, as well as highly pinned.

도 1은 종래의 반도체 패키지를 나타낸 종단면도1 is a vertical cross-sectional view showing a conventional semiconductor package

도 2는 본 고안을 나타낸 종단면도Figure 2 is a longitudinal cross-sectional view showing the present invention

도 3은 도 2의 반도체 칩에 형성된 칩패드를 나타낸 사시도3 is a perspective view illustrating a chip pad formed on the semiconductor chip of FIG. 2.

도 4는 도 2의 반도체 칩에 형성된 칩패드와 인너 리드를 이방성 전도 테이프로 본딩하기 전,후의 상태를 나타낸 종단면도4 is a longitudinal cross-sectional view showing a state before and after bonding a chip pad and an inner lead formed on the semiconductor chip of FIG. 2 with anisotropic conductive tape;

도 5는 본 고안의 다른 실시예를 나타낸 종단면도Figure 5 is a longitudinal cross-sectional view showing another embodiment of the present invention

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

1; 리드 프레임 2; 패들One; Lead frame 2; Paddle

3; 접착제 4; 반도체 칩3; Adhesive 4; Semiconductor chip

5; 칩패드 6; 인너 리드5; Chip pad 6; Inner lead

7; 이방성 전도 테이프 8; 몰딩부7; Anisotropic conductive tape 8; Molding part

9; 아웃 리드 10; 솔더 볼9; Out lead 10; Solder ball

상기한 목적을 달성하기 위한 본 고안의 형태에 따르면, 리드 프레임의 패들 상면에 접착제에 의해 고정된 상태로 부착되는 반도체 칩과, 상기 반도체 칩의 상면에 요입되어 형성되는 복수개의 칩패드와, 상기 칩패드와의 사이에 각각 열과 압력을 가하면 전도성 물질 끼리 연결이 되어 전기가 통하도록 이방성 전도 테이프에 의해 본딩되는 인너 리드와, 상기 반도체 칩과 패들 및 인너 리드의 일정 부분을 감싸도록 형성된 몰딩부의 외측에 각각의 인너 리드에 연장되어 일체로 돌출 형성되는 아웃 리드를 포함하여 구성된 것을 특징으로 하는 반도체 패키지가 제공되므로써 달성된다.According to an aspect of the present invention for achieving the above object, a semiconductor chip attached to the upper surface of the paddle of the lead frame fixed by an adhesive, a plurality of chip pads formed by being inserted into the upper surface of the semiconductor chip, and When heat and pressure are respectively applied between the chip pads and the conductive materials, the inner leads are bonded by anisotropic conductive tape so as to conduct electricity, and the outer side of the molding part formed to surround a portion of the semiconductor chip, the paddle, and the inner leads. It is achieved by providing a semiconductor package comprising an out lead extending to each inner lead and integrally protruding from the inner lead.

여기서, 상기 인너 리드 피치는 리드 프레임의 두께를 얇게하여 에칭을 세밀하게 진행할수 있도록 반도체 칩의 칩패드와 동일하게 형성되고, 상기 리드 프레임의 패들 저면은 열방출이 용이하도록 패키지의 밖으로 노출된 것을 그 특징으로 한다.Here, the inner lead pitch is formed in the same way as the chip pad of the semiconductor chip so that the thickness of the lead frame can be finely etched, and the bottom of the paddle of the lead frame is exposed to the outside of the package to facilitate heat dissipation. It is characterized by.

한편, 상기한 목적을 달성하기 위한 본 고안의 다른 형태에 따르면, 리드 프레임의 패들 상면에 접착제에 의해 고정된 상태로 부착되는 반도체 칩과, 상기 반도체 칩의 상면에 요입되어 형성되는 복수개의 칩패드와, 상기 칩패드와의 사이에 각각 열과 압력을 가하면 전도성 물질 끼리 연결이 되어 전기가 통하도록 이방성 전도 테이프에 의해 본딩되며 몰딩후 상부면이 노출되는 인너 리드와, 상기 인너 리드의 상부면에 부착되는 솔더 볼을 포함하여 구성된 것을 특징으로 하는 반도체 패키지가 제공되므로써 달성된다.On the other hand, according to another aspect of the present invention for achieving the above object, a semiconductor chip attached to the upper surface of the paddle of the lead frame fixed by an adhesive, and a plurality of chip pads formed by being embedded in the upper surface of the semiconductor chip And an inner lead that is electrically connected to each other by applying heat and pressure between the chip pads and is bonded by an anisotropic conductive tape so as to conduct electricity, and exposed to an upper surface after molding, and attached to an upper surface of the inner lead. It is achieved by providing a semiconductor package comprising a solder ball to be formed.

상기 인너 리드에는 아웃 리드가 형성되지 않은 것을 그 특징으로 한다.The inner lead is characterized in that no out lead is formed.

따라서, 본 고안에 의하면, 반도체 패키지를 제조할 때 와이어 본딩 공정을 진행하지 않고 이방성 전도 테이프를 사용하여 리드 프레임의 인너 리드와 반도체 칩의 칩패드를 직접 본딩시키므로써 종래의 패키지에서 금속 와이어의 높이만큼 패키지의 두께를 줄일수 있어서 패키지를 초박형으로 콤팩트화 할수 있으며, 종래의 플라스틱 패키지보다 더 하이 핀화가 가능하게 된다.Therefore, according to the present invention, the height of the metal wire in the conventional package by directly bonding the inner lead of the lead frame and the chip pad of the semiconductor chip using an anisotropic conductive tape without proceeding the wire bonding process when manufacturing the semiconductor package. As the thickness of the package can be reduced, the package can be made extremely compact and high pinning is possible than the conventional plastic package.

이하, 상기한 목적을 달성하기 위한 본 고안의 바람직한 실시예를 첨부 도면에 의거하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention for achieving the above object will be described in detail with reference to the accompanying drawings.

도 2는 본 고안을 나타낸 종단면도이고, 도 3은 도 2의 반도체 칩에 형성된 칩패드를 나타낸 사시도이며, 도 4는 도 2의 반도체 칩에 형성된 칩패드와 인너 리드를 이방성 전도 테이프로 본딩하기 전,후의 상태를 나타낸 종단면도로서, 종래의 기술과 동일한 부분에 대해서는 동일 부호를 부여하여 본 고안을 설명한다.FIG. 2 is a longitudinal cross-sectional view illustrating the present invention, FIG. 3 is a perspective view illustrating a chip pad formed on the semiconductor chip of FIG. 2, and FIG. 4 is a diagram illustrating bonding the chip pad and inner lead formed on the semiconductor chip of FIG. 2 with anisotropic conductive tape. As a longitudinal sectional view which shows the state before and after, this invention is demonstrated by attaching | subjecting the same code | symbol about the part same as the prior art.

본 고안의 반도체 패키지는 리드 프레임(1)의 패들(2) 상면에 에폭시로 된 접착제(3)에 의해 반도체 칩(4)이 고정된 상태로 부착되고, 상기 반도체 칩(4)의 상면에는 요입되어 복수개의 칩패드(5)가 형성되며, 칩패드(5)와 인너 리드(6)의 사이는 각각 열과 압력을 가하면 전도성 물질 끼리 연결이 되어 전기가 통하도록 이방성 전도 테이프(7)에 의해 본딩된다.The semiconductor package of the present invention is attached to the upper surface of the paddle 2 of the lead frame 1 in a state where the semiconductor chip 4 is fixed by an adhesive 3 made of epoxy, and recessed on the upper surface of the semiconductor chip 4. Thus, a plurality of chip pads 5 are formed, and the chip pads 5 and the inner lead 6 are bonded by anisotropic conductive tapes 7 so that conductive materials are connected to each other when heat and pressure are applied to each other so that the electricity passes. do.

또한, 상기 반도체 칩(4), 패들(2) 및 인너 리드(6)의 일정 부분을 감싸도록 몰딩부(8)가 형성되고, 상기 몰딩부(8)의 외측에는 각각의 인너 리드(6)에 연장되어 아웃 리드(9)가 일체로 돌출된 상태로 형성된다.In addition, a molding part 8 is formed to surround a portion of the semiconductor chip 4, the paddle 2, and the inner lead 6, and each inner lead 6 is formed outside the molding part 8. Extending to the out lead 9 is formed in a state of integrally projecting.

그리고, 상기 리드 프레임(1)의 인너 리드(6) 피치는 리드 프레임(1)의 두께를 얇게하여 에칭을 세밀하게 진행할수 있도록 반도체 칩(4)의 칩패드(5)와 동일하게 형성되며, 상기 리드 프레임(1)의 패들(2) 저면은 열방출이 용이하도록 패키지의 밖으로 노출되도록 구성된다.In addition, the pitch of the inner lead 6 of the lead frame 1 is formed in the same manner as the chip pad 5 of the semiconductor chip 4 so that the thickness of the lead frame 1 can be thinned to proceed the etching in detail. The paddle 2 bottom of the lead frame 1 is configured to be exposed out of the package to facilitate heat dissipation.

상기와 같이 구성된 본 고안은 도 2 내지 도 4에 나타낸 바와 같이, 반도체 패키지를 제조할 때에는 먼저, 별도의 공정인 스템핑 또는 에칭 방법으로 리드 프레임(1)을 제작하는 리드 프레임 제조 공정을 수행한 후, 상기와 같이 제조된 리드 프레임(1)의 패들(2) 상면에 에폭시로 된 접착제(3)를 이용하여 반도체 칩(4)을 고정된 상태로 부착시키는 다이 본딩 공정을 종래와 동일한 방법으로 수행한다.2 to 4, the present invention configured as described above, when manufacturing the semiconductor package, first, the lead frame manufacturing process for manufacturing the lead frame 1 by a separate process, stamping or etching method Thereafter, the die bonding step of attaching the semiconductor chip 4 in a fixed state by using an adhesive 3 made of epoxy on the upper surface of the paddle 2 of the lead frame 1 manufactured as described above is performed in the same manner as in the related art. Perform.

그 다음, 상기 반도체 칩(4)의 상면에 요입되어 형성된 복수개의 칩패드(5)에 이방성 전도 테이프(7)를 부착시킨 후, 이방성 전도 테이프(7) 상에 인너 리드(6)를 얼라인하여 부착시킨 상태에서 열과 압력을 가하여 본딩시킴에 따라 전도성 물질 끼리 연결이 되어 상기 반도체 칩(4)의 내부 단자와 리드 프레임(1)의 외부 단자가 전기적으로 통하도록 연결시킨 다음, 상기 반도체 칩(4), 패들(2) 및 인너 리드(6)의 일정 부분을 감싸도록 몰딩부(8)를 형성하는 몰딩 공정을 수행한 후, 후공정인 트리밍/포밍 공정을 수행하여 반도체 패키지를 완성하게 된다.Next, the anisotropic conductive tape 7 is attached to the plurality of chip pads 5 formed by being inserted into the upper surface of the semiconductor chip 4, and then the inner lead 6 is aligned on the anisotropic conductive tape 7. As the bonding is performed by applying heat and pressure in the attached state, the conductive materials are connected to each other so that the inner terminal of the semiconductor chip 4 and the outer terminal of the lead frame 1 are electrically connected to each other. ), A molding process of forming the molding part 8 to surround a portion of the paddle 2 and the inner lead 6 is performed, and then a semiconductor package is completed by performing a trimming / forming process.

이때, 상기 리드 프레임(1)의 인너 리드(6) 피치는 반도체 칩(4)의 칩패드(5)와 동일하게 형성되므로 리드 프레임(1)의 두께가 얇게됨에 따라 에칭을 세밀하게 진행할수 있으며, 상기 리드 프레임(1)의 패들(2) 저면이 패키지의 밖으로 노출되도록 위치되므로 전력 소모량이 큰 제품에 패키지가 실장된 상태에서 열방출을 효율적으로 수행할수 있게 된다.At this time, since the pitch of the inner lead 6 of the lead frame 1 is formed to be the same as the chip pad 5 of the semiconductor chip 4, the etching of the lead frame 1 may be performed as the thickness of the lead frame 1 becomes thin. Since the bottom surface of the paddle 2 of the lead frame 1 is positioned to be exposed to the outside of the package, heat dissipation can be efficiently performed in a state where the package is mounted on a product with high power consumption.

한편, 본 고안의 다른 실시예로서 도 5에 나타낸 바와 같이, 반도체 패키지의 제작시 리드 프레임(1)의 인너 리드(6)에 연장되어 일체로 형성된 아웃 리드(9) 부분을 없애고, 상기한 바와 같이 반도체 칩(4)의 칩패드(5)와 인너 리드(6)의 사이를 각각 이방성 전도 테이프(7)에 의해 본딩시킨 후, 몰딩시 상기 인너 리드(6)의 상부면을 노출시키고, 최종적으로 인너 리드(6)의 상부면에 솔더 볼(10)을 부착시킨 다음, 후공정인 트리밍/포밍 공정을 수행하여 반도체 패키지를 제작할수 있게 된다.Meanwhile, as shown in FIG. 5 as another embodiment of the present invention, the part of the out lead 9 which is formed integrally by extending to the inner lead 6 of the lead frame 1 when the semiconductor package is manufactured is removed. Similarly, after bonding between the chip pad 5 and the inner lead 6 of the semiconductor chip 4 with the anisotropic conductive tape 7, the upper surface of the inner lead 6 is exposed during molding and finally By attaching the solder ball 10 to the upper surface of the inner lead 6, it is possible to manufacture a semiconductor package by performing a trimming / forming process that is a post-process.

이상에서와 같이, 본 고안은 다음과 같은 효과를 갖게 된다.As described above, the present invention has the following effects.

첫째, 반도체 패키지를 제조할 때 와이어 본딩 공정을 진행하지 않고 이방성 전도 테이프를 사용하여 리드 프레임의 인너 리드와 반도체 칩의 칩패드를 직접 본딩시키므로써 종래의 패키지에서 금속 와이어의 높이만큼 패키지의 두께를 줄일수 있어서 패키지를 초박형으로 콤팩트화 할수 있으며, 종래의 플라스틱 패키지보다 더 하이 핀화가 가능하게 된다.First, when fabricating a semiconductor package, the inner lead of the lead frame and the chip pad of the semiconductor chip are directly bonded using anisotropic conductive tape without the wire bonding process, thereby reducing the thickness of the package by the height of the metal wire in the conventional package. It can be reduced and the package can be made extremely thin, and high pinning is possible than conventional plastic packages.

둘째, 와이어 본딩 공정없이 인너 리드와 칩패드를 연결시키므로써 반도체 칩의 전기적인 특성, 특히 구동 스피드를 증가시킬수 있으며, 초박형 패키지로서 인쇄 회로기판 상의 실장 밀도를 높일수 있게 된다.Second, by connecting the inner lead and the chip pad without the wire bonding process, it is possible to increase the electrical characteristics of the semiconductor chip, in particular the driving speed, and to increase the mounting density on the printed circuit board as an ultra-thin package.

셋째, 리드 프레임의 인너 리드 피치가 반도체 칩의 칩패드와 동일하게 형성되므로 리드 프레임의 두께가 얇게됨에 따라 에칭성을 향상시켜 세밀하게 진행할수 있게 된다.Third, since the inner lead pitch of the lead frame is formed to be the same as the chip pad of the semiconductor chip, the thickness of the lead frame is thinned to improve the etching property and to proceed in fine detail.

넷째, 전력 소모량이 큰 제품에 패키지가 실장된 상태에서도 리드 프레임의 패들 저면이 패키지의 밖으로 노출되어 있으므로 열방출을 효율적으로 수행할수 있게 되는 등의 많은 장점이 구비된 매우 유용한 고안이다.Fourth, since the bottom of the paddle of the lead frame is exposed to the outside of the package even when the package is mounted on a product with high power consumption, it is a very useful design with many advantages such as efficient heat dissipation.

이상에서는 본 고안의 바람직한 실시예를 도시하고 또한 설명하였으나, 본 고안은 상기한 실시예에 한정되지 않고, 이하 청구범위에서 청구하는 본 고안의 요지를 벗어남이 없이 당해 고안이 속하는 기술 분야에서 통상의 지식을 가진자라면 누구든지 다양한 변경 실시가 가능할 것이다.Although the above has shown and described a preferred embodiment of the present invention, the present invention is not limited to the above-described embodiment, it is common in the technical field to which the subject innovation belongs without departing from the gist of the subject innovation claimed in the claims below. Anyone with knowledge will be able to make various changes.

Claims (5)

리드 프레임의 패들 상면에 접착제에 의해 고정된 상태로 부착되는 반도체 칩과, 상기 반도체 칩의 상면에 요입되어 형성되는 복수개의 칩패드와, 상기 칩패드와의 사이에 각각 열과 압력을 가하면 전도성 물질 끼리 연결이 되어 전기가 통하도록 이방성 전도 테이프에 의해 본딩되는 인너 리드와, 상기 반도체 칩과 패들 및 인너 리드의 일정 부분을 감싸도록 형성된 몰딩부의 외측에 각각의 인너 리드에 연장되어 일체로 돌출 형성되는 아웃 리드를 포함하여 구성된 것을 특징으로 하는 반도체 패키지.The semiconductor chip attached to the upper surface of the paddle of the lead frame in a fixed state by an adhesive, a plurality of chip pads formed by being inserted into the upper surface of the semiconductor chip, and conductive materials are formed when heat and pressure are applied between the chip pads. Inner leads which are connected by anisotropic conductive tape to be electrically connected to each other, and which are formed to protrude integrally from the inner leads outside the molding portion formed to surround a portion of the semiconductor chip, the paddle, and the inner lead. A semiconductor package comprising a lead. 제 1 항에 있어서, 상기 인너 리드 피치가 리드 프레임의 두께를 얇게하여 에칭을 세밀하게 진행할수 있도록 반도체 칩의 칩패드와 동일하게 형성된 것을 특징으로 하는 반도체 패키지.The semiconductor package according to claim 1, wherein the inner lead pitch is formed in the same manner as the chip pad of the semiconductor chip so that the thickness of the lead frame can be reduced to proceed the etching. 제 1 항에 있어서, 상기 리드 프레임의 패들 저면이 열방출이 용이하도록 패키지의 밖으로 노출된 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein the paddle bottom surface of the lead frame is exposed out of the package to facilitate heat dissipation. 리드 프레임의 패들 상면에 접착제에 의해 고정된 상태로 부착되는 반도체 칩과, 상기 반도체 칩의 상면에 요입되어 형성되는 복수개의 칩패드와, 상기 칩패드와의 사이에 각각 열과 압력을 가하면 전도성 물질 끼리 연결이 되어 전기가 통하도록 이방성 전도 테이프에 의해 본딩되며 몰딩후 상부면이 노출되는 인너 리드와, 상기 인너 리드의 상부면에 부착되는 솔더 볼을 포함하여 구성된 것을 특징으로 하는 반도체 패키지.The semiconductor chip attached to the upper surface of the paddle of the lead frame in a fixed state by an adhesive, a plurality of chip pads formed by being inserted into the upper surface of the semiconductor chip, and conductive materials are formed when heat and pressure are applied between the chip pads. A semiconductor package comprising an inner lead which is connected by anisotropic conductive tape so as to be connected and electrically connected, and has an upper surface exposed after molding and a solder ball attached to the upper surface of the inner lead. 제 4 항에 있어서, 상기 인너 리드에는 아웃 리드가 형성되지 않은 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 4, wherein an out lead is not formed in the inner lead.
KR2019980005946U 1998-04-15 1998-04-15 Semiconductor package KR200187486Y1 (en)

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