KR200164676Y1 - Mold for semiconductor molding - Google Patents

Mold for semiconductor molding Download PDF

Info

Publication number
KR200164676Y1
KR200164676Y1 KR2019970006132U KR19970006132U KR200164676Y1 KR 200164676 Y1 KR200164676 Y1 KR 200164676Y1 KR 2019970006132 U KR2019970006132 U KR 2019970006132U KR 19970006132 U KR19970006132 U KR 19970006132U KR 200164676 Y1 KR200164676 Y1 KR 200164676Y1
Authority
KR
South Korea
Prior art keywords
port
mold
molding
cavity
semiconductor
Prior art date
Application number
KR2019970006132U
Other languages
Korean (ko)
Other versions
KR19980061847U (en
Inventor
김대규
Original Assignee
김영환
현대반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대반도체주식회사 filed Critical 김영환
Priority to KR2019970006132U priority Critical patent/KR200164676Y1/en
Publication of KR19980061847U publication Critical patent/KR19980061847U/en
Application granted granted Critical
Publication of KR200164676Y1 publication Critical patent/KR200164676Y1/en

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
    • B29C45/02—Transfer moulding, i.e. transferring the required volume of moulding material by a plunger from a "shot" cavity into a mould cavity
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
    • B29C45/14—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
    • B29C45/14639—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components
    • B29C45/14655—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components connected to or mounted on a carrier, e.g. lead frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

본 고안은 반도체 몰딩용 금형에 관한 것으로, 종래에는 포트에서 멀리 떨어져 있는 캐비티에는 유속 발란스를 위하여 상대적으로 큰 압력을 가하여 몰딩 컴파운드를 공급하여야 하기 때문에 포트에 근접한 리드프레임의 와이어가 압력에 의한 처짐현상이 발생하는 문제점이 있었다. 본 고안 반도체 몰딩용 금형은 하부다이(13)에 일정 깊이의 제1 포트(17)를 형성하고, 그 제1 포트(17)에 연장하여 제1 포트(17) 보다 내경이 작은 제2 포트(18)를 형성하며, 그 제1 포트(17)와 제2 포트(18)에 각각 1단 및 2단 트랜스퍼(19)(20)를 각각 설치하여 2차에 걸쳐 몰딩컴파운드를 주입하므로 포트에 근접한 캐비티와 원거리에 위치한 캐비티에 전해지는 유속의 차이를 감소시키게 되어 와이어의 처짐불량을 감소시키는 효과가 있다.The present invention relates to a mold for semiconductor molding, and in the related art, the cavity of a lead frame close to the port sags due to pressure because a molding compound must be supplied to the cavity far from the port for relatively high flow velocity. There was a problem that occurred. The mold for semiconductor molding of the present invention forms a first port 17 having a predetermined depth in the lower die 13, and extends to the first port 17 so as to have a second port having an inner diameter smaller than that of the first port 17. 18) and the first and second stages 19 and 20 are respectively installed in the first port 17 and the second port 18 so that molding compound is injected in the second step so as to be close to the port. This reduces the difference in flow velocity transmitted to the cavity and the cavity located far away, thereby reducing the deflection of the wire.

Description

반도체 몰딩용 금형Mold for Semiconductor Molding

본 고안은 반도체 몰딩용 금형에 관한 것으로, 특히 각각의 캐비티(CAVITY)에 동일압력으로 컴파운드(COMPOUND)가 공급되도록하여 와이어의 처짐(WIRE SWEEPING)을 방지하도록 하는데 적합한 반도체 몰딩용 금형에 관한 것이다.The present invention relates to a mold for semiconductor molding, and more particularly, to a mold for semiconductor molding suitable for preventing a wire from being swept by allowing a compound to be supplied to each cavity at the same pressure.

도 1은 종래 반도체 몰딩용 금형의 구조를 보인 단면도로서, 도시된 바와 같이, 몰딩용 컴파운드가 유입되어 일정형태의 몰딩부가 이루어지는 캐비티(1)가 형성되도록 상,하부다이(2)(3)이 설치되어 있고, 그 하부다이(3)의 내측에 형성되어 있는 포트(4)에는 몰딩 컴파운드(5)를 밀어넣기 위한 트랜스퍼(TRANSFER)(6)가 설치되어 있으며, 상기 상,하부다이(2)(3)의 상,하면에는 상,하부플레이트(7)(8)가 설치되어 있고, 그 상,하부플레이트(7)(8)의 가장자리에는 상,하방향으로 가이드 포스트(GUIDE POST)(9)가 설치되어 있다.1 is a cross-sectional view illustrating a structure of a mold for semiconductor molding according to the related art. As illustrated, the upper and lower dies 2 and 3 are formed such that a molding compound is introduced to form a cavity 1 having a molding part of a predetermined shape. In the port 4 formed inside the lower die 3, a transfer 6 for pushing the molding compound 5 is provided, and the upper and lower dies 2 are provided. The upper and lower plates (3) are provided with upper and lower plates (7) (8), and the upper and lower plates (GUIDE POST) (9, 8) are positioned at the edges of the upper and lower plates (7) (8). ) Is installed.

상기와 같이 구성되어 있는 반도체 몰딩용 금형을 이용하여 몰딩공정이 진행되는 동작을 설명하면 다음과 같다.Referring to the operation of the molding process using the mold for semiconductor molding configured as described above are as follows.

먼저, 상기 상,하부다이(2)(3)를 일정간격으로 유지시킨 상태에서 하부다이(2)의 상면에 리드프레임을 얹어 놓는다. 이와 같은 상태에서 상,하부다이(2)(3)를 이동하여 일정공간의 캐비티(1)가 형성되도록 형합하고, 그 캐비티(1)의 내측에 리드프레임의 패들 상면에 부착되어 있는 칩이 위치하도록 한다. 이와 같은 상태에서 예열된 몰딩 컴파운드(5)를 포트(4)에 삽입하고, 트랜스퍼(6)를 이용하여 밀어넣는다. 이와 같이 포트(4)로 유입된 몰딩 컴파운드(5)는 도 2와 같이 런너(10)를 통과하여 각각의 캐비티(1)로 유입되어 일정크기의 몰딩부가 형성되는 것이다.First, the lead frame is placed on the upper surface of the lower die 2 in a state where the upper and lower dies 2 and 3 are maintained at a predetermined interval. In such a state, the upper and lower dies 2 and 3 are moved to form a cavity 1 in a predetermined space, and a chip attached to the upper surface of the paddle of the lead frame is located inside the cavity 1. Do it. In this state, the preheated molding compound 5 is inserted into the port 4 and pushed in using the transfer 6. As described above, the molding compound 5 introduced into the port 4 passes through the runner 10 as shown in FIG. 2 and enters the respective cavity 1 to form a molding part having a predetermined size.

그러나, 상기와 같은 종래 반도체 몰딩용 금형은 포트(4)에서 멀리 떨어져 있는 캐비티(1)에는 유속 발란스를 위하여 상대적으로 큰 압력을 가하여 몰딩 컴파운드(5)를 공급하여야 하기 때문에 포트(4)에 근접한 리드프레임의 와이어가 압력에 의한 처짐현상이 발생하는 문제점이 있었다. 이와 같은 문제점은 와이어간의 접촉에 의한 쇼트를 유발하기 때문에 불량발생의 요인되는 것이다.However, the above-described conventional mold for semiconductor molding has to be close to the port 4 because the molding compound 5 must be supplied to the cavity 1 far from the port 4 by applying a relatively large pressure for flow velocity balance. There was a problem that the wire of the lead frame deflection due to pressure. Such a problem is a cause of defects because it causes a short due to contact between wires.

상기와 같은 문제점을 감안하여 안출한 본 고안의 목적은 몰딩공정시 와이어의 처짐을 방지하도록 하는데 적합한 반도체 몰딩용 금형을 제공함에 있다.An object of the present invention devised in view of the above problems is to provide a mold for semiconductor molding suitable for preventing the deflection of the wire during the molding process.

도 1은 종래 반도체 몰딩용 금형의 구조를 보인 단면도.1 is a cross-sectional view showing the structure of a conventional mold for molding semiconductor.

도 2는 종래 반도체 몰딩용 금형에 컴파운드가 유입되는 상태를 보인 평면도.2 is a plan view showing a state in which a compound flows into a conventional mold for semiconductor molding.

도 3은 본 고안 반도체 몰딩용 금형의 구조를 보인 단면도.Figure 3 is a cross-sectional view showing the structure of the mold for molding a semiconductor of the present invention.

도 4는 도 3의 A부를 상세하게 보인 단면도.4 is a cross-sectional view showing in detail the portion A of FIG.

도 5는 본 고안의 요부인 1단/2단 트랜스퍼의 동작을 보인 단면도.Figure 5 is a cross-sectional view showing the operation of the main stage 1/2 stage transfer of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

13 : 하부다이 17 : 제1 포트13: lower die 17: first port

18 : 제2 포트 19 : 1단 트랜스퍼18: 2nd port 19: 1st stage transfer

20 : 2단 트랜스퍼20: two-stage transfer

상기와 같은 본 고안의 목적을 달성하기 위하여 캐비티가 형성되도록 상,하부다이가 설치되어 있는 반도체 몰딩용 금형에 있어서, 상기 하부다이의 내측에 일정깊이의 제1 포트를 형성하고, 그 제1 포트에 연장하여 제1 포트보다 내경이 작은 제2 포트를 형성하며, 그 제1/제2 포트에 2단으로 몰딩할 수 있도록 1단 및 2단 트랜스퍼가 설치된 것을 특징으로 하는 반도체 몰딩용 금형이 제공된다.In order to achieve the object of the present invention as described above, in the mold for semiconductor molding in which upper and lower dies are provided so that a cavity is formed, a first port having a predetermined depth is formed inside the lower die, and the first port is formed. A second port having an inner diameter smaller than the first port and extending to the first port, and having first and second stage transfers provided to mold the first and second ports in two stages. do.

이하, 상기와 같이 구성되는 본 고안 반도체 몰딩용 금형을 첨부된 도면의 실시예를 참고하여 보다 상세히 설명하면 다음과 같다.Hereinafter, with reference to the embodiment of the accompanying drawings, the invention-molded mold for semiconductor design configured as described above in more detail as follows.

도 3은 본 고안 반도체 몰딩용 금형의 구조를 보인 단면도이고, 도 4는 도 3의 A부를 상세하게 보인 단면도이다.3 is a cross-sectional view showing the structure of a mold for molding a semiconductor of the present invention, and FIG. 4 is a cross-sectional view showing part A of FIG. 3 in detail.

도시된 바와 같이, 본 고안 반도체 몰딩용 금형은 일정크기의 캐비티(11)가 형성되도록 상,하부다이(12)(13)가 설치되어 있고, 그 상,하부다이(12)(13)의 상,하면에는 상,하부플레이트(14)(15)가 설치되어 있으며, 그 상,하부플레이트(14)의 가장자리에는 상,하방향으로 수개의 가이드포스트(16)가 설치되어 있는 구성은 종래와 유사하다.As shown in the figure, the mold for semiconductor molding of the present invention is provided with upper and lower dies 12 and 13 to form a cavity 11 having a predetermined size, and the upper and lower dies 12 and 13 have upper images. The lower and upper plates 14 and 15 are provided on the lower surface, and the upper and lower plates 14 are provided with several guide posts 16 at the edges of the upper and lower plates. Do.

여기서, 본 고안은 하부다이(13)에 일정크기의 제1 포트(17)를 형성하고, 그 제1 포트(17)에 연장하여 제1 포트(17) 보다 내경이 작은 제2 포트(18)를 연장형성하였다.Here, the present invention forms a first port 17 having a predetermined size in the lower die 13, and extends to the first port 17, the second port 18 having a smaller inner diameter than the first port 17. Was extended.

그리고, 상기 제1 포트(17)에 1단 트랜스퍼(19)를 삽입설치하고, 그 1단 트랜스퍼(19)의 전방에는 2단 트랜스퍼(20)를 연결설치하였다.Then, a first stage transfer 19 is inserted into and installed in the first port 17, and a second stage transfer 20 is connected and installed in front of the first stage transfer 19.

또한, 상기 1단 트랜스퍼(19)의 전단면에는 2단 트랜스퍼(20)가 후진시 피난할 수 있는 일정깊이의 피난홈(19a)이 형성된다.In addition, an evacuation groove 19a of a predetermined depth is formed on the front end surface of the first stage transfer 19 so that the second stage transfer 20 may evacuate in reverse.

상기와 같이 구성되는 본 고안 반도체 몰딩용 금형을 이용하여 몰딩공정을 진행하는 동작을 설명하면 다음과 같다.Referring to the operation of proceeding the molding process using the present invention mold for molding configured as described above are as follows.

먼저, 상기 상,하부다이(12)(13)를 일정간격으로 유지시킨 상태에서 하부다이(13)의 상면에 리드프레임을 얹어 놓는다. 이와 같은 상태에서 상,하부다이(12)(13)를 이동하여 일정공간의 캐비티(11)가 형성되도록 형합하고, 그 캐비티(11)의 내측에 리드프레임의 패들 상면에 부착되어 있는 칩이 위치하도록 한다. 이와 같은 상태에서 도 5와 같이 제1 포트(17)의 내측에 예열된 몰딩 컴파운드 삽입하고, 1단 트랜스퍼(19)를 이용하여 몰딩 컴파운드를 캐비티(11)의 내측으로 밀어넣게 되는데, 이때 2단 트랜스퍼(20)는 1단 트랜스퍼(19)의 전단부에 형성된 피난홈(19a)에 위치한다. 이와 같이 1단 트랜스퍼(19)의 동작이 완료된 후에는 2단 트랜스터(20)가 전진하여 제2 포트(18)의 내측으로 몰딩 컴파운드를 밀어 넣는다.First, the lead frame is placed on the upper surface of the lower die 13 while maintaining the upper and lower dies 12 and 13 at a predetermined interval. In such a state, the upper and lower dies 12 and 13 are moved to form a cavity 11 in a predetermined space, and a chip attached to the upper surface of the paddle of the lead frame is located inside the cavity 11. Do it. In this state, as shown in FIG. 5, the pre-molded molding compound is inserted into the first port 17, and the molding compound is pushed into the cavity 11 by using the first stage transfer 19. The transfer 20 is located in the evacuation groove 19a formed at the front end of the first stage transfer 19. After the operation of the first stage transfer 19 is completed as described above, the second stage transfer unit 20 advances and pushes the molding compound into the second port 18.

즉, 1단 트랜스퍼(19)를 이용하여 1차적으로 전체 캐비티(11)의 약 1/2을 채운다음, 2단 트랜스퍼(20)를 이용하여 2차적으로 나머지 1/2의 캐비티(11)에 몰딩 컴파운드를 채우는 것이다.That is, first half of the entire cavity 11 is filled using the first stage transfer 19, and then second half of the cavity 11 is secondarily filled using the second stage transfer 20. To fill the molding compound.

이상에서 상세히 설명한 바와 같이 본 고안 반도체 몰딩용 금형은 하부다이에 일정 깊이의 제1 포트를 형성하고, 그 제1 포트에 연장하여 제1 포트 보다 내경이 작은 제2 포트를 형성하며, 그 제1 포트와 제2 포트에 각각 1단 및 2단 트랜스퍼를 각각 설치하여 2차에 걸쳐 몰딩컴파운드를 주입하므로 포트에 근접한 캐비티와 원거리에 위치한 캐비티에 전해지는 유속의 차이를 감소시키게 되어 와이어의 처짐불량을 감소시키는 효과가 있다.As described in detail above, the inventive mold for molding a semiconductor has a first port having a predetermined depth formed in a lower die, and extends to the first port to form a second port having an inner diameter smaller than that of the first port. Molding compound is injected in two stages by installing the first and second stage transfers respectively in the port and the second port, thereby reducing the difference in flow velocity transmitted to the cavity close to the port and the cavity located remotely. It has a reducing effect.

Claims (2)

캐비티가 형성되도록 상,하부다이가 설치되어 있는 반도체 몰딩용 금형에 있어서, 상기 하부다이의 내측에 일정깊이의 제1 포트를 형성하고, 그 제1 포트에 연장하여 제1 포트보다 내경이 작은 제2 포트를 형성하며, 그 제1/제2 포트에 2단으로 몰딩할 수 있도록 1단 및 2단 트랜스퍼가 설치된 것을 특징으로 하는 반도체 몰딩용 금형.In the mold for semiconductor molding in which upper and lower dies are formed so that the cavity is formed, a first port having a predetermined depth is formed inside the lower die, and extends to the first port to have a smaller inner diameter than the first port. A mold for forming a semiconductor, characterized in that a first stage and a second stage transfer are formed to form two ports and to mold in two stages to the first / second port. 제 1항에 있어서, 상기 1단 트랜스퍼의 전단면에는 2단 트랜스퍼가 후진시 피난할 수 있는 일정깊이의 피난홈이 형성된 것을 특징으로 하는 반도체 몰딩용 금형.The mold for semiconductor molding according to claim 1, wherein an evacuation groove of a predetermined depth is formed on the front end surface of the first stage transfer to evacuate the second stage transfer.
KR2019970006132U 1997-03-28 1997-03-28 Mold for semiconductor molding KR200164676Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019970006132U KR200164676Y1 (en) 1997-03-28 1997-03-28 Mold for semiconductor molding

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019970006132U KR200164676Y1 (en) 1997-03-28 1997-03-28 Mold for semiconductor molding

Publications (2)

Publication Number Publication Date
KR19980061847U KR19980061847U (en) 1998-11-16
KR200164676Y1 true KR200164676Y1 (en) 2000-01-15

Family

ID=19498118

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019970006132U KR200164676Y1 (en) 1997-03-28 1997-03-28 Mold for semiconductor molding

Country Status (1)

Country Link
KR (1) KR200164676Y1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101050657B1 (en) * 2009-11-10 2011-07-19 동일고무벨트주식회사 Transfer molder for manufacturing weather strip products

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101050657B1 (en) * 2009-11-10 2011-07-19 동일고무벨트주식회사 Transfer molder for manufacturing weather strip products

Also Published As

Publication number Publication date
KR19980061847U (en) 1998-11-16

Similar Documents

Publication Publication Date Title
US5077237A (en) Method of encapsulating a semiconductor element using a resin mold having upper and lower mold half resin inflow openings
KR940000740B1 (en) Manufacturing apparatus for resin and semiconductor
KR200164676Y1 (en) Mold for semiconductor molding
JPS6240851B2 (en)
EP1060507B1 (en) Mould part, mould and method for encapsulating electronic components mounted on a carrier
US6179599B1 (en) Sealing ejector pin
JPS609131A (en) Method for resin sealing of semiconductor device and apparatus thereof
CN109435146A (en) Optoelectronic switch and its production technology and corresponding production mould
JP2778332B2 (en) Method for manufacturing semiconductor device
CN214926589U (en) Earphone cover body mould
KR100520592B1 (en) Cleaning method of mold for manufacturing semiconductor package and frame for the same
KR100533756B1 (en) Mold for semiconductor package
KR960005041B1 (en) Semiconductor molding apparatus
KR20010037252A (en) Mold for manufacturing semiconductor package
JP3106946B2 (en) Manufacturing method of resin-encapsulated semiconductor device and its mold
JPS63143824A (en) Molding die
JPH03184351A (en) Degating method for matrix frame
JPH1058478A (en) Transfer molding machine and manufacture of semiconductor device using it
JPH09181107A (en) Manufacture of semiconductor device
JPH06120278A (en) Production unit of resin-sealed type semiconductor device
JPH08250530A (en) Manufacture of semiconductor device, and molding die
JPH065644A (en) Resin sealing method for semiconductor device
JP2950782B2 (en) Method for manufacturing semiconductor device
JPS59201429A (en) Semiconductor resin sealing apparatus
KR101020382B1 (en) A extension nozzle for the stack mold

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 20050923

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee