KR200145298Y1 - Semiconductor chip with pad for probe confirmation - Google Patents
Semiconductor chip with pad for probe confirmation Download PDFInfo
- Publication number
- KR200145298Y1 KR200145298Y1 KR2019960024153U KR19960024153U KR200145298Y1 KR 200145298 Y1 KR200145298 Y1 KR 200145298Y1 KR 2019960024153 U KR2019960024153 U KR 2019960024153U KR 19960024153 U KR19960024153 U KR 19960024153U KR 200145298 Y1 KR200145298 Y1 KR 200145298Y1
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- Prior art keywords
- probe
- semiconductor chip
- pad
- present
- sensing pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
본 고안은 반도체 칩에 관한 것으로 특히, 반도체 칩의 내부 회로와 전혀 상관없는 위치에 두 개의 탐침감지용 패드를 형성하고 상기 탐침감지용 패드를 연결하는 메탈라인을 구비시키는 것을 특징으로 하는 탐침확인용 패드(PAD)가 내장된 반도체 칩을 제공하여 프로우버 테스트시 탐침의 길이를 확인할 수 있어 탐침의 길이차이로 인해 반도체 칩의 전기적 특성의 변화가 발생될 때 이를 반도체의 오류로 판단할 수 있다는 문제점을 해소하는 효과가 있다.The present invention relates to a semiconductor chip, and in particular, to form two probe sensing pads at a position irrelevant to the internal circuit of the semiconductor chip, and the probe is characterized in that it comprises a metal line connecting the probe sensing pads Providing semiconductor chip with pad (PAD) to check probe length during probe test It has the effect of relieving.
Description
제1도는 종래 반도체 칩의 핀위치를 예시한 간략도.1 is a simplified diagram illustrating pin positions of a conventional semiconductor chip.
제2도는 본 고안에 따른 탐침 확인용 PAD가 내장된 반도체 칩의 핀위치를 예시한 간략도.Figure 2 is a simplified diagram illustrating the pin position of the semiconductor chip with a probe confirmation PAD according to the present invention.
본 고안은 반도체 칩에 관한 것으로 특히, 탐침에 적당하도록 한 프로우버(Prober) 테스터에 적용하기 용이한 탐침 확인용 패드가 내장된 반도체 칩에 관한 것이다.The present invention relates to a semiconductor chip, and more particularly, to a semiconductor chip having a probe identification pad that is easy to apply to a prober tester suitable for a probe.
일반적으로, 트랜지스터나 IC를 웨이퍼 상태로 검사하려면 본딩 패드(PAD)부분 또는 체크용 패터언 부분에 탐침을 세워서 측정하여야 한다. 이 때문에 다 탐침과 이것을 차례로 전후 좌우로 공급하는 장치를 프로우버라 칭하며, 프로우브(탐침)와 정밀한 공급장치를 조합한 것이다.In general, to inspect a transistor or an IC in a wafer state, a probe must be measured by standing a probe on a bonding pad (PAD) portion or a check pattern portion. For this reason, a probe which supplies all the probes to the front, rear, left, and right sides in turn is called a prober, and it combines a probe and a precise supply apparatus.
이때, 프로우버 태스트를 위해 필요한 패드의 기능을 종래의 반도체 칩에서는 통상 첨부한 제1도에 도시되어 있는 바와같이 반도체 칩의 핀(1∼8)이외에 칩 내부에 패드(ㄱ)를 구비시키고 있다.At this time, in the conventional semiconductor chip, the pad (a) is provided inside the chip in addition to the pins 1 to 8 of the semiconductor chip, as shown in FIG. .
또한, 도시하지는 않았지만 전력관계용 반도체 칩은 프로우브(탐침)를 위한 패드를 따로 만들지 않고 각 핀이 패드의 역할을 수행하게 된다.In addition, although not shown, the power-related semiconductor chip does not make a pad for a probe (probe), and each pin plays a role of a pad.
마지막으로, 역시 도시하지는 않았지만 반도체 소자의 내부 블록을 점검하거나 테스트모드로 전환할 때 필요한 패드를 따로 프로우버 태스트를 위해 구비시키는 경우도 있다.Lastly, although not shown, pads necessary for inspecting an internal block of a semiconductor device or entering a test mode may be separately provided for the prober task.
그러나, 이와같은 종래의 반도체 칩의 패드 구조로는 반도체 칩의 전기적 특성을 확인하기 위한 프로우브 카드의 핀이 반도체 칩의 패드에 콘택한 상태를 알 수 없으며 오직 탐침 흔적으로만 확인 가능하기 때문에 특히, 양산중에 탐침이 마모 등의 이유로 길이가 달라지면 그 길이차이로 인해 반도체 칩의 전기적 특성의 변화를 가져올 수 있는데 이를 반도체의 오류로 판단할 수 있다는 문제점이 발생되었다.However, in the pad structure of the conventional semiconductor chip, the pin of the probe card for confirming the electrical characteristics of the semiconductor chip is not known to be in contact with the pad of the semiconductor chip. In addition, if the length of the probe is changed during mass production due to wear, etc., the difference in length may result in a change in the electrical characteristics of the semiconductor chip, which may be regarded as an error of the semiconductor.
상기와 같은 문제점을 해소하기 윈한 본 고안의 목적은 탐침의 전압차를 확인할 수 있는 패드를 반도체의 동작과 전혀 무관한 위치에 설정한 후 이를 통해 탐침의 전압차이를 확인한 후 즉, 탐침의 길이를 확인한 후 프로우버(Prober) 테스팅 동작을 수행할 수 있도록 하는 탐침 확인용 패드가 내장된 반도체 칩을 제공하는데 있다.The purpose of the present invention to solve the above problems is to set the pad that can check the voltage difference of the probe at a position irrelevant to the operation of the semiconductor and then check the voltage difference of the probe through this, that is, the length of the probe The present invention provides a semiconductor chip with a built-in probe check pad that enables a probe to perform probe testing.
상기 목적을 달성하기 위한 본 고안의 특징은, 반도체 칩에 있어서, 반도체 칩의 내부 회로와 전혀 상관없는 위치에 두 개의 탐침감지용 패드를 형성하고, 탐침감지용 패드를 연결하는 메탈라인을 구비시키는 데 있다.A feature of the present invention for achieving the above object, in the semiconductor chip, forming two probe sensing pads at positions irrelevant to the internal circuit of the semiconductor chip, and having a metal line connecting the probe sensing pads There is.
이하, 첨부된 도면을 참조하여 본 고안에 따른 바람직한 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment according to the present invention.
제2도는 본 고안에 따른 탐침 확인용 PAD가 내장된 반도체 칩의 핀위치를 예시한 간략도로서, 제1도에 도시되어 있는 도면과의 차이만을 살펴보면, 반도체 칩의 내부 회로와 전혀 상관없는 위치에 두 개의 탐칩감지용 패드(ㄴ)를 구현하고 탐침감지요 패드(ㄴ)를 연결하는 메탈라인(ㄷ)이 구비되어 있다.FIG. 2 is a simplified diagram illustrating pin positions of a semiconductor chip having a probe identification PAD according to the present invention. Referring only to the difference from the drawing illustrated in FIG. 1, the position is irrelevant to the internal circuit of the semiconductor chip. The metal line (c) is provided to implement two probe chip sensing pads (b) and to connect the probe sensing pads (b).
상기와 같은 구성의 본 고안에 따른 탐침 확인용 PAD가 내장된 반도체 칩의 바람직한 사용예를 살펴보면 다음과 같다.Looking at the preferred use of the semiconductor chip with a probe confirmation PAD according to the present invention of the configuration as described above are as follows.
프로우버 테스터를 이용한 검사 동작을 수행하기 전에 두 개의 탐침을 탐침감지용 패드(ㄴ)에 연결한다. 이때, 프로우버 테스터에서는 하나의 탐침을 통해 연결되어 있는 탐침감지용 패드(ㄴ)에 전압을 인가하고 다른 하나의 탐침에 걸리는 전압의 크기를 검색하여 전압차를 판단한다.Connect the two probes to the probe detection pad (b) before performing the test operation with the prober tester. At this time, the prober tester applies a voltage to the probe detecting pad (b) connected through one probe and determines the voltage difference by searching the magnitude of the voltage applied to the other probe.
이때, 두 개의 탐침감지용 패드(ㄴ)에 각각 연결되어 있는 탐침이 동일한 길이를 갖고 있는 경우에는 각 탐침에 걸리는 전압의 크기는 전압차가 적거나 돌일하게 되는데, 반하여 길이가 차이나는 경우 즉, 어느 하나의 탐침이 짧은 경우 탐침감지용 패드(ㄴ)에 연결되지 않게되어 전압차가 매우 크게 나타나게 된다.At this time, when the probes respectively connected to the two probe sensing pads (b) have the same length, the magnitude of the voltage applied to each probe is small or retarded, whereas the difference in length is different. If one probe is short, it will not be connected to the probe detecting pad (b), resulting in a very large voltage difference.
이러한 경우 탐침에 이상이 있음을 알 수 있게 된다.In this case, it can be seen that there is a problem with the probe.
그러므로, 상술한 바와 같은 본 발명에 따른 탐침 확인용 패드(PAD)가 내장된 반도체 칩을 제공하면 프로우버 태스트시 탐침의 길이를 확인할 수 있어 탐침의 길이차이로 인해 반도체 칩의 전기적 특성의 변화가 발생될 때 이를 반도체의 오류로 판단할 수 있다는 문제점을 해소하는 효과가 있다.Therefore, by providing a semiconductor chip with a probe check pad (PAD) according to the present invention as described above, it is possible to check the length of the probe during probe operation, so that the electrical characteristics of the semiconductor chip are changed due to the difference in the probe length. When this occurs, there is an effect of solving the problem that can be determined as a semiconductor error.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019960024153U KR200145298Y1 (en) | 1996-08-12 | 1996-08-12 | Semiconductor chip with pad for probe confirmation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019960024153U KR200145298Y1 (en) | 1996-08-12 | 1996-08-12 | Semiconductor chip with pad for probe confirmation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980010701U KR19980010701U (en) | 1998-05-15 |
| KR200145298Y1 true KR200145298Y1 (en) | 1999-06-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019960024153U KR200145298Y1 (en) | 1996-08-12 | 1996-08-12 | Semiconductor chip with pad for probe confirmation |
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| Country | Link |
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| KR (1) | KR200145298Y1 (en) |
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1996
- 1996-08-12 KR KR2019960024153U patent/KR200145298Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR19980010701U (en) | 1998-05-15 |
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