KR20010114054A - Method of manufacturing a capacitor - Google Patents
Method of manufacturing a capacitor Download PDFInfo
- Publication number
- KR20010114054A KR20010114054A KR1020000033986A KR20000033986A KR20010114054A KR 20010114054 A KR20010114054 A KR 20010114054A KR 1020000033986 A KR1020000033986 A KR 1020000033986A KR 20000033986 A KR20000033986 A KR 20000033986A KR 20010114054 A KR20010114054 A KR 20010114054A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- film
- tio
- capacitor
- lower electrode
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
Abstract
본 발명은 커패시터 제조 방법에 관한 것으로, 하부 전극 및 상부 전극을 폴리실리콘으로 형성하고 유전체막을 Ta2O5으로 형성하는 커패시터 제조 공정에서, Ta2O5에 TiO2를 도핑시켜 Ta2O5-TiO2유전체막을 형성하므로 충분한 정전 용량을 확보하면서, 폴리실리콘 상부 전극을 형성하기 전에 알루미늄 산화막(Al2O3)을 형성하여 폴리실리콘 상부 전극과 유전체막과의 반응을 억제하므로써, 커패시터의 전기적 특성을 개선시킬 수 있는 커패시터 제조 방법이 개시된다.The present invention was doped with In to the lower electrode and the capacitor manufacturing process of forming the upper electrode of polysilicon, and forming a dielectric film by Ta 2 O 5 on the capacitor production process, TiO 2 in Ta 2 O 5 Ta 2 O 5 - By forming a TiO 2 dielectric film, while ensuring sufficient capacitance, before forming the polysilicon top electrode, the aluminum oxide film (Al 2 O 3 ) is formed to suppress the reaction between the polysilicon top electrode and the dielectric film, thereby preventing the electrical characteristics of the capacitor. Disclosed is a capacitor manufacturing method that can improve the efficiency.
Description
본 발명은 커패시터 제조 방법에 관한 것으로, 특히 하부 전극 및 상부 전극을 폴리실리콘으로 형성하고 유전체막을 Ta2O5로 형성하는 SIS(Silicon-Insulator-Silicon) 구조의 커패시터 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a capacitor, and more particularly, to a method of manufacturing a capacitor having a silicon-insulator-silicon (SIS) structure in which a lower electrode and an upper electrode are formed of polysilicon and a dielectric film is formed of Ta 2 O 5 .
최근, 소자가 점점 고집적화 됨에 따라 커패시터의 사이즈가 줄어드는 반면 안정된 소자동작을 위해서는 셀의 커패시턴스(Capacitance)는 그대로 유지시켜야 하는 어려움이 있다.Recently, as the device is increasingly integrated, the size of the capacitor decreases, but there is a difficulty in maintaining the capacitance of the cell as it is for stable device operation.
일반적으로, 커패시터는 하부 전극, 유전체막 그리고 상부 전극으로 구성된다. 커패시턴스에 영향을 미치는 요인 중 중요한 것은 하부 전극의 유효 산화막 두께(Tox)를 낮추는 것과 유전체막의 유전 특성을 향상시키는 것이다. 현재는 유전체막으로 탄탈륨 옥사이드(Ta2O5)를 많이 사용하고 있으나 Ta2O5의 유전율이 약 25정도이기 때문에 소자가 더욱 고집적화 될 경우 Ta2O5유전체막을 이용한 정전용량 확보에도 한계가 있다. 이러한 한계를 극복하기 위한 다른 방안으로는 메탈 하부 전극을 도입하여 유효 산화막 두께(Tox)를 낮추어 정전 용량을 확보하거나, Ta2O5보다 고유전체 물질을 사용해야 한다. 또한, MIS(Metal-Insulator-Silicon) 구조의 Ta2O5커패시터에서의 문제점은 상부 전극으로 TiN을 사용하고 있어 하부 전극인 폴리실리콘과의 일 함수(Work Function) 차이에 인한 정전 용량의 △C 값의 차이가 크므로 소자 적용에 어려움이 있다.Generally, a capacitor consists of a lower electrode, a dielectric film and an upper electrode. Important factors affecting the capacitance are to lower the effective oxide thickness (Tox) of the lower electrode and to improve the dielectric properties of the dielectric film. Currently, many tantalum oxides (Ta 2 O 5 ) are used as the dielectric film. However, since the dielectric constant of Ta 2 O 5 is about 25, there is a limit to securing the capacitance using the Ta 2 O 5 dielectric film when the device is further integrated. . Another way to overcome this limitation is to introduce a metal lower electrode to lower the effective oxide thickness (Tox) to secure the capacitance, or to use a high-k dielectric material than Ta 2 O 5 . In addition, the problem with the Ta 2 O 5 capacitor of the metal-insulator-silicon (MIS) structure is that TiN is used as the upper electrode, so that the capacitance ΔC due to the difference in the work function of the lower electrode polysilicon. Because of the large difference in values, it is difficult to apply the device.
따라서, 본 발명은 하부 전극 및 상부 전극을 폴리실리콘으로 사용할 때Ta2O5유전체막에 유전율이 40 내지 60인 TiO2를 도핑시켜 정전 용량을 확보하고, 상부 전극 증착 전에 알루미늄 산화막(Al2O3)을 형성하여 폴리실리콘 상부전극과 유전체막과의 반응을 억제하므로 커패시터의 전기적 특성을 개선할 수 있는 커패시터 제조 방법을 제공하는데 그 목적이 있다.Therefore, in the present invention, when the lower electrode and the upper electrode are used as polysilicon, the Ta 2 O 5 dielectric layer is doped with TiO 2 having a dielectric constant of 40 to 60 to secure a capacitance, and an aluminum oxide layer (Al 2 O It is an object of the present invention to provide a method of manufacturing a capacitor that can improve the electrical characteristics of the capacitor by forming a 3 ) to suppress the reaction between the polysilicon upper electrode and the dielectric film.
이러한 목적을 달성하기 위한 본 발명에 따른 커패시터 제조 방법은 반도체 소자를 형성하기 위한 여러 가지 요소가 형성된 반도체 기판 상에 하부 전극을 형성하는 단계; 상기 하부 전극 상에 질화막을 형성하는 단계; 상기 질화막 상에 Ta2O5-TiO2유전체막을 형성하는 단계; 상기 Ta2O5-TiO2유전체막 상에 Al2O3막을 증착하는 단계; 및 열처리를 실시한 후, 상기 Al2O3막 상에 상부전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a capacitor manufacturing method including: forming a lower electrode on a semiconductor substrate on which various elements for forming a semiconductor device are formed; Forming a nitride film on the lower electrode; Forming a Ta 2 O 5 —TiO 2 dielectric film on the nitride film; Depositing an Al 2 O 3 film on the Ta 2 O 5 —TiO 2 dielectric film; And after performing heat treatment, forming an upper electrode on the Al 2 O 3 film.
도 1a 내지 도 1c는 본 발명에 따른 커패시터 제조 방법을 설명하기 위하여 순차적으로 도시한 단면도.1A to 1C are cross-sectional views sequentially shown to explain a method of manufacturing a capacitor according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
10 : 반도체 기판 11 : 폴리실리콘 하부 전극10 semiconductor substrate 11 polysilicon lower electrode
12 : 질화막 13 : Ta2O5-TiO2유전체막12: nitride film 13: Ta 2 O 5 -TiO 2 dielectric film
14 : 알루미늄 산화막 15 : 폴리실리콘 상부 전극14 aluminum oxide film 15 polysilicon upper electrode
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 상세히 설명하기로 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1c는 본 발명에 따른 커패시터 제조 방법을 설명하기 위하여 순차적으로 도시한 단면도이다.1A through 1C are cross-sectional views sequentially illustrating a method of manufacturing a capacitor according to the present invention.
도 1a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 반도체 기판(10) 상에 폴리실리콘으로 하부 전극(11)을 형성한 후 하부 전극(11)의 표면을 HF 및 BOE(Buffer Oxide Etchant) 중 어느 하나로 식각하여 자연 산화막을 제거한다. 폴리실리콘 하부 전극(11)의 표면을 급속 질화 열처리(RTN)하여 질화막(12)을 형성한다. 질화막(12)은 후속 열공정에 의한 폴리실리콘 하부 전극(11) 표면에 SiO2형성을 억제한다. 이후, 하부 전극(11) 상에 Ta2O5-TiO2유전체막(13)을 형성한다.Referring to FIG. 1A, a lower electrode 11 is formed of polysilicon on a semiconductor substrate 10 on which various elements for forming a semiconductor device are formed, and then the surface of the lower electrode 11 is HF and BOE (Buffer Oxide Etchant). ) To remove the native oxide film. The surface of the polysilicon lower electrode 11 is rapidly nitrided (RTN) to form the nitride film 12. The nitride film 12 suppresses SiO 2 formation on the surface of the polysilicon lower electrode 11 by a subsequent thermal process. Thereafter, a Ta 2 O 5 —TiO 2 dielectric film 13 is formed on the lower electrode 11.
상기에서, Ta2O5-TiO2유전체막(13)은 소오스인 탄탈륨 에칠레이트(Ta(OC2H5)5)를 170 내지 190℃의 온도범위로 유지되는 기화기에서 기상상태로 만들어 증착 챔버에 공급하고, 이때, 반도체 기판(10)의 온도는 300 내지 400℃의 온도범위로 유지하며 0.1 내지 2Torr의 압력범위에서 10 내지 1000sccm의 O2가스를 반응가스로 이용하는 상태에서 10 내지 900sccm의 Ti를 공급하여 형성한다. TiO2는 유전율(ε)이 40 내지 60으로 유전율이 25인 Ta2O5보다 월등히 높기 때문에 Ta2O5만으로 유전체막을 형성할 때보다 Ta2O5-TiO2유전체막(13)이 유전율이 높아져 우수한 정전 용량을 확보할 수 있게 된다.In the above, the Ta 2 O 5 -TiO 2 dielectric film 13 is a vapor deposition chamber by making the source tantalum acrylate (Ta (OC 2 H 5 ) 5 ) in a gaseous state in a vaporizer maintained at a temperature range of 170 to 190 ℃ In this case, the temperature of the semiconductor substrate 10 is maintained in the temperature range of 300 to 400 ℃ and 10 to 900sccm Ti in the state using 10 to 1000sccm O 2 gas in the pressure range of 0.1 to 2Torr as the reaction gas It is formed by supplying. Since the TiO 2 has a dielectric constant (ε) of 40 to 60 and is significantly higher than that of Ta 2 O 5 having a dielectric constant of 25, the Ta 2 O 5 -TiO 2 dielectric layer 13 has a higher dielectric constant than when forming a dielectric layer using only Ta 2 O 5 . Higher capacitance can be obtained.
도 1b를 참조하면, Ta2O5-TiO2유전체막(13)상에 알루미늄 산화막(Al2O3;14)을 형성한 후, 후속 열처리 공정을 실시한다.Referring to FIG. 1B, an aluminum oxide layer (Al 2 O 3 ; 14) is formed on the Ta 2 O 5 —TiO 2 dielectric layer 13, and then a subsequent heat treatment process is performed.
상기에서, 알루미늄 산화막(14)은 반도체 기판(10)을 200 내지 450℃의 온도로 가열하고, 0.1 내지 2Torr의 압력범위에서 (CH3)3Al 소오스와 H2O를 반응가스로 하여 형성한다. 이후, 후속 열처리 공정은 N2O 플라즈마 및 UV 오존 중 어느 한 분위기에서 300 내지 500℃의 온도 범위의 저온으로 1 내지 5분 동안 실시한 다음,N2O 및 O2중 어느 한 분위기에서 650 내지 800℃의 고온으로 1 내지 30분 동안 퍼니스 어닐(Furnace Anneal) 처리를 한다.In the above, the aluminum oxide film 14 is formed by heating the semiconductor substrate 10 to a temperature of 200 to 450 ℃, a (CH 3 ) 3 Al source and H 2 O as a reaction gas in the pressure range of 0.1 to 2 Torr. . Subsequently, the subsequent heat treatment process is performed for 1 to 5 minutes at a low temperature in the temperature range of 300 to 500 ° C. in either atmosphere of N 2 O plasma and UV ozone, and then 650 to 800 in either atmosphere of N 2 O and O 2 . Furnace Anneal treatment is carried out for 1 to 30 minutes at a high temperature of ℃.
도 1c를 참조하면, Al2O3막(14) 상에 폴리실리콘을 이용하여 상부전극(15)을 형성한다.Referring to FIG. 1C, the upper electrode 15 is formed on the Al 2 O 3 film 14 using polysilicon.
상기한 공정에서, Al2O3막(14)은 상부 전극(14)이 폴리실리콘 상부 전극(15)과 Ta2O5-TiO2유전체막(13)과의 기생 반응을 방지하여 정전 용량을 증가시킨다.In the above process, the Al 2 O 3 film 14 prevents the parasitic reaction of the upper electrode 14 with the polysilicon upper electrode 15 and the Ta 2 O 5 -TiO 2 dielectric film 13 to reduce the capacitance. Increase.
상술한 바와 같이, 본 발명은 유전체막으로 Ta2O5-TiO2유전체막을 사용하므로 정전용량을 충분히 확보할 수 있고, 폴리실리콘 상부전극을 증착하기 전에 Al2O3막을 형성하므로 상부 전극과 Ta2O5-TiO2유전체막과의 기생 반응을 방지하여 기존의 상부 전극으로 TiN을 사용할 때 문제가 되었던 △C 값을 줄여 커패시터의 전기적 특성을 향상시키는 효과가 있다.As described above, the present invention uses a Ta 2 O 5 -TiO 2 dielectric film as the dielectric film, thereby sufficiently securing the capacitance, and forming the Al 2 O 3 film before depositing the polysilicon upper electrode. By preventing the parasitic reaction with the 2 O 5 -TiO 2 dielectric film, it is effective to reduce the ΔC value, which was a problem when using TiN as the existing upper electrode, to improve the electrical characteristics of the capacitor.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000033986A KR20010114054A (en) | 2000-06-20 | 2000-06-20 | Method of manufacturing a capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000033986A KR20010114054A (en) | 2000-06-20 | 2000-06-20 | Method of manufacturing a capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010114054A true KR20010114054A (en) | 2001-12-29 |
Family
ID=19672830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000033986A KR20010114054A (en) | 2000-06-20 | 2000-06-20 | Method of manufacturing a capacitor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20010114054A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100500940B1 (en) * | 2002-06-21 | 2005-07-14 | 주식회사 하이닉스반도체 | Method for fabricating capacitor in semiconductor device |
-
2000
- 2000-06-20 KR KR1020000033986A patent/KR20010114054A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100500940B1 (en) * | 2002-06-21 | 2005-07-14 | 주식회사 하이닉스반도체 | Method for fabricating capacitor in semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2000208508A (en) | Vacuum deposition of high-dielectric material made of silicate | |
| KR100639200B1 (en) | Method for manufactruing capacitor in semiconductor memory device | |
| KR100415516B1 (en) | Method of manufacturing a capacitor in a semiconductor device | |
| KR20010108995A (en) | Method for manufacturing capacitor in semiconductor memory divice | |
| US6835658B2 (en) | Method of fabricating capacitor with hafnium | |
| KR20080011788A (en) | Semiconductor device having dielectric layer and method for forming the same | |
| KR20010114054A (en) | Method of manufacturing a capacitor | |
| KR100583157B1 (en) | Method of manufacturing a capacitor in a semiconductor device | |
| KR100342873B1 (en) | Method for forming capacitor of semiconductor device | |
| KR20010088207A (en) | Method of forming composite dielectric film of tantalum oxide and titanium oxide | |
| KR100326237B1 (en) | Method for forming tantalum oxide layer using ozone gas and method for capacitor of semiconductor device by the same | |
| KR20010017212A (en) | Method of manufacturing a capacitor in a semiconductor device | |
| KR100297100B1 (en) | Method of manufacturing a capacitor in a semiconductor device | |
| KR100231604B1 (en) | Manufacturing method of capacitor of semiconductor device | |
| KR100434704B1 (en) | Capacitor of semiconductor device and Method for fabricating the same | |
| KR100297101B1 (en) | Method of manufacturing a capacitor in a semiconductor device | |
| KR100440777B1 (en) | Method of manufacturing capacitor in semiconductor device | |
| KR100702116B1 (en) | Fabrication method for semiconductor device having high insulator capacitor | |
| KR100646921B1 (en) | Method of manufacturing a capacitor | |
| KR100382610B1 (en) | Method for forming of capacitor the cell used high-integrated DRAM | |
| JP4106513B2 (en) | Capacitor manufacturing method for semiconductor device | |
| KR20040061278A (en) | Method for fabricating capacitor of semiconductor device | |
| KR100404481B1 (en) | Method for manufacturing capacitor semiconductor device | |
| KR20030050051A (en) | Method for fabricating tion capacitor | |
| KR20040059807A (en) | Method for forming hafnium oxide layer in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |