KR20010109783A - Method of Forming MOS Transistor by Using Selective Epitaxial Growth - Google Patents

Abstract

The method of forming a MOS transistor of the present invention comprises the steps of: forming a gate pattern including a gate insulating film and a gate electrode on a substrate, forming an insulating film spacer on a sidewall of the gate pattern, and performing selective crystal growth on a source / drain region; Forming an additional spacer in addition to the insulating layer spacer on the sidewall of the gate pattern, performing ion implantation to form a source / drain region, and performing a heat treatment to diffuse impurities.

The LDD structure of the MOS transistor formed as described above has a low junction region of a source / drain region and a deep junction structure of a high concentration region, which is advantageous for forming contact portions, and can effectively prevent a high temperature carrier effect.

Description

Method of forming MOS transistor using selective crystal growth {Method of Forming MOS Transistor by Using Selective Epitaxial Growth}

The present invention relates to a method of forming a MOS transistor (SEG type MOS Transistor) using a selective crystal growth, and more particularly to a SEG type MOS transistor that can reduce the exposure process.

With the high device integration of semiconductor devices, a method of reducing the formation size of a transistor, which is a typical device, is required. However, as the size of the transistor decreases, a short channel effect occurs, thereby reducing a threshold voltage and increasing a leakage current. A typical technique for preventing this is to form a source / drain of a lightly doped drain (LDD) structure.

However, as the integration of devices progresses, the source / drain structure of the LDD structure is approaching its limit. In other words, the thickness of the gate sidewall spacer used for forming the LDD structure cannot be sufficiently set. That is, when the sidewall spacer is thin, there is a problem that the source / drain region of the deep junction is recessed under the gate electrode, and when the sidewall spacer is thick, the source / drain contact region becomes very narrow.

In order to solve this problem at the same time, SEG (Selective Crystal Growth) is used to form MOS transistors. The SEG method is a method of securing the electrode thickness required for electrical connection by growing silicon substrates in the gate electrode and the source / drain electrode regions as shown in FIGS. 1 to 3. In the formation method, first, the device isolation film 11 is formed on the substrate 10, and the gate insulating film 13 and the gate film 15 are successively stacked and patterned to form a gate pattern. Ion implantation is performed using the gate pattern as a mask to prepare a shallow junction source / drain region 17. Sidewall spacers 15 are formed in the gate pattern, and the SEG film 19 is grown on the gate film and the source / drain regions 17 as shown in FIG. As shown in FIG. 3, the SEG film is changed into a tungsten silicide film 21. Further, source / drain regions 27 of deep junctions are formed by high dose ion implantation.

Another type of SEG method is a double spacer method. In this case, by forming the spacers of the gate sidewalls in duplicate, it is possible to secure the width of the LDD region while securing more regions for source / drain contact connection.

However, in order to form the LDD region, two ion implantation processes and two exposure processes are required depending on the impurity type of each transistor. Therefore, when forming a common metal oxide silicate (CMOS) transistor on a semiconductor substrate, impurity ion implantation of n-type impurity ion implantation 2, p-type impurity ion implantation 2 and a total of 4 is required. And each exposure and ion implantation is very cumbersome work.

Accordingly, an object of the present invention is to provide a method for forming a SEG type MOS transistor through fewer exposure steps than in the prior art.

1 to 3 are process sectional views showing an example of a conventional method of forming a SEG type MOS transistor;

4 through 6 are cross-sectional views illustrating a method of forming a SEG type MOS transistor according to an exemplary embodiment of the present invention.

※ Explanation of code for main part of drawing

10: Substrate 11: Device Separator

13,23: gate film 15,25: spacer

17, 27, 49: source / drain regions 19: SEG film

21: tungsten silicide film 22: gate insulating film

24: capping film 35: additional spacer

39: epitaxy 59: low concentration diffusion layer

In order to achieve the above object, a method of forming a MOS transistor includes: forming a gate pattern including a gate insulating layer and a gate electrode on a substrate, forming an insulating layer spacer on the sidewall of the gate pattern, and selectively determining a source / drain region Forming an additional spacer in addition to the insulating film spacer on the sidewall of the gate pattern, performing ion implantation to form a source / drain region, and performing a heat treatment for impurity diffusion. .

In the present invention, the gate pattern is generally formed by successively stacking and patterning a gate insulating film, a conductor gate electrode, and an insulating capping film, and the lamination film for forming the capping film, the spacer, and the additional spacer is preferably made of a silicon nitride film (Si3N4). .

Further, in the present invention, it is preferable that the first spacer is formed thin, and the maximum concentration value of ion implantation is in the selective crystal growth layer.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

4 through 6 are cross-sectional views illustrating a method of forming an N-type SEG type MOS transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 4, a gate insulating film 22 made of a silicon oxide film, a gate film 23 made of polysilicon, and a gate capping film 24 made of a silicon nitride film are sequentially formed on the substrate 10 on which the device isolation film 11 is formed. The gate stack is formed by photolithography and etching, and then a thin silicon nitride film is conformally stacked and anisotropically etched to form a spacer 25 on the sidewall of the gate stack. This is a common process.

Each transistor formation region is separated by an element isolation film 11.

Referring to FIG. 5, the silicon epitaxial film 39 is formed on the substrate by selectively growing crystals in the active region except for the gate stack and the spacers 25. The epitaxy layer 39 then forms part of the source / drain region. The additional spacers 35 are formed on sidewalls of the gate stack on which the spacers 25 are formed. The additional spacer 35 is mainly formed of a silicon nitride film and is formed by performing anisotropic front etching.

6, ion implantation is performed with N-type impurities such as arsenic over the entire surface of the substrate 10 on which the additional spacers 35 are formed. Ion implantation is not performed on the substrate covered by the spacer 25, the additional spacer 35, and the gate stack, and impurity doping is performed on the epitaxial layer 39 and the lower substrate to form the source / drain regions 49. .

Preferably, ion implantation controls the formation thickness and ion implantation energy of the epitaxy layer 39 so that the highest concentration is formed in the epitaxy layer 39. Arsenic can be implanted at a dose of 5E15 particles / CM ² with an energy of 65 kev. The thickness of the epitaxy film 39 is usually 50 to 500 nm, the thickness of the initially formed thin spacer 25 is 10 to 30 nm, and the thickness of the additional spacer 35 is 20 to 100 nm. In some cases, the impurity ions may be formed in-situ together with the epitaxial film 39.

After ion doping, the furnace is heated to 800C for 30 minutes for thermal diffusion, and arsenic diffuses into the substrate about 70nm. Considering the thickness of the epitaxy film 39, the contact portion is bonded to a depth of 140 nm. As a result of the thermal diffusion, the arsenic also diffuses in the channel direction together with the depth direction to form the low concentration diffusion layer 59. Therefore, an arsenic layer exists lightly below the sidewall spacers 25 and also in the channel portion, and the junction depth is formed very shallowly, such as 20 nm, and 20 nm is embedded in the channel.

The LDD structure formed as above has a low junction region of the source / drain region and a deep junction structure of the high concentration region, compared to the LDD structure of the conventional ion implantation, which is advantageous for forming a contact portion and effectively preventing a high temperature carrier effect. have.

Looking at the effect of improving transistor characteristics through simulation, etc., the improvement of the channel effect may contribute to reducing the chip size by reaching 10 to 15% based on 0.2 μm at 30 to 40 nm. In addition, it shows an effect of improving channel low current by about 5%, which is pointed out as a weak point of the existing LDD structure.

Claims (3)

Forming a gate pattern including a gate insulating layer and a gate electrode on the substrate, Forming an insulating film spacer on the gate pattern sidewall, Performing selective crystal growth in the active region, Forming an additional spacer on the sidewall of the gate pattern in addition to the insulating layer spacer; Performing ion implantation to form source / drain regions, and A method of forming a selective crystal growth MOS transistor comprising the step of performing a heat treatment for diffusion of impurities. The method of claim 1, And the gate pattern is formed by successively stacking and patterning a gate insulating film, a conductor gate electrode, and an insulating capping film. The method of claim 1, And the capping layer, the spacer, and the additional spacer are formed of a silicon nitride film (Si 3 N 4).