KR20010093077A - Pc based systems for driving of multiple screens - Google Patents

Abstract

The standard PC architecture changes so that multiple screens are driven from one PC motherboard. A plurality of screen controllers are attached to the AGP bus and correspondingly extended buses. Multiple screen controllers also attach to the extended PCI bus. The MPEG II decoder on the PCI bus is attached to each of the screen controllers on the AGP bus via a multimedia channel. Each display controller is addressed by one of the PCI and AGP buses and connected to only one of the PCI and AGP buses.

Description

PC-based system for personal computers running multiple screens {PC BASED SYSTEMS FOR DRIVING OF MULTIPLE SCREENS}

There are many environments where it is desirable to display (display) data on multiple screens or to display different data on multiple screens in one location. Examples of this data include video, graphics, text, and a mixture of these formats.

Conventional PCs include a general purpose data bus to which a display controller is attached. Data to and from the monitor are routed on this bus. Currently, it is possible to run multiple screens from the same processor, but they are limited to providing the same display. In order to display potentially different data or potentially to provide multiple screens for executing separate applications, a number of different processors, associated components such as system chipsets, memory, etc. are required. This is obviously expensive.

FIELD OF THE INVENTION The present invention relates to personal computers (PCs), and in particular to the display of data on multiple screens.

1 is a schematic diagram of a conventional PC architecture,

2 is a block diagram of an architecture embodying the present invention,

3 is a block diagram showing how three displays are driven from a single board computer;

4 shows how the PCI and AGP buses scale to drive a larger number of screens.

The present invention seeks to improve this problem and to allow multiple screens to run from a single processor.

In its broad form, the present invention connects a display controller to one or more buses. In one described embodiment, one display controller is attached to a general purpose bus such as a PCI bus, and another display controller is attached to a graphics bus such as an AGP bus.

In particular, a processor bus for transferring data between the processor and the processor, a graphics bus, a general purpose bus for transferring data between a plurality of input and output devices, the processor bus, and the graphics. A system chipset having a plurality of controller devices connected to a bus and the universal bus and controlling the processor bus, the graphics bus and the universal bus, and a first screen connected to the universal bus to control at least one display screen. And a second screen controller connected to the graphics bus for controlling at least one display screen, wherein the first and second screen controllers are addressed only from one of the general purpose and graphics buses, respectively. Provide a personal computer (PC).

Preferably, the graphics bus is an AGP bus.

Preferably, the general purpose bus is a PCI bus.

Embodiments of the present invention have the advantage that additional screen controllers can be attached to the motherboard, where multiple screens are not executed by the same PC processor and each can potentially execute a separate application.

Preferably, a video decoder is attached to the screen controller on the general purpose bus and the graphics bus. This video decoder is an MPEG II decoder connected through a multimedia channel with the advantage of faster data processing performance with minimal processor interference.

Preferably, the PC controller has a plurality of screen controllers attached to the graphics bus.

By extending the graphics bus, which is an AGP bus, and the universal bus, which is a PCI bus, a plurality of screen controllers may be connected to each bus to allow multiple displays to run from a single processor. The number of screens is limited only by the number of device addresses that can be allocated from the system BIOS.

Preferably, the two or more screens consist of screens of different display types. By using a screen controller that can support different types of simultaneous output, such as a tri-view controller that outputs VGA, TFT and TV, the number of screens that can be executed from a single processor is further increased.

The present invention also relates to a central processor unit (CPU) having a CPU bus connected thereto for transferring data between the CPU, an AGP bus communicating with the graphics controller, and a plurality of peripheral devices. A PCI bus, a system chipset having a system controller in communication with the AGP bus, a system chipset, a bridge in communication with a plurality of other buses and devices, at least one first screen controller in communication with the PCI bus, and the AGP At least one second screen controller in communication with a bus, wherein the PCI bus is in communication with the system controller and the bridge, and the first and second screen controllers are each connected by only one of the PCI and AGP buses, respectively. Provide an addressable personal computer (PC).

1, the architecture described is a conventional standard PC architecture. For example, a processor, which is a PENTIUM II (TM) processor manufactured by Intel Corporation, is connected to the system or CPU bus 12. The CPU operates at 66, 75, 83 or 100 MHz and at 3.3V, 2.5V or 1.9V. The second level cache memory 14 and the system chipset 16 are also connected to the CPU bus 12. Chipset 16 includes a peripheral component interconnect (PCI) bus (18), an accelerated graphics port (AGP) bus (20), and an Industry Standard Architecture (ISA) bus (22). A plurality of other buses including a bus are connected. PCI bus 18, also manufactured by Intel Corporation, is a 32-bit bus that functions as a 64-bit bus running at 33 or 66 MHz. The PCI bus is compatible with the ISA bus and operates asynchronously. The PCI bus 18 has a number of expansion slots 24 attached thereto. The PCI bus is an example of a general purpose bus that routes data between the processor and the peripherals of the system.

The AGP bus adjusts the PCI bus for graphics data to focus on the efficiency of transferring data from disk drives. Thus, the AGP bus is a graphics bus intended to perform dedicated functions. As can be seen from FIG. 2, the AGP bus is connected to the 3D graphics controller 25. For conventional PCs, devices on a single card can be attached to the AGP bus, while four or more expansion slots can be attached to the PCI bus. The addressing for these additional devices is controlled by a system bios (basic input / output software) that is retained in the ROM and cannot be changed once so set up.

The system chipset 16 functions to control the buses around the CPU, AGP, PCI and ISA buses, and also controls DRAM (dynamic RAM) 26 via the memory bus 23. The chipset's settings can only be changed by special BIOS software. The system chipset also controls interfaces such as secondary level cache memory 14, a keyboard or mouse, and a universal serial bus (USB). The USB bus is a serial input device that replaces connections to input and output devices such as keyboards, mice, and printers.

One example of a suitable chipset is the VIA Apollo MVP3 chipset, available from Via Corporation. This is a high performance, high energy efficient chipset intended for the realization of the AGP, PCI, and ISA buses for PC systems from 66 MHz to 100 MHz based on 64-bit Socket-7 Super-scalar processors. to be. The chipset is based on the north and south bridge architecture, which acts as a router that routes data from one bus to another. The north bridge takes heavy traffic and the south bridge routes to many other weaker routes. The VIA Apollo MVP3 is shown in the dotted indefinite triangle in FIG. This chipset has a system controller 28 identified as chip VT82C598 acting as the north bridge and a PCI-ISA bridge 30 realized as chip VT82C586B acting as the south bridge. The system controller 28 provides a pipeline, burst, and superior performance between the CPU 10, the optional synchronous cache (second level cache) 14, the DRAM 26, the AGP bus 20, and the PCI bus 18. And concurrent operations. The controller 28 communicates with the DRAM via the memory bus 23 and supports standard fast pase mode (FPM), extended data output (EDO), SDRAM, and DDR SDRAM. The system controller also complies with AGP specification 1: 0 and feature support for 66/75/83 / 100MHz CPU frequencies and 66MHz AGP bus frequencies. The PCI integrated peripheral controller forms part of the chipset and supports Intel and non-Intel family processors for PCI bus bridge functionality to create a complete Microsoft PC97-compliant PCI / ISA system. Peripheral controllers provide ISA expansion bus functionality and include multiple intelligent peripherals, including a dual-channel direct memory access (DMA) engine and a master-mode Illustrated Drive Electronics (IDE) controller with interlaced dual-channel commands. Contains a device controller. High performance transfers between devices connected to the PCI and IDE buses can be achieved through dedicated FIFOs coupled with scatter and gather master mode operations. Other intelligent peripheral controllers include USB controllers, keyboard controllers with PS2 mouse support, real time clocks with 256-byte extended CMOS, Advanced Configuration and Power Interface (ACPI), and legacy Advanced Advanced Management (APM). On-demand power management, distributed DMA-capable output for support of ISA legacy DMA over PCI bus, plus and play control to allow any interrupt channel to handle any interrupt on PCI bus, Three additional interruptible interrupt channels are provided to allow plug and play and reconfiguration capabilities of on-board peripherals for Windows 95 compliance, and for linked compliant symmetric multiprocessor systems. Includes external IOAPIC support.

Returning to Figure 3, the motherboard is configured such that a graphics accelerator is connected to both the PCI bus and the AGP bus. The architecture shown in Figure 3 permits a triple display screen configuration to a single board computer. Accordingly, in FIG. 3, the PCI VGA controller 40 is attached to the PCI bus, and the PCI VGA controller 40 is attached to the thin film transistor (TFT) bus display. An AGP VGA controller 42 is attached to the AGP bus, and the AGP VGA controller 42 has an output capable of supporting a VGA, TFT or TV display. The AGP VGA controller is also connected to the external memory 44. The MPEG II decoder 46 is attached to the PCI bus and connected to the AGP VGA controller via an ATI Multimedia Channel (AMC) bus 48. This allows for faster data processing with minimal CPU interference. Each of the display controllers 40 and 42 requires addressing from only one of the PCI and AGP buses to double the driver capacity.

Returning now to FIG. 4, the PCI and AGP buses are powered by twelve PCI VGA controllers 40 or graphics accelerators attached to the PCI bus that drive twelve TFT displays, twelve VGA monitors or twelve other TFT displays. It extends to 12 AGP VGA controllers 42 attached to the AGP bus. Thus, a total of 12 VGA monitors or 24 TFT monitors can be driven simultaneously or independently of each other. To select the appropriate display, the system bios may be an ID that selects a PCI bus through a PCI integrated peripheral controller that permits valid bus usage, and an AGP bus through a system controller that provides additional displays at the same time. Therefore, the VGA controller on the PCI bus is shown in FIG. 4 as having a device for addressing AGP IDs # 19 to 31. FIG. As in the embodiment of FIG. 3, the VGA controller and the display controller are addressed only from one of the AGP and PCI buses, respectively, and connected to only one of the AGP and PCI buses, thereby doubling the number of display controllers that can be connected to the system. do.

4, it can be seen that the AGP bus is driven by the system controller 28. Suitable graphics accelerators for use as AGP VGA controllers are capable of high quality 2D and 3D performance, full motion DVD with integrated motion compensation according to MPEG II standards, integrated LVDS transmitters, and simultaneous output to TV, CRT and LCD. ATI 3D Rage LT Pro with the advantage of providing a tri-view architecture. In consideration of the tree view feature and the configuration described with reference to FIG. 3, it is possible to drive a monitor and a TFT display with one graphic accelerator on the AGP bus, and one TFT display with one graphic accelerator on the PCI bus. Done.

In short, embodiments of the present invention described reconfigure the use of a dedicated graphics bus such as an AGP bus and a general purpose bus such as a PCI bus in a PC architecture. Rather than using a dedicated graphics bus for graphics data, the graphics bus is also used for the display controller. Thus, it is possible to support a display separated from both the graphics bus and the general purpose bus. These displays may be completely separate from each other, or may display different types of data. By the selection of suitable graphics accelerators, such as one or both of these buses, the number of mixed forms of displays, such as TFT and CRT, is greater than the number of graphics accelerators. Each display controller is connected to only one of the AGP bus, which is a dedicated graphics bus, and the PCI bus, which is a general purpose bus, and the number of display controllers that can be connected by requiring addressing from only one bus, and thus the displays that can be driven. Increase the number of This means that an address location on both buses is only needed when resumed for a display controller that is connected to and can be driven by that bus.

By extending both the dedicated graphics bus and the general purpose bus, the number of graphics accelerators that can be attached to each bus is significantly increased. The use of multiple display controllers on each bus makes it possible to drive a large number of displays in a single or mixed form from a single PC motherboard with a single processor and a single system chipset. The number of display controllers that can be attached is limited by the size of the graphics and universal buses, and also by the number of device addresses that can be maintained in the system BIOS. The BIOS software is stored in the ROM 50 and therefore cannot be changed once set. It is currently possible to drive at least 12 display controllers on each bus. This is thought to be possible for 24 display controllers for each bus as the commonly used standard BIOS assigns two device numbers to each display controller. A single device number is sufficient, and by reallocating the device numbers remaining on other display controllers, the number of controllers that can be supplied is doubled.

Examples of the TFT screen that can be connected include SVGA TFT, XGA TFT, UXGA TFT, Super TFT and the like. Each of these screens provides a touch screen qualification. Other screens include plasma and VGA monitors.

By using a VGA chipset that includes Low Voltage Differential Signaling (LVDS), it is possible to mount a second display 10 to 15 meters away from the base unit. This is an advantage for many sales and retail environments.

Thus, multiple screens can each drive multiple displays running potentially separate applications from the same PC processor using a single motherboard and chipset. This significantly reduces the cost per screen for commercial organizations and has many potential applications, such as in the service industry and retail. Suitable applications include electronic point of sale (EPOS) touch screen terminals, promotional advertisements, promotional hours, lifestyle games for children in retail environments, royalty-type payment systems, interactive customer terminals, television, and music. Creating atmosphere, multimedia capable output, kiosk terminal, and direct distribution of information to a guest room at the request of a guest, for example, in a hotel environment.

Claims (17)

A processor bus for transmitting data between the processor and the processor, a graphics bus, a universal bus for transferring data between a plurality of input and output devices, the processor bus, the graphics bus, and A system chipset connected to the universal bus and having a plurality of controller devices for controlling the processor bus, the graphics bus and the universal bus, a first screen controller connected to the universal bus and controlling at least one display screen; A second screen controller connected to the graphics bus for controlling at least one display screen, And the first and second screen controllers are only addressed from one of the general purpose bus and the graphics bus, respectively. A personal computer as in claim 1, wherein the graphics bus is an AGP bus. A personal computer as claimed in claim 1 or 2, wherein the universal bus is a PCI bus. 4. The system chipset of claim 1, 2 or 3, wherein the system chipset includes a system controller chip and a bridge chip disposed between the general purpose bus and the I / O bus. A personal computer connected to the system controller chip. The personal computer as claimed in claim 4, wherein the universal bus is connected between the system controller chip and the bridge chip. The personal computer as claimed in any one of claims 1 to 5, wherein a video decoder is attached to a screen controller on the universal bus and the graphics bus. 7. The personal computer of claim 6, wherein the video decoder is an MPEG II decoder. 8. The personal computer of claim 7, wherein the MPEG II decoder is connected to a screen controller on the graphics bus by a multimedia channel bus. The personal computer according to any one of claims 1 to 8, wherein at least one of the screen controllers connected to the graphics bus and the universal bus is capable of simultaneously outputting data to two or more screens. . 10. The personal computer of claim 9, wherein the two or more screens comprise screens of different display types. 11. The personal computer of claim 10, wherein the display form comprises a VGA monitor, a TV screen and a TFT screen. 12. A personal computer as claimed in any preceding claim, having a plurality of screen controllers attached to the graphics bus. 13. The personal computer as claimed in any one of claims 1 to 12, comprising a plurality of screen controllers connected to the universal bus. 14. The personal computer of claim 13, wherein the general purpose bus has a plurality of expansion slots, and the plurality of screen controllers are more than the plurality of expansion slots. The personal computer according to any one of claims 12 and 6 to 8, wherein each of said plurality of screen controllers connected to said graphics bus is connected to said video decoder. The personal computer as claimed in claim 15, wherein each of the screen controllers and the video decoder is connected by a multimedia channel bus. A central processing unit (CPU) having a CPU bus connected thereto to transfer data between the CPU, an AGP bus communicating with the graphics controller, a PCI bus communicating with a plurality of peripherals, and communicating with the AGP bus A system chipset having a system controller, a bridge in communication with the system chipset, and a plurality of other buses and devices, at least one first screen controller in communication with the PCI bus, and at least one second in communication with the AGP bus. Configured with a screen controller, And the PCI bus communicates with the system controller and the bridge, and wherein the first and second screen controllers are addressed only by one of the PCI bus and the AGP bus, respectively.