JP2000148110A - Composite screen pc base system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To connect a display controller to one or more buses, and drive plural screens from a single processor. SOLUTION: This personal computer includes a processor 10, a processor bus for transferring data to the processor 10 and from the processor 10, a graphic bus 20, a general purpose bus 18 for transferring the data to plural input/output devices and from the plural input/output devices, a system chip set connected to the processor bus, the graphic bus 20 and the general purpose bus 18 and including plural control devices for controlling the processor bus, the graphic bus 20 and the general purpose bus 18, a first screen controller 40 connected to the general purpose bus 18 for controlling at least one display screen, and a second screen controller 42 connected to the graphic bus 20 for controlling at least one display screen, and the first and the second screen controllers 40, 42 can be addressed respectively from only either of the general purpose bus 18 and the graphic bus 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a personal computer (PC), and more particularly, to displaying data on a plurality of screens.

[0002]

2. Description of the Related Art There are many environments in which it is desirable to display data on a plurality of screens or to display different data on a plurality of screens from a single position. This data may include video, graphics, text, etc., or a combination of these formats.

A conventional PC has a general-purpose data bus to which a display controller is connected. Data for and from the monitor is sent on this bus. Currently, multiple screens can be executed from a single processor, but they are limited to the same display. To provide multiple screens that display potentially different data or run potentially independent applications,
Requires multiple different processors and associated components, such as a system chipset, memory, and the like. This is obviously expensive.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and has as its object to connect one display controller to a general-purpose bus such as a PCI bus and to connect another display controller to an AGP bus. By connecting a display controller to one or more buses, such as by connecting to a graphics bus, it is possible to drive multiple screens from a single processor.

[0005]

SUMMARY OF THE INVENTION A PC computer according to the present invention comprises a processor, a processor bus for transferring data to and from the processor,
A graphics bus, a general-purpose bus for transferring data to and from a plurality of input and output devices, and the processor bus, the graphic bus, and the general-purpose bus connected to the general-purpose bus; A system chipset including a plurality of control devices for controlling the general-purpose bus, a first screen controller connected to the general-purpose bus and controlling at least one display screen, and at least one connected to the graphic bus; A second screen controller for controlling one display screen, wherein the first and second screen controllers each receive an address from only one of the general-purpose bus and the graphic bus. Thus, the above object is achieved.

[0006] The graphic bus may be an accelerated graphic port (AGP) bus.

[0007] The universal bus is a peripheral interconnect (peripheral).
al component interconnect (PCI) bus.

The system chipset includes a system control chip, and the general purpose bus and additional inputs / outputs (I / O).
/ O) a bridge chip disposed between the system control chip and the system control chip.

[0009] The general-purpose bus may be connected between the system control chip and the bridge chip.

[0010] A video decoder may be connected to the screen controller of the general-purpose bus and the graphic bus.

[0011] The video decoder may be an MPEGII decoder.

[0012] The MPEGII decoder may be connected to the screen controller on the graphic bus by a multimedia channel bus.

[0013] At least one screen controller connected to the graphic bus and the general-purpose bus may be capable of simultaneously outputting data to two or more screens.

The two or more screens may include screens of different display types.

The display type is VGA monitor, TV
Screen and a TFT screen.

[0016] The image processing apparatus may include a plurality of screen controllers connected to the graphic bus.

[0017] A plurality of screen controllers connected to the general-purpose bus may be included.

[0018] The general-purpose bus may have a plurality of expansion slots, and a plurality of screen controllers may be more than the number of the expansion slots.

[0019] Each of the plurality of screen controllers connected to the graphic bus may be connected to the video decoder.

The connection between each of the screen controllers and the video decoder may be a multimedia channel bus.

The PC computer according to the present invention has a CPU
A CPU bus coupled for transferring data to and from the CPU; an accelerated graphics port (AGP) bus for communicating with a graphics controller; and a peripheral interconnect (PCI) bus for communicating with a plurality of peripherals. , The AG
A PC computer including a central processing unit (CPU) including a system chipset including a system controller in communication with a P bus, and a bridge in communication with the system controller and a plurality of additional buses and devices,
The PCI bus communicates with a system controller and a bridge, at least one of the first screen controllers communicates with the PCI bus, and at least one of the second screen controllers communicates with the AG.
In communication with a P bus, each of the first and second screen controllers is addressed by only one of the PCI bus and the AGP bus, thereby accomplishing the above objective.

The present invention improves on the above problems and allows driving multiple screens from a single processor.

The present invention, in its broadest form,
Connect the display controller to one or more buses. In one preferred embodiment, one display controller is connected to a general purpose bus, such as a PCI bus, and another display controller is connected to a graphics bus, such as an AGP bus.

More specifically, a processor, a processor bus for transferring data to and from the processor, a graphics bus, and transferring data to and from a plurality of input and output devices. General-purpose bus, processor bus,
A graphics bus, a system chipset including a general purpose bus, including the processor bus, the graphics bus, and the general purpose bus; a first screen controller connected to the general purpose bus, for controlling at least one display screen; And a second screen controller for controlling at least one display screen, wherein the first and second screen controllers each have only one of a general-purpose bus and a graphic bus. Is provided.

[0025] Preferably, the graphics bus is an accelerated graphics port (AGP) bus.

[0026] Preferably, the universal bus comprises a peripheral interconnect (P
CI) bus.

Embodiments of the present invention have the advantage of mounting additional screen controls on the motherboard, running multiple screens on the same PC processor, and each screen can potentially execute a separate application.

[0028] Preferably, the video decoder is connected to a screen controller on a general purpose bus and a graphics bus. The video decoder can be an MPEG II decoder connected via a multimedia channel, which has the advantage of having faster data processing capability with minimal processor interference.

Preferably, the PC computer includes a plurality of screen controllers connected to the graphics bus.

[0030] Preferably, the PC computer includes a plurality of screen controllers connected to the general purpose bus.

A graphics bus, which can be an AGP bus,
By extending a general purpose bus, which may be a PCI bus, multiple screen controllers can be connected to each bus, and multiple displays can be performed from a single processor unit. The number of screens is limited only by the number of device addresses arranged from the system BIOS.

Preferably, the two or more screens include screens of different display types. Screen controllers that can simultaneously support different types of outputs, eg VGA, TF
The use of a Tri-view controller that outputs T and TV further increases the number of screens that can be executed from a single processor.

The present invention also relates to a CPU and a CP.
A CPU bus coupled to transfer data from the U; an accelerated graphics port (AGP) bus in communication with a graphics controller; a peripheral device interconnect (PCI) bus in communication with a plurality of peripheral devices; and an AGP bus. A central processing unit (CP) including a system chipset including a system controller in communication with the system controller and a bridge communicating with the system controller and a plurality of additional buses and devices.
U), wherein the PCI bus communicates with the system controller and the bridge, at least one of the first screen controllers communicates with the PCI bus, and at least one of the second screen controllers communicates with the AGP. Communicate with the bus, the first
And each of the second screen controllers are PCI and A
PC addressed by only one of the GP buses
Provide a computer.

[0034]

BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be described with reference to one embodiment of the invention, given only by way of example, and shown in the accompanying drawings.

Referring to FIG. 1, the architecture shown is a conventional standard PC architecture. The processor 10 is, for example, an Intel Corporation.
on may be a PENTIUM II ™ processor, connected to this system or CPU bus 12. The CPU bus has 66, 75, 83, or 100 MHz, and an I / O voltage of 3.3 V, 2.5
V, or 1.9V. The second level cache memory 14 and the system chipset 16 are also connected to the CPU bus 12. Peripheral interconnect (PCI) bus 18, accelerated graphics port (AG
A number of additional buses, including a P) bus 20, an ISA (Industrial Standard Architecture) bus 22, are also connected to the chipset 16. PCI bus 18 is also available from Intel Cor
A 32-bit bus that is manufactured by the Corporation and runs at 33 or 66 MHz and functions as a 64-bit bus. The PCI bus is compatible with the ISA bus and operates asynchronously. The plurality of expansion slots 24 are connected to the PCI bus 18. The PCI bus is an example of a general-purpose bus that routes data to and from processors and system peripherals.

The AGP bus removes the graphics data on the PCI bus, thereby allowing the PCI bus to concentrate on operations such as data transfer from disk drives. Thus, the AGP bus is a graphic bus intended to perform dedicated functions. As shown in FIG. 2, the AGP is connected to the 3D graphic controller 25. In a conventional PC, one device on a single card can be connected to the AGP bus, and up to four expansion slots can be connected to the PCI bus. The addresses to these additional devices are controlled by a system BIOS (basic input / output software), which is stored in ROM and, once set, does not change.

The system chipset 16 functions to control a dynamic RAM (DRAM) 26 via a bus around the CPU, an AGP bus, a PCI and ISA bus, and a memory bus 23 as shown in FIG.
The chipset settings can only be changed by special BIOS software. The system chipset also controls the second level cache memory, interfaces such as a keyboard or mouse, and the Universal Serial Bus (USB). The USB bus is a serial input device that replaces connection parts for I / O devices such as a keyboard, mouse, and printer.

One example of a suitable chipset is ViaCo
VIAApol commercially available from Rporation Inc.
It is a loMVP3 chipset. This is a 66 MHz to 100 MHz PC system based on a 64-bit Socket-7 Superscalar processor,
High performance, energy efficient, intended to implement AGP, PCI and ISA buses
ient) Chipset. The chipset is based on a north and south bridge architecture, where both bridges act as routers and send and receive data from bus to bus. The north bridge is responsible for the overcrowded traffic, and the south bridge is responsible for many different, more dense routes. VIA Apo
IloMVP3 is shown in the trapezoid drawn by the wavy line in FIG. The chipset acts as a north bridge,
A system controller 28, shown as chip VT82C598,
And functions as a south bridge, and the chip VT82C58
Includes a PCI to ISA bridge 30 labeled 6B. The system controller 28 provides excellent performance with pipeline processing, burst processing, and simultaneous processing to the CPU 1
0 and any synchronous cache (second level cache)
, DRAM 26, AGP bus 20, PCI bus 1
8 and provided. The controller 28 communicates with the DRAM via the memory bus 23 and operates in a standard accelerated mode (fast).
pase mode) (FPM), extended data output (EDO),
Supports SDRAM and DDRSDRAM.
The system controller is also compliant with the accelerated graphics port use 1: 0, 66/75/83/100 MHz C
It has the feature of further supporting the PU frequency and the AGP bus frequency of 66 MHz. The PCI built-in peripheral controller forms part of the chipset, functions as a PCI bus bridge, supports Intel-based or non-based processors, and is fully Mic
softwarePC97 compliant PCI / IS
Build the A system. The peripheral controller provides the function of an ISA expansion bus, and has a dual channel DMA (direct memory access) engine and a master mode IDE having a dual channel command of interlace.
Includes multiple intelligent peripheral controllers including (illustrated drive electronics) controllers. High performance transfer between devices connected to the PCI and IDE buses is achieved via a dedicated FIFO connected to a dedicated scatter and gather master mode process. Additional intelligent peripheral controls include USB controller, keyboard controller with PS2 mouse support, 256 bytes of extended C
Real-time clock with MOS, ACPI (extended configuration and power interface mechanism) and legacy APM
(Enhanced power management) Conditional power management function, distributed DMA performance supporting ISA legacy DMA on PCI bus, and P that enables maneuverability to send all interrupts on PCI bus to interrupt channel
LUS and play control, Windows95 (TM)
Includes three additional screenable interrupt channels that allow plug-and-play and reconfiguration of compliant on-board peripherals, as well as external IOAPIC support for cooperating compliant symmetric multiprocessor systems.

Referring to FIG. 3, the motherboard is configured so that the graphic accelerator can be connected to both the PCI bus and the AGP bus. The architecture shown in FIG. 3 allows for three display screen configurations on a single board computer. Therefore, in FIG.
A controller 40 is connected to the PCI and is also connected to a TFT (thin film transistor) bus display. AGPVGA controller 42 is connected to the AGP bus and has an output that can support VGA, TFT, and TV displays. AGPV
The GA controller is also connected to the external memory 44. M
The PEG II decoder 46 is connected to the PCI bus,
A via multimedia channel (AMC) bus 48
It is coupled to a GPVGA controller. This allows for faster data processing capability with minimal CPU interference. It can be seen that the driver capacity is doubled because each display controller 40, 42 only needs addresses from either the PCI or AGP bus.

Referring to FIG. 4, both the PCI and AGP buses have 12 PCIVGA controllers 40 or PCI buses.
Expanded by a graphics accelerator connected to the bus, it is possible to drive 12 TFT displays, and 12 AGPVGA controllers 42 are connected to the AGP to provide 12 VGA monitors or an additional 12 T monitors.
It is possible to drive an FT display. Therefore, a total of 12 VGA monitors or 24 TFT monitors are driven simultaneously or independently of each other. To select the appropriate display, the system BIOS ID selects the PCI bus via a PCI built-in peripherals controller that allows efficient bus utilization while at the same time providing a system controller that provides an additional display. Via the AGP bus. Therefore, the VGA controller on the PCI bus
It is shown in FIG. 4 as having device addresses of AGPID numbers 19 through 31. As shown in the embodiment of FIG. 3, the VGA controller and the display controller are each addressed and connected to only one of the AGP and PCI buses, respectively, and determine the number of display controllers that can be connected to the system. I have doubled.

As can be seen from FIG. 4, the AGP bus is driven by the system controller 28. Graphical accelerators suitable for use as AGPVGA controllers include high quality 2D and 3D performance, full motion DVD with motion compensation according to the MPEG II standard, built-in LVD
S transmitter and TV, CRT, and LCD
ATI3DRa with the advantage of providing a tri-view architecture that allows simultaneous output to
geLTPro. Due to the triple display characteristics and taking into account the configuration described with reference to FIG. 3, one monitor and one TFT display are driven by a single graphic accelerator on the AGP bus and one TFT The display can be driven on the PCI bus by a single graphic accelerator.

In summary, the above-described embodiments of the present invention illustrate reconfiguring within a PC architecture the use of a dedicated graphics bus such as an AGP bus and a general purpose bus such as a PCI bus. Rather than using a dedicated graphic bus only for graphic data,
The graphic bus is also used for the display controller. Thus, a separate display can be supported from both the graphics bus and the universal bus. These displays are completely independent of each other and display different types of data. By selecting the appropriate graphic accelerator on one or both buses, the number of mixed display types, such as TFT and CRT, can be greater than the number of graphic accelerators. Each display controller is connected to one of the graphic dedicated bus, the AGP bus, the general-purpose bus, and the PCI bus, and requires only an address from one bus, so that the number of connected display controllers is greatly increased. Increase, thereby greatly increasing the number of displays that can be driven. This requires that address locations on the two buses resume only for the display controller connected and driven to that bus.

By expanding both the dedicated graphics bus and the general purpose bus, the number of graphics accelerators that can be connected to each bus is greatly increased. By using multiple display controllers on each bus, a single processor with a single processor and a single system chipset can be used.
It is possible to drive a much larger number of single or mixed type displays driven from a C motherboard. The number of display controllers that can be connected is limited by the size of the graphics bus and general-purpose bus, and by the number of device addresses that can be built into the system BIOS (basic input / output software). BIOS software is RO
Since it is stored in M50, it cannot be changed once it is set. Currently, at least 12 display controllers can be driven for each bus. Since a standard BIOS that is in general use assigns two device numbers to each display controller, it can be assumed that 24 display controllers per bus may be possible. Reassigning the remaining device numbers to additional display controls doubles the number of controls that can be connected, since a single device number is sufficient.

An example of a TFT screen that can be connected is SVGAT.
FT, XGATFT, UXGATFT, and Suppe
It includes rTFT ^TM. Each of these screens may provide touch screen performance. Other screens have Plasma
And a VGA monitor.

By using a VGA chipset that includes low voltage differential signaling (LVDS), the second display can be mounted 10 to 15 meters away from the base unit. This is advantageous in many commercial and retail environments.

The standard PC architecture uses a single P
It is changed to drive a plurality of screens from the C motherboard. A plurality of screen controllers are connected to the AGP bus, and the bus is extended correspondingly. The plurality of screen controllers are also connected to the extended PCI bus. MP of PCI bus
The EGII decoder is connected to A via a multimedia channel.
It is connected to each screen controller of the GP bus. Each display controller is addressed and connected only by either the PCI bus or the AGP bus.

[0047]

As described above, a plurality of displays capable of executing each screen independently can be driven from one PC processor using a single motherboard and chipset. This can significantly reduce the cost per screen in a for-profit organization and has many applications, for example in the customer service and retail industries. Suitable applications include EPOS
(Electronic Point of Sales) touch screen terminals,
Promotional advertising, time of day promotion, children's games, loyalty-based systems in retail environments, interactive customer terminals, television and music, creating a lifestyle environment, multimedia possibilities, kiosk This includes information distribution such as providing information directly to terminals and guest rooms in a hotel environment in accordance with customer requirements.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overview of a conventional PC architecture.

FIG. 2 is a block diagram of an architecture implementing the present invention.

FIG. 3 is a block diagram showing how three displays can be driven from a single board computer.

FIG. 4 illustrates how the PCI bus and the AGP bus can be extended to drive more screens.

[Explanation of symbols]

 10 Processor 12 CPU Bus 18 ID Selection Number 19 20 ID Selection Number 19 23 Memory Bus 26 DRAM 28 VT82C598 30 VT82C586B 40 PCI VGA Controller 42 AGP VGA Controller 48 AMC 50 BIOS ROM

 ────────────────────────────────────────────────── ─── Continuation of front page (71) Applicant 599116856 Townsend Farm Road, Houghton Regis, Dunstable, Bedfordshire LU5 5BA U.S.A. K. (72) Inventor Karim Lahemtura UK L5 5B, Bedfordshire, Dunstable, Houghton Rage, Townsend Farm Road (no address)

Claims (17)

[Claims] 1. A processor, a processor bus for transferring data to and from the processor, a graphics bus, and transferring data to and from a plurality of input and output devices. A general-purpose bus, a system chip set including the processor bus, the graphic bus, and a plurality of control devices controlling the general-purpose bus connected to the processor bus, the graphic bus, and the general-purpose bus; and a connection to the general-purpose bus A PC computer, comprising: a first screen controller for controlling at least one display screen; and a second screen controller connected to the graphic bus and controlling at least one display screen. The first and second screen controllers are each provided with one of the general-purpose bus and the graphic bus. Addressed from one side only, P
C computer. 2. The PC computer according to claim 1, wherein said graphics bus is an accelerated graphics port (AGP) bus. 3. The general-purpose bus is connected to a peripheral interconnect (PC).
The PC computer according to claim 1 or 2, wherein the PC computer is a bus. 4. The system chipset includes a system control chip, and a bridge chip disposed between the general purpose bus and an additional input / output (I / O) bus, wherein the graphics bus includes the system bus. The PC according to claim 1, 2 or 3, which is connected to a control chip.
Computer. 5. The PC computer according to claim 4, wherein said general-purpose bus is connected between said system control chip and said bridge chip. 6. The PC computer according to claim 1, wherein a video decoder is connected to a screen controller of said general-purpose bus and said graphic bus. 7. The PC computer according to claim 6, wherein said video decoder is an MPEG II decoder. 8. The PC of claim 7, wherein said MPEG II decoder is connected to said screen controller on said graphics bus by a multimedia channel bus.
C computer. 9. The at least one screen controller connected to the graphic bus and the general-purpose bus,
9. The PC computer according to claim 1, wherein data can be output simultaneously to two or more screens. 10. The PC computer of claim 9, wherein the two or more screens include screens of different display types. 11. The display type is a VGA monitor,
The PC according to claim 10, including a TV screen and a TFT screen.
Computer. 12. The PC computer according to claim 1, further comprising a plurality of screen controllers connected to said graphic bus. 13. The P according to claim 1, further comprising a plurality of screen controllers connected to the general-purpose bus.
C computer. 14. The PC computer according to claim 13, wherein the general-purpose bus has a plurality of expansion slots, and a plurality of screen controllers are larger than the number of the expansion slots. 15. The PC computer according to claim 12, wherein each of the plurality of screen controllers connected to the graphic bus is connected to the video decoder. 16. The PC computer of claim 15, wherein the connection between each said screen controller and said video decoder is a multimedia channel bus. 17. An accelerated graphics port (AG) for communicating with a graphics controller and a CPU bus coupled for transferring data to and from the CPU.
A P) bus, a peripheral interconnect (PCI) bus communicating with a plurality of peripherals, a system chipset including a system controller communicating with the AGP bus, the system controller and a plurality of additional buses and devices. A communicating bridge; and a P including a central processing unit (CPU).
C computer, wherein the PCI bus is in communication with the system controller and the bridge, at least one of the first screen controllers is in communication with the PCI bus, and at least one of the second screen controllers is in the AGP bus. A PC computer, wherein the first and second screen controllers are each addressed by only one of the PCI bus and the AGP bus.