TW468133B - Multiple screen PC based system - Google Patents

Abstract

A standard PC architecture is modified to enable a plurality of screens to be driven from a single PC motherboard. A plurality of screen controllers is attached to the AGP bus and the bus extended correspondingly. A plurality of screen controllers is also attached to an extended PCI bus. An MPEG II decoder, on the PCI bus is attached to each of the screen controllers on the AGP bus via a multimedia channel. Each display controller is addressed by and connected to only one of the PCI and AGP buses.

Description

46 81 33 V. Description of the invention (1) Counting data is related to a kind of personal computer, a screen display technology. Computer applications have different operating environment commands to display data on multiple screens and β screens. These ones. Yo4, or a mixed form of different sources. Xi = The personal computer contains a universal data repository. Data input and output by the monitor. Existing multiple curtains can be provided from the same location but cannot provide data to the same display. ^ It can display different data. It may take several different processors and their combined elements, memory, etc. to achieve the operation. So blame. The object of the present invention is to improve the aforementioned problems with multiple screens. Xi is in the broadest form of expression X, Ben Faxi is on a bus. In a preferred embodiment, a busbar ' is used, e.g. a PCI bus and a universal bus such as an AGP bus. For = personal computer, including: a processor, data transfer in and out to the processor, a drop · row for connecting to the processor by a plurality of input and wheel out system chipset, graphics, especially a related Correspondence to some of these environments must be able to be displayed from a single location. Not included. Images, graphics, and text streams are connected to a display control. The bus determines the transmission processor to perform the display, but is subject to the provision of multiple It is independent of the application, so it requires pieces, for example: the system chip causes the aforementioned hardware requirements relative-the processor is actuated to drive the display controller to 'display controller connected to other display controllers. The present invention provides a processor bus for a graphics bus, a general-purpose bus for incoming and outgoing data, and a general-purpose bus that includes the following:

Na m.Ptd Page 4 4 6 81 3 3 V. Description of the invention (2) processor bus, the graphics bus and the universal bus, a first glory controller for controlling at least one connected to the universal bus The display screen and a first screen controller are used to control at least one display screen connected to the graphics bus; in #, the first and second screen controllers are only individually addressed by a universal and graphic bus. The graphic bus is preferably a (jp) bus. The universal bus is preferably a PC! Bus. The advantage of the embodiment of the present invention is that an additional screen controller can be connected to the motherboard so that Multiple screens are moved and executed by the same personal computer processor, so each possible execution can be done in a separate application. An image decoder is preferably connected to a universal bus and a graphics bus to a screen controller. The image decoder can be an MpEG It decoder and connected to a multimedia channel, which has the advantage of achieving faster data access with minimal processor processing time. The computer controller preferably includes multiple screens The controller is connected to the universal bus. By expanding the graphic bus, which may be an accelerated graphics bus, and the universal bus, which may be a PC I bus, a plurality of screen controllers may be connected to each bus and from one A single processor unit performs actuation of multiple displays. The foregoing multiple displays are limited only by the number of device addresses that can be addressed from the system BI0S. ^ The two or three displays preferably include screens of different display forms. By using a screen controller, different types of synchronous output can be achieved, such as a Tr 1-vei w controller that can output VGA, TFT, and TV. Number of screens again

99P〇172.ptd Page 5 1 s 8 1 3 3 ^ ----- 5. Description of the invention ⑶ " ----- It can still be executed by a single processor. The present invention also provides a personal computer comprising: a central processing unit having a CPU bus coupled to the CPU for transferring data in or out of the CPU, an accelerated graphics port (AGP) bus connected to a graphics control unit, and a peripheral The component connection (PC) bus connects a plurality of peripheral components. A system chipset includes a system controller connected to the accelerated graphics port bus, a bridge connected to the system controller, and a plurality of buses and devices. 'The PC I bus is connected to the system controller and the bridge, at least one first screen controller is connected to the PC I bus and at least one second screen controller is connected to the AGJP bus, and the first and second screen controls The device is only addressed by the respective edge avoidance element connections and the accelerated graphics / busbars. The present invention can be further understood from the following description, and please refer to the accompanying drawings when reading: FIG. 1 shows a schematic diagram of a conventional personal computer architecture; FIG. 2 shows a block diagram of an architecture according to an embodiment of the present invention; A block of three displays driven by a single computer motherboard according to the present invention; FIG. 4 shows an embodiment of how to expand peripheral component connections and accelerate the graphics port bus to drive a larger number of screens according to the present invention. Referring to Figure 1, a schematic diagram of a conventional standard personal computer architecture will be described. A processor 10, such as a PENTIUM I I processor 'manufactured by Intel Corporation, is connected to the system or CPU bus 12. The CPU bus can be operated at 66, redundant, 83 or 100 MHz and at output voltages of 3, 3, 2.5 or 1.9 volts. —The second layer of cache memory 14 and system chipset 16 are also connected to the CPU sink

99P0172.ptd Page 6 4 6 813 3 V. Description of the invention (4) Flow row 1 2. A plurality of buses are connected to the system chipset 16 including a peripheral component connection (PCI) bus 18, an accelerated graphics port (AGP) 20 and an industry standard architecture (ISA) 22. The Peripheral Component Connection (PCI) bus 18 is also manufactured by Intel Corporation and is a 32-bit bus that performs 64-bit bus operation at 33 or 66 MHz. (: The I bus is compatible with the I SA bus and can be operated asynchronously. A plurality of expansion slots 2 and 4 are connected to the peripheral component connection (PCI) bus 18 ^ Example of the PCI bus as a universal bus One is that it is decided by the processor and the system to pass data around. The aforementioned accelerated graphics port bus is used to explain the burden on the graphics data of the PCI bus, so that it can focus on the drive data transmission. Therefore, the AGP bus is a graphic bus used to achieve a specific function. As shown in Figure 2, the AGP bus is connected to a 31) 控制器 controller 25. In a traditional personal computer, a single-chip card device can be connected to an AGp bus and up to four expansion slots can be connected to the PC I bus. The addresses of those additional devices are controlled by the system BIOS (Basic Input Output Software), which is stored in ROM and cannot be changed. The function of this system chipset 16 is to control the buses surrounding the CPU, AGP, PC I and I SA buses, as shown in Figure 1. It also controls the dynamic random access memory (DRAM) by the memory 23 26. The settings of this chipset are only changed by specific B I 0 S software. The system chipset also controls the second-level cache memory and interfaces such as keyboard, mouse, and universal serial bus (USB). Rong Universal Continuous Bus replaces the continuous in-line device of the input and output device ports such as keyboard, mouse and printer. A suitable chipset is VIA Apollo MVP3 manufactured by vu

468133 V. Description of the invention (5) --- Chipset. This is a high-performance and energy-efficient chipset for the kAGP, PCI and I SA busbars in 66MHz to 2000 PC systems with "bit-7 Socket-7 Superscalar processors. This chipset is based on The North Bridge and the South Bridge are composed of two architectures; both serve as routers and transmit data from one bus to another. The North Bridge carries heavy data transmission while the South Bridge has a large number of different properties. Light data transmission. VIA Α ρ ο 11 ο VP VP 3 chipset shown in Figure 2 is shown by dashed lines. The chipset includes a system controller 2 8 composed of chip V T 8 2 C 5 9 8 as Nortel Bridge, and — PCI to IS Α bridge 30 and the chip V Τ 8 2 C 5 8 6 Β as the south bridge. The system controller 2 8 provides the central processing unit, and selects the synchronous cache memory (brother · One layer of cache memory 14), DRAM 26, AGP bus 20 and superior performance with the PCI bus 18 which has a color burst signal path. The system controller 28 is connected to the memory DRA Μ on 2 3 and supports standard fast pass mode (FAM), extended capital Output (EDO), SDRAM and DDE SDRAM. The system controller 28 also follows the Accelerated Graphics Port Specification 1: 0 and supports 66/75/83/10 0Mhz CPU frequency and 66Mhz AGP bus frequency. The PC I integrates peripheral control The processor forms part of the chipset and supports Inte 1 and non-Intel processors to the PCI bus bridge function to form a complete Microsoft PC97-compatible PCI / ISA system. The PCI integrated peripheral controller provides IS A extended bus Features multiple intelligent peripheral controllers including main mode IDE (Drive Ellectronics in the attached picture) controller with dual circuit DMA (direct memory access) engine and combined dual loop instructions. Connected to PCI and IDE bus devices High performance can be achieved via dedicated F IF0

99P0172.ptd Page 8 46 81 33 V. Invention; Explanation (6) The main mode of operation in combination with divergent collection was achieved. Further smart peripheral controllers include a USB controller; a keyboard with PS2 mouse support; a 256-bit extended CMOS timely timing; a series management function that complies with ACPI (Advanced Configuration and Power Interface) specifications and succeeds APM ( Advanced Power Management) requirements; to support the allocation of the DMA to the PCI bus ISA's successor DMA feature; to allow all the interrupt built-in forward transfer control on the PCI bus to any interrupt channel; to provide compatibility with Windows 95 Three additional screen capabilities for plug-and-play and built-in peripheral reset; and external I0APIC support for connection compatible synchronous multiprocessor systems. Continuing to refer to FIG. 2 ’The motherboard system is constructed to allow graphics acceleration to connect to the PC and AGP bus. The architecture shown in Figure 3 allows triple display on a single motherboard computer. Therefore, in FIG. 3, a pci VGA controller 40 is connected to the PCI bus and also connected to a TFT (thin film transistor) bus display. An AGP VGA controller 42 is connected to the AGP bus and also outputs to support VGA, TFT and TV displays. An oxygen AGP VGA controller 42 is also connected to the extra memory 44. ^ MPEG encoder 46 is connected to a PCI bus and connected to an AGP VGA controller via an ATI MultiMedia Channel (AMC) bus 48. This allows for faster data tolerance with minimal CPU intervention. It can be further inferred that each display controller 40, 42 only needs to be located at a certain location of the PCI and AG buses so that the capacity of the driver can be doubled. . Continue to refer to Figure 4 ’Both the PCI and AGP buses can be expanded to twelve PCI VGA controllers or forty graphics connected to the PCI bus

99P0172.ptd Page 9 46 81 33

It can drive twelve TFT displays and twelve controllers connected to the AGP forty-two to allow driving twelve VAG screens or twelve VAb screens or twelve TFT displays. Therefore, a total of twelve VGA or twenty-four monitors can be driven simultaneously or individually. In order to select the appropriate display, the system BIOS will use PCI to integrate peripheral controllers for ID selection and allow effective utilization of the ‘ml’ bus, while selecting a ◦ p bus by the system controller given an additional display. Therefore, the VGA controller on the pCΪ bus is shown in Figure 4. With device location AGP ID # 1 9-31. In the embodiment of FIG. 3, the VGA control is and the display controller are individually addressed and connected to only one of the p and PC I buses, so that the number of display controllers is doubled and can be connected to the system. It can also be seen from Figure 4 that the AGP bus is driven by the system controller 28. The normal graphics accelerator as AGP VGA controller can be An 3D Rage LT Pro 'It has high performance 2D and 3]) performance, full motion daylight DVD with two animation compression according to MpEG II standard, combined LVDS transmitter And actuate the synchronous output to the TV, CRT and LCD three-view architecture and other advantages. Because of the characteristics of the three-view architecture and the point of view of the structure described in Figure 3, a graphics accelerator on the AGP bus can be used to drive a monitor and a graphics accelerator on the P CI bus can be used to drive the TF display. In short, the graphics bus architecture and its application described in the embodiments of the present invention can be AGP bus, general bus, and PCI bus on a personal computer. The graphics bus is also used on the display controller rather than dedicated to the processing of graphics data. Therefore, individual displays can display different shapes completely independently.

99P0172.ptd Page 10 46 81 33 V. Description of the invention (8). By selecting appropriate graphics to display different forms of data. By selecting an appropriate graphics accelerator, it can be used as a bus for multiple mixed-mode displays. For example, the number of TFTs and CRTs is greater than the number of graphics accelerators. Each display controller is only connected to a dedicated graphics bus, AGp bus, Universal buses and PCI buses, which are only addressed by each bus. This can greatly increase the number of connected display controls and drive multiple displays. This means that the address in the two buses only needs to be set for the display controller connected and driven by the bus. By expanding the number of dedicated graphics buses and universal buses, the number of graphics accelerators connected to each bus has increased significantly. The use of f display controllers on various buses actuates a large number of displays, driving Cuiyi or mixed-type personal data from a separate personal computer motherboard with an f-processor and SoC. The number of connected display controllers is limited by the capacity of the graphics bus and universal bus, and the number of device addresses controlled by the system 6105 is determined. The BIOs software is ROM5 and cannot be changed. Under the current conditions, two display controllers can be driven on each bus. When standard B [os is used to specify the number of two devices to each display, the controller 'can drive twenty-four display controllers. A single number of devices is sufficient and the number of display controllers and their capacity can be further increased by reassigning the number of holding devices. Examples of TFT screens can be connected to products including SVGA tft, XGA TFT, UXGA TFT and Super TFT. Each of these screens can be extended with touch screen capabilities. Other screens can include PlaSmSa and VGA displays.

99P0172.ptd Page 11 6 8133 V. Description of the invention (9) By using two monitors, it can be installed in commercial use and therefore, with a single motherboard and commercial organization to each hospital and retailer's terminal equipment; The establishment of the environment; The VGA chipset includes low-voltage differential signaling. It is located at a distance of 10 to 15 meters from the base unit and has great advantages in retail applications. Personal computer processors with multiple chipset implementations that may implement possible applications drive the cost of one screen with potential, including electronic point-of-sale (EPOS) resale advertising industry; marketing time; actual systems; interactive customer terminals; Video multi-media capability; information dissemination in rooms requested by public telephone terminals has the (LVDS), first-class position. So the screen can be used by. This can reduce applications, such as: used touch screens, young music in retail environments, and physical conditions in hospitals.

d 6 B 1 3 3 Schematic description 99P0172.ptd (This page is intentionally blank.) Page 13

Claims (1)

4 6 81 3 3 VI. Scope of Patent Application (lj) A personal computer includes: a processor 'processor bus for transmitting data / materials by the processor, a graphics bus, The output device is a general-purpose bus for transmitting data, a bus connected to the processor, a graphics bus, and a general-purpose bus, including a controller chip for controlling the processor bus, the graphics bus, and the general-purpose bus. A first screen controller connected to the universal bus for controlling at least one display screen and a second screen controller connected to the graphics bus for controlling at least one display screen; wherein 'the first And the second screen controller is only by a certain address of the universal bus and graphics bus respectively. 2 / A personal computer as described in item 1 of the scope of patent application, wherein the graphics bus is an accelerated graphics port (A G P) bus. A personal computer according to item 1 or item 2 of the scope of patent application, wherein the universal bus is a peripheral component connection (PCI) bus. ', / A personal computer as described in item 1 of the scope of patent application, wherein the system chipset includes a system controller and a bridge chip installed between a universal bus and a wheel in / output bus, and wherein the graphic The bus is connected to the system controller chip. 5v A personal computer as described in item 4 of the scope of patent application, wherein a general bus is connected between the system control chip and the bridge chip. 6. A personal computer according to item 1 of the scope of the patent application, wherein the video decoder is connected to a general-purpose bus and a screen suppressor on a graphics bus. ^ 7 A personal computer as described in item 6 of the scope of patent application, wherein the video 4 6 81 3 3 6. Scope of patent application The decoder is an MPEG II decoder. A personal computer according to item 7 of the scope of patent application, wherein the MPEG 11 decoder is connected to a screen controller on a graphics bus via a multimedia channel bus. b. A personal computer as described in item 1 of the scope of patent application, wherein at least one screen controller connected to the graphics bus and the universal bus can simultaneously output data to two or more screens. The H is a brain described in item 9 of the scope of patent application, wherein the aforementioned two or more screens include different display types. d1. A personal computer as described in item 10 of the scope of patent application. The display type includes a VGA monitor, a TV screen, and a TFT screen. It includes a personal computer as described in item 1 of the scope of patent application, connected to a plurality of screen controllers of a graphics bus. It includes a personal computer as described in item 1 of the patent application, which is connected to a plurality of screen controllers connected to a universal bus. hi * A personal computer according to item 3 of the scope of the patent application, wherein the universal bus has a plurality of expansion slots and a plurality of screen controllers which are larger than the number of the expansion slots. , S li, 1 \ 5: If any one of the personal computers of item 6, 7, 8 or 12 of the scope of patent application is applied, each of the aforementioned multiple screen controllers connected to the graphics bus is connected to the aforementioned video decoder. 16 · A personal computer as described in item 5 of the scope of patent application, wherein the connection between each screen controller and video decoder is a multimedia channel bus 0 " ¢ 8 7 33 " '___ 6. Shen Yuan Patent Fan Yuan 1 A personal computer includes a command processing unit, and the CPU bus is integrated in it), it's a picture curtain 迨 ηγρ 彳 @ Transmission data from Ρϋ, an accelerated ^ shape 皋(AGP) Sink "No connection to a graphics controller, a peripheral component connection (PCI) bus connection to a plurality of violations _ chat bit, dump a peripheral component, system chipset ^ including the system controller to connect the acceleration graphics The port bus and the bridge are connected to the system controller and a plurality of buses and devices, wherein the peripheral component is connected to the bus and connected to the system controller and the bridge, and at least one first screen controller is connected to the peripheral component and connected to the bus. The at least one second screen controller is connected to the accelerated graphics port bus. The first and second screens are connected to the accelerated graphics port bus only by the peripheral components connected to the accelerated graphics port. 99P〇172.ptd Page 16