CN100336045C

CN100336045C - Multifunction chip set and relative method

Info

Publication number: CN100336045C
Application number: CNB2004100953032A
Authority: CN
Inventors: 林吉星; 余嘉兴
Original assignee: Via Technologies Inc
Current assignee: Via Technologies Inc
Priority date: 2004-11-19
Filing date: 2004-11-19
Publication date: 2007-09-05
Anticipated expiration: 2024-11-19
Also published as: CN1624918A

Abstract

The present invention provides a multifunctional chip set and a relevant design and manufacture method so as to realize two kinds of chip sets capable of respectively supporting a bus of a drawing acceleration port (AGP) and an interconnection (PCI-X) bus of an increase peripheral device by using the design of the same kind of integrated circuit. Control circuits of the two buses are arranged in the integrated circuit of the chip set of the present invention, the two control circuits can share output and input pads of the same design together, a terminal short circuit can be used for setting which bus the chip set supports, and the design of a single integrated circuit can realize two kinds of chip sets with different functions. In addition, the present invention can also respectively realize two kinds of chip sets capable of supporting different bus specifications respectively by alien wire bonding collocation when the integrated circuit is packed.

Description

Multifunction chip group and correlation technique

Technical field

The present invention relates to the method for a kind of multifunction chip group and relevant design/manufacturing, particularly a kind of method and the chipset that can realize out the relevant design manufacturing of two kinds of difference in functionality chipsets with the single IC for both design.

Background technology

Computer system is a most important hardware foundation in the modernized information society; Along with computer system is extensively used by society, the different users is also highlighted gradually to the different demands of computer system.In order to adapt to different functional requirements, information manufacturer also develops various associated component for computer system.As be familiar with known to the operator, the exchanges data between central processing unit, Installed System Memory, cartographic accelerator card and various auxiliary insert card/adjunct circuit, peripheral device is managed/controlled to meeting use chipset (chipset) in the computer system; For instance, chipset can be connected to cartographic accelerator card by the bus incoming call of certain specification, with the exchanges data between management, control cartographic accelerator card and central processing unit.Because the cartographic accelerator cards that adopt acceleration port (AGP, the accelerated graphic port) specification of drawing among the existing personal computer system so in the personal computer system, just need to adopt the chipset that can support the AGP bus specification more.On the other hand, the network service computer system big concerning the data flow, that performance requirements is high, the then normal enhancement type peripheral device interconnection (PCI-X at a high speed that uses, peripheral componentinterconnect extended) bus connects drafting card and other auxiliary insert card (similarly being the express network card), so in network service computer system, just need to adopt the chipset that to support the PCI-X bus.

In the prior art, can support the chipset of AGP bus and the chipset of PCI-X bus all to design respectively and manufacture; In other words, in the prior art, these two kinds of different kinds of chips groups will be used diverse integrated circuit (IC) design, can not continue to use circuit layout each other mutually; Jointly, the required consumed time and the cost of semiconductor technology just can't reduce, because different integrated circuit (IC) design just needs to use different gratings, different technology and encapsulation to set.

Summary of the invention

Therefore, fundamental purpose of the present invention promptly is to propose a kind of technology that can realize out the difference in functionality chipset with same integrated circuit respectively, realized so that the chipset of AGP bus and PCI-X bus can be continued to use identical integrated circuit, overcome the shortcoming of prior art.

In the present invention, be on same integrated circuit, to have disposed the control circuit of AGP bus and the control circuit of PCI-X bus, optionally enable (enable) control circuit and make another control circuit anergy (disable), just can with same integrated circuit selective realize out supporting the chipset of AGP bus, or can support the chipset of PCI-X bus.Though the AGP bus has adopted different signaling protocols and data framework basically with the PCI-X bus, both specifications also have the resemblance of part.For instance, the clock frequency of data transmission is very approaching on AGP bus and the PCI-X bus, all be 533MHz, on behalf of the control circuit of these two kinds of buses, this be highly suitable for shared some topological design in the same integrated circuit, similarly is the topological design that pad (I/O pad) is gone in output.

As be familiar with known to the operator, it is one of most important considerations on the topological design that output goes into to fill up to go up each clock frequency of exporting signal; Topological design need be considered the clock frequency that signal is gone in output, each exports space interval (spacing), cabling and layout configurations between the pad with decision, the various signals interference of avoiding each output to go between the pad (similarly are that train of signal rings, cross-talk, or the distortion of clock and shake, clock skew and jitter, or the like).And the present invention makes full use of the close characteristics of data clock frequency in AGP and the PCI-X bus specification, and the control circuit of these two kinds of buses can be incorporated into together in same integrated circuit, and the topological design of pad is gone in shared output.In preferred embodiment of the present invention, can control these two kinds of bus control circuits by the multiplex module of a multiplexer and go into being electrically connected of pad with output; This multiplex module can via the control of terminal short circuit (pin strapping) with optionally wherein a control circuit be electrically connected in output and go into pad, make this control circuit can bring into play function, the control circuit anergy and not acting on then that is not electrically connected and goes into pad to output; So, just can realize out the two kinds of chipsets that can support different bus respectively with same integrated circuit.

In the present invention, because the chipset of difference in functionality can be continued to use the process of same integrated circuit (IC) design, manufacturing and encapsulation, so the present invention can effectively reduce the time and the cost of various chipset productions/manufacturing.In addition, since the layout area itself that the pad configuration is gone in the output of existing chipset just greater than the layout area of integrated circuit (IC) logic circuit, so export total layout area that the layout area of going into to fill up has just been arranged integrated circuit; Even the present invention is integrated with two kinds of bus control circuits in integrated circuit, total also can't increase the layout area of integrated circuit.

In another embodiment of the present invention, two bus control circuits on the same integrated circuit then can use different output to go into pad respectively, and cooperate different routing process plannings different control circuits to be electrically connected in ball seat (ball) on the package substrates (substrate) at encapsulated phase, so also can utilize same integrated circuit to realize the chipset of difference in functionality.

Description of drawings

Fig. 1 is the synoptic diagram of chipset one embodiment of the present invention.

Fig. 2 and Fig. 3 are that Fig. 1 chips group is applied to the synoptic diagram in the various computing machine system.

Fig. 4 is a synoptic diagram of realizing two kinds of difference in functionality chipsets in another embodiment of the present invention with single IC for both.

The reference numeral explanation

10,60A-60B: chipset

12A, 52: integrated circuit

12B, 66A-66B: package substrates

14A: interface circuit

The 14B:PCI control circuit

14C: storage interface control circuit

14D: memory control circuit

16A, 56A:AGP bus control circuit

16B, 56B:PCI-X bus control circuit

18: multiplexer

20: multiplex module

22-26,58A-58B: I/O port

28-32,62-64: ball seat

36A-36B: central processing unit

38A-38B: Installed System Memory

40A-40B: computer system

Embodiment

Please refer to Fig. 1, Fig. 1 is chipset 10 1 embodiment D function block schematic diagrams of the present invention.Chipset 10 is to realize with the integrated circuit 12A that is packaged in a package substrates 12B; Then can be provided with among the integrated circuit 12A: can manage peripheral device interconnection (PCI, peripheral componentinterconnect) the PCI control circuit 14B of bus, may command storage device (similarly being hard disk or CD) but the memory control circuit 14D of the storage interface control circuit 14C management system memory access of access, and an interface circuit 14A, with the exchanges data between managing chip group 10 and computer system central processing unit.In addition, but also have the display process circuit of the sound effect circuit processing graphics signal that can handle audio output or network on-line control circuit or the like among the integrated circuit 12A in optionally.Above-mentioned these circuit can be gone into pad 22 reception/transmission signals or grid bias power supply via the output on the integrated circuit 12A; When integrated circuit 12A was packaged in package substrates 12B, these export pad 22 just can be via the routing between integrated circuit 12A and the package substrates 12B and the cabling layout in the package substrates 12B and be electrically connected in each corresponding ball seat (or terminal) 28 on the package substrates 12B.

Except above-mentioned circuit arrangement,, also be provided with an AGP bus control circuit 16A, a PCI-X bus control circuit 16B and a multiplex module 20 in the integrated circuit 12A of the present invention in addition in order to realize technical spirit of the present invention.AGP bus control circuit 16A (can be considered first bus control circuit) can manage on the AGP specification bus signal and exchanges data of each device, PCI-X bus control circuit 16B (can be considered second bus control circuit) but then signal data exchange of each device on the administration PC I-X specification bus.Can be provided with a plurality of multiplexers 18 in the multiplex module 20, it promptly is that pad 24 is gone in the output that is connected to a correspondence via the multiplexer 18 of a correspondence that each of double bus control circuit 16A and 16B exported into end, and pad 24 is gone in each output then can be electrically connected in each corresponding ball seat 30 via the cabling layout in the routing between integrated circuit and package substrates and the package substrates.Under this configuration, whether each multiplexer 18 just can go into to hold actual electrical to be connected in corresponding output according to the output that a setting signal S controls the double bus control circuit and go into to fill up 24 and ball seat 30.

For instance, as shown in fig. 1, there is an output to go into to hold a1, p1 to be electrically connected in a corresponding multiplexer 18 among AGP and PCI-X bus control circuit 16A and the 16B respectively; When this multiplexer receives the setting signal S (for example being the direct current signal of a high level) of a certain certain content, this multiplexer 18 will make the output of AGP bus control circuit go into to hold a1 to be electrically connected to the output of correspondence to go into pad and ball seat, and the output of PCI-X bus control circuit goes into to hold p1 just to be isolated from corresponding output to go into pad and ball seat.Relatively, when if this multiplexer receives the setting signal (similarly being a low level direct current signal) of another certain content, this multiplexer will make the output of PCI-X bus control circuit go into to hold p1 to be electrically connected in corresponding output to go into pad and ball seat, makes the output of AGP bus control circuit go into to hold a1 to isolate from corresponding output on the contrary and goes into pad and ball seat.So, by the effect of each multiplexer 18 in the multiplex module 20, just optionally control is could be exported into pad 24 and ball seat 30 transmitting/receiving signals by AGP or PCI-X bus control circuit via each; And these ball seats 30 just can be considered the bus ball seat of AGP or PCI-X bus.

In other words, when if the present invention need realize supporting the chipset of AGP specification bus with chipset 10, just can make AGP bus control circuit 16A go into pad 24 and ball seat 30 transmitting/receiving signals, the function of the total line traffic control of performance AGP by the running of multiplex module 20 via output; And PCI-X bus control circuit 16B will be isolated from each output by multiplex module and goes into pad and ball seat, does not bring into play any function.Relatively, if in the time of will realizing to support the chipset of PCI-X bus specification with same chipset 10, also can make PCI-X bus control circuit 16B go into pad 24 and ball seat 30 transmitting/receiving signals via the running of multiplex module 20, performance PCI-X bus control function via output; And AGP bus control circuit 16A will be isolated from each output and goes into pad and ball seat and stop to bring into play function.When reality realized, the present invention also can utilize the running of multiplex module 20, made not to be electrically connected in the bus control circuit anergy that pad/ball seat is gone in output.For instance, multiplex module 20 can make and not be electrically connected in output and go into the bus control circuit of pad/ball seat and can't obtain electric power supply, similarly be that the power circuit that makes this bus control circuit no longer be electrically connected in confession delivery of energy in the integrated circuit (similarly is a power layer, power plane), so that its anergy no longer consumes energy.Relatively, be electrically connected in output and go into the bus control circuit of pad/ball seat and then can obtain electric power supply and enable, and go into pad/ball seat via each output that is electrically connected and come transmitting/receiving signal.

As for the setting signal S that multiplex module 20 is received itself, it can be by (shown in the embodiment of Fig. 1) that receive outside the chipset 10 by exporting pad 26 and corresponding ball seat 32; Just make ball seat 32 become a multiplex (MUX) and set ball seat, allow the user of chipset 10 can utilize the mode of terminal short circuit (pinstrapping) to set, selecting chipset 10 is the chipset that can support AGP or PCI-X specification on earth.For instance, when the user sets the multiplex (MUX) of chipset 10 ball seat 32 and is short-circuited to the DC voltage of high level, just be equivalent to multiplex module 20 is sent the setting signal of a high level, one of them enables with AGP or PCI-X bus control circuit can to make multiplex module 20, and allow it to export into pad 24 and corresponding ball seat 30 and transmitting/receiving signal the bus control function that performance is corresponding via each.In addition, in the setting technique of the terminal short circuit of some chip, be under chip is in special pattern (for example be the initial setting pattern, the set-up) setting signal that just can set by specific setting terminal receiving function; Be under the normal operation pattern and after bringing into play the function of its setting, this specific setting terminal just can be used as general output/input terminal Deng chip, no longer being used as is the setting terminal of terminal short circuit.In the present invention, also can utilize the setting technique of this terminal short circuit to control the function of multiplex module 20.For instance, one setting signal buffer can be set in the multiplex module 20, this buffer can be when chipset 10 operates on the initial setting pattern when just having started shooting (similarly be computer system) is electrically connected in this multiplex (MUX) and sets ball seat 32, receive the setting signal of the external world's (similarly being motherboard) through ball seat 32 thus, will become the chipset of AGP or PCI-X bus with decision chipset 10.When chipset 10 is in the normal operation pattern by the time (similarly being that computer system is finished the start back), it is which bus control circuit to enable and to be electrically connected in each ball seat by that each multiplexer 18 in the multiplex module 20 just can be controlled according to the setting signal that stores in this buffer; Ball seat 32 then can be terminated to this buffer and switch other control circuit that is electrically connected in the chipset 10 outward and separately, and the general signal that becomes chipset 10 is exported into ball seat.In other words, under the normal operation pattern, multiplex module 20 can not decide the situation that is electrically connected of bus control circuit again according to the signal on the ball seat 32.

Comprehensive above the description as can be known, the embodiment of the present invention in Fig. 1 can make the AGP output shared identical with the PCI-X bus go into shield office and configuration via the arrangement of multiplex module 20.Owing to AGP and PCI-X bus originally with regard to being based on the pci bus specification that development comes out of deriving, so define in AGP and the PCI-X bus specification many similar signals are arranged, similarly be in the double bus specification, all to define/used signals such as IRDY, TRDY, Frame.And the present invention utilizes this characteristic exactly, makes the control circuit of these two kinds of buses can share identical output and goes into shield office.In addition, the more important thing is that the clock frequency of signal transmission is very approaching in AGP and the PCI-X bus specification, in fact is identical 533MHz (having specification tolerance slightly when actual operation).As know known to the technology personage, the clock frequency of signal is to design one of most important Consideration when exporting shield office, clock frequency can influence the setting of wiring length, interval or the like parameter value; Pad is gone in the output of transmitting different clock frequencies, and its topological design also can differ widely.Yet, because the signal clock frequency in AGP and the PCI-X bus specification is very approaching, should easily share most output and go into the design of shield office, and the present invention makes full use of this characteristic exactly, and the bus control circuit of AGP and PCI-X can be integrated in the same integrated circuit.

What deserves to be mentioned is that in the integrated circuit (IC) design of existing chipset, its layout area is to be dominated by the configuration that output goes into to fill up; That is to say, in fact in the chipset each control circuit layout area and less than the layout total area of integrated circuit, but go into the space/area demand that pad distributes owing to will yield to output, no matter how little the area of each control circuit is, total the layout area of integrated circuit can not dwindle thereupon.And the present invention can make the AGP output shared identical with the PCI-X bus control circuit go into shield office, just can under the situation that does not increase the total layout area of integrated circuit AGP and PCI-X double bus control circuit be integrated in the same integrated circuit.In other words, even include the bus control circuit of AGP and PCI-X in the integrated circuit of chipset of the present invention simultaneously, but the summation of these control circuit layout areas is still less than exporting into the required layout area of pad, so only otherwise increasing output goes into to fill up required layout area, the present invention just need not increase total layout area of chipset integrated circuit.

Certainly, under AGP and PCI-X bus specification, both required signal numbers may be unequal; For instance, because the PCI-X bus specification relates to 64 signal transmission, its bus control circuit may be gone into pad and ball seat comes a fairly large number of signal/data of transmission with more output.In Fig. 1, the output that these PCI-X additionally need goes into that pad/ball seat just can go into to fill up 24B with exporting, ball seat 30B realizes.When chipset will be embodied as the chipset of PCI-X bus, the PCI-X bus control circuit 16B in the chipset 10 just can come transmitting/receiving signal via ball seat 30,30B.Otherwise when chipset 10 will be embodied as the chipset of AGP bus, these ball seats 30B just can become the ball seat that does not use (not used).

Please refer to Fig. 2 and Fig. 3 (and in the lump with reference to figure 1); Fig. 2 and Fig. 3 are chipset 10 of the present invention is embodied as the difference in functionality chipset in different computer systems synoptic diagram; In order to make graphic more clear legibility, do not hindering technology of the present invention to disclose under the situation, some circuit in the chipset 10 has been omitted among Fig. 2 and Fig. 3 and do not drawn.In Fig. 2, computer system 40A can be a personal computer, set via suitable terminal short circuit multiplex module 20, multiplex module 20 just can allow PCI-X bus management circuit 16B anergy, and enable AGP bus control circuit 16A in the chipset 10, make it be electrically connected in an AGP slot 42A via each ball seat 30; By the switching of AGP slot 42A, chipset 10 just can be brought into play the control function of AGP bus, becomes the chipset that can support AGP specification bus, with the device on the management AGP bus, similarly is the AGP cartographic accelerator card 46A among Fig. 2.In addition, 28 of other ball seats of chipset 10 can be electrically connected (similarly be by the cabling layout on the motherboard be electrically connected to) respectively to a central processing unit 36A, an Installed System Memory 38A (similarly being random access memory), one or more storage device (similarly being hard disk) 50A and one or more slot 48A (similarly being the bus slot of PCI specification), with the signal exchange between management central processing unit 36A, Installed System Memory 38A, AGP slot apparatus, PCI slot apparatus (similarly being network card, sound card or the like) and each storage device.

In Fig. 3, computer system 40B then can be the network service host of a high speed, needs the chipset that can support high-speed PCI-X bus; And chipset 10 of the present invention is after suitably the terminal short circuit is set, multiplex module 20 just can make AGI bus control circuit 16A anergy and enable PCI-X bus controller 16B, make PCI-X bus controller 16B be able to be electrically connected in one or more PCI-X slot 42B via ball seat 30 (and 30B), to realize out the chipset of a PCI-X specification, and the device on the administration PC I-X slot 42B, similarly be PCI-X auxiliary insert card 46B (it can be the cartographic accelerator card of a PCI-X specification, or express network card or the like).Other ball seat 28 of chipset 10 then can be electrically connected respectively to a central processing unit 36B, an Installed System Memory 38B, one or more storage device 50B and slot 48B (similarly being the bus slot of PCI specification), with the signal exchange between management central processing unit 36A, Installed System Memory 38A, PCI-X slot apparatus, PCI slot apparatus and each storage device (similarly being hard disk).

By the discussion of Fig. 2, Fig. 3 as can be known, the present invention can use identical chipset design to realize out supporting respectively two kinds of chipsets of AGP and PCI-X bus, in other words, the present invention is as long as design, produce, develop single a kind of chipset, just can realize out the chipset of difference in functionality, satisfy the difference in functionality demand of various computing machine system simultaneously, and the time and the cost of chipset design production exploitation just can decrease also.

Please refer to Fig. 4; Fig. 4 realizes out the synoptic diagram of two kinds of difference in functionality chipsets with single IC for both 52 in another embodiment for the present invention.Can be provided with a treatment circuit 54, an AGP bus control circuit 56A and a PCI-X bus control circuit 56B in the integrated circuit 52.Can be provided with various interface circuit, control circuit in the treatment circuit 54, similarly be the circuit 14A to 14D among Fig. 1, but also optionally be provided with the display process circuit of sound effect circuit processing graphics signal or network on-line control circuit or the like; This handles circuit 54 can export the transmitting/receiving signal into pad 58C by on the integrated circuit 52 each.AGP bus control circuit 56A can export the transmitting/receiving signal into pad 58A by each, with the device on management, control, the service AGP specification bus; PCI-X bus control circuit 56B then can export the transmitting/receiving signal into pad 58B via each, with the device on the keyholed back plate service PCI-X specification bus.In other words, in integrated circuit 52, the output that AGP and PCI-X bus control circuit have respectively separately goes into to fill up 58A, 58B.

When the present invention will realize out the chipset 60A that can support AGP specification bus with integrated circuit 52, integrated circuit 52 can cooperate corresponding routing process planning in encapsulation process, each that makes AGP bus control circuit 56A exported can routing be electrically connected each ball seat 64 (bus ball seat just) to base plate for packaging 66A of pad 58A; So, AGP bus control circuit 56A just can be via I/O port 58A, ball seat 64 and transmitting/receiving signal, the control function of performance AGP bus.Relatively, each output of PCI-X bus control circuit 56B is gone into to fill up 58B and then can be electrically connected to each ball seat in this routing technology, and PCI-X bus control circuit 56B just can not have an effect naturally.In addition, this routing technology also can be gone into to fill up the 58C routing with the output of treatment circuit 54 and is electrically connected to each corresponding ball seat 62.

On the other hand, if in the time of will realizing out that another kind can be supported the chipset 60B of PCI-X bus with integrated circuit 52, then can utilize another kind of routing process planning, so that being gone into to fill up the 58B routing, each output of PCI-X bus control circuit 56B is electrically connected to each ball seat 64 (bus ball seat just), make PCI-X bus control circuit 56B go into to fill up 58B, ball seat 64 and transmitting/receiving signal, the control function of performance PCI-X bus via output.Relatively, in this routing technology, each of AGP bus control circuit 56A exported into pad 58A and just can be electrically connected to each ball seat by routing, is equivalent to make AGP bus control circuit 56A anergy and do not operate.Each output of treatment circuit 54 is gone into to fill up 58C and then can be electrically connected to each corresponding ball seat 62 by routing.Wherein, base plate for packaging 66A, 66B can be identical base plate for packaging.

As seen from the above description, the embodiment of the present invention in Fig. 4 continues to use with a kind of integrated circuit (even identical base plate for packaging), cooperate again with routing process plannings different in the encapsulation process, so that AGP and PCI-X bus control circuit one of them can obtain electric power and signal is gone in output, and realize out two kinds of difference in functionalitys, can support the chipset of AGP and PCI-X bus respectively with this.

In summary, the AGP and the PCI-X bus chip group that will design respectively, make in the prior art, as long as the present invention continues to use with a kind of integrated circuit or even same base plate for packaging and routing technology (as the embodiment of the present invention in Fig. 1), just can realize out the chipset of two kinds of difference in functionalitys respectively, so can significantly reduce the time and the cost of chipset design, production, development, satisfy the needs of various computing machine system.

The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.

Claims

1. chipset of supporting two kinds of bussing techniques, wherein, this chipset includes:

One first bus control circuit is in order to manage the signal exchange of one first kind of bussing technique;

One second bus control circuit is in order to manage the signal exchange of one second kind of bussing technique; And

One multiplex module, include a plurality of multiplexers, wherein, each of this first bus control circuit and this second bus control circuit exported the input end that is linked to this correspondence multiplexer into end respectively, and this multiplex module is managed this chipset and is accepted or transmit the signal of this first kind of bussing technique or the signal of this second kind of bussing technique according to a setting signal.

Wherein, the chipset of two kinds of bussing techniques of described support more includes a plurality of bus ball seats, be linked to the output terminal of these a plurality of multiplexers respectively, in order to binding as this first bus control circuit or this second bus control circuit and outside other circuit of this chipset.

2. the chipset of two kinds of bussing techniques of support as claimed in claim 1, wherein, more include at least one multiplex (MUX) and set ball seat, be linked to this multiplex module and this chipset circuit external, in order to bus kind, send this setting signal and give this multiplex module according to this external circuit.

3. the chipset of two kinds of bussing techniques of support as claimed in claim 2, wherein, this multiplex (MUX) sets ball seat can make this chipset can utilize the mode of terminal short circuit to select to support the signal of this first bussing technique or the signal of this second bussing technique.

4. the chipset of two kinds of bussing techniques of support as claimed in claim 3, wherein, when this chip enable, according to the external circuit that this chip linked determine this chipset support this first bussing technique or this second bussing technique one of them, and send this corresponding setting signal.

5. the chipset of two kinds of bussing techniques of support as claimed in claim 4, wherein, this multiplex module is provided with one and is linked to the setting signal buffer that this multiplex (MUX) sets ball seat, in order to receive this setting signal.

6. the chipset of two kinds of bussing techniques of support as claimed in claim 1, wherein, when the signal of this first kind of bussing technique select is supported in the control of accepting this setting signal when this chipset, then enable this first bus control circuit, this second bus control circuit of disable.

7. the chipset of two kinds of bussing techniques of support as claimed in claim 1, wherein, when the signal of this second kind of bussing technique select is supported in the control of accepting this setting signal when this chipset, then enable this second bus control circuit, this first bus control circuit of disable.

8. the chipset of two kinds of bussing techniques of support as claimed in claim 1, wherein, this first kind of bussing technique is the bussing technique that port specification is quickened in a drawing.

9. the chipset of two kinds of bussing techniques of support as claimed in claim 1, wherein, this second kind of bussing technique is the bussing technique of an enhancement type peripheral device interconnection specification.