KR20010086506A - Fuse circuit for semiconductor device - Google Patents

Abstract

PURPOSE: A fuse circuit for a semiconductor device is provided to prevent the malfunction of a fuse device by dividing certainly the cut-off state and the previous cut-off state of the fuse device. CONSTITUTION: A fuse device(F4) having resistance is connected to a voltage power supply terminal(VDD). The voltage of the voltage power supply terminal(VDD) is divided by a predetermined ratio. The first load device(R2) connects with the fuse device(F4) in series, and outputs the divided voltage with the resistance of the fuse device(F4). The second and the third load devices(R3, R4) are connected between the voltage power supply terminal(VDD) and a ground terminal(GND) in series. A switching circuit(TR3) is arranged between the second and the third load devices(R2, R3), receives the divided voltage, and generates an output signal corresponding to the cut-off or the connection of the fuse device(F4), so that an opening or closing operation is performed.

Description

Fuse circuit for semiconductor devices {FUSE CIRCUIT FOR SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to fuse circuits for semiconductor devices, and more particularly to fuse circuits to compensate for incomplete blows of semiconductor devices.

Fuse circuits for semiconductor devices (e.g., microprocessors, microcontrollers or memory devices, etc.) are typically repaired to repair memory cells, adjust transistor dimensions and delay or transmit pulse widths. Widely used.

In general, a common fuse circuit has a single fuse device as a set. In this case, when the cutting of the fuse device is incomplete, the expected operation cannot be obtained. To compensate for this, a circuit for connecting a fuse device in series is implemented. However, such a circuit has an difficulty in manufacturing an efficient semiconductor device by increasing the area of the fuse circuit in the semiconductor device, thereby increasing the size of the semiconductor device.

A fuse circuit according to the prior art is shown in FIGS. 1A-1C.

Referring to FIG. 1A, a fuse circuit 2a according to an exemplary embodiment of the prior art includes a fuse device F1 having a resistor (hereinafter referred to as a fuse resistor), a power supply terminal VDD, and a gate terminal. It consists of the NMOS transistor TR1. The fuse device F1 and the NMOS transistor TR1 are connected in series between a power supply voltage terminal VDD and a ground terminal GND, and are connected to a fuse circuit 2a at a drain terminal of the NMOS transistor TR1. An output signal of is generated.

In the case where the fuse circuit 2a is not interrupted by, for example, the fuse device F1, the NMOS transistor TR1 is always activated by the power supply voltage VDD connected to the gate terminal. Since the NMOS transistor TR1 has a resistance component in itself, the NMOS transistor TR1 operates as a resistor circuit connected in series with the fuse resistor. In practice, when the NMOS transistor TR1 is implemented in a semiconductor manufacturing process, the resistance value between the source terminal and the drain terminal of the NMOS transistor TR1 has a high value, so that the output signal Output has a value close to the power supply voltage VDD. Have.

When the fuse device F1 is cut off, the fuse resistor becomes open and does not affect the output signal. The output signal Output becomes the drain voltage value of the NMOS transistor TR1, which is close to the ground voltage GND because the NMOS transistor TR1 is activated.

However, when the fuse device F1 is incompletely cut, the fuse resistor has a residual material such as poly, tungsten silicon (WSi), or titanium nitride film (TiN) that forms the fuse circuit 2a. It acts as a resistance component. This can be confirmed through electrical verification, resulting in malfunction of the fuse circuit 2a and the semiconductor device including the same.

Table 1 shows the result of simulating the voltage value of the output signal Output according to the fuse resistance value using the fuse circuit 2a of FIG.

TABLE 1

Fuse resistance A B C D E F Output voltage value 2.0 V 1.99 V 1.99 V 1.99 V 1.10 V 1.72 mV

Referring to Table 1, the fuse resistance value is divided by a log scale, and in the case where the cutting of the fuse device F1 is completed, the fuse resistance value is outside the fuse resistance value F section. This is clearly distinguished from the fuse resistance section A section C section. In the case where the fuse resistance is incompletely cut out of the resistance value section in Table 1, a malfunction of the fuse circuit 2a occurs between the D section and the E section.

Referring to FIG. 1B, the fuse circuit 2b of another embodiment includes a fuse device F2, a resistor R1, and a pull-down device 4. The resistor R1 is connected in series to a power supply voltage terminal VDD and the fuse device F2. The pull-down device 4 is provided as a controllable switch (for example, an NMOS transistor) connected between the fuse device F2 and the ground terminal GND.

Referring to FIG. 1C, another example fuse circuit 2c includes a fuse device F3, an NMOS transistor TR2, and an inverter circuit 6. The fuse device F3 is connected to a power supply voltage terminal VDD and a source terminal of the NMOS transistor TR2. The NMOS transistor TR2 connects the output terminal of the inverter circuit 6 to a gate terminal, and the drain terminal is grounded. One end of the inverter circuit 6 is connected to the source terminal of the NMOS transistor TR2, and the other end thereof is connected to the output terminal Output.

The fuse circuits 2b and 2c of FIGS. 1b and 1c also have a fuse circuit because they are directly connected to an output terminal of the fuse circuit without a circuit that properly compensates for an incomplete cut state of the fuse resistor as described above with reference to FIG. Malfunctions and malfunctions of the semiconductor device occur.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, and to implement a fuse circuit for preventing a malfunction of a semiconductor device caused by an incomplete cutting state of the fuse device.

1A to 1C are circuit diagrams showing the configuration of a general fuse circuit;

2 is a circuit diagram showing the configuration of a fuse circuit according to an embodiment of the present invention; And

3 is a circuit diagram illustrating a configuration of a fuse circuit including a booster according to another embodiment of the present invention.

* Explanation of symbols on the main parts of the drawing *

10, 20: fuse circuit 22: boost circuit

F4: Fuse device R2, R3, R4: Fixed resistor

TR3: PMOS Transistor

According to an aspect of the present invention for achieving the above object, a fuse circuit of a semiconductor device provided between a power supply voltage terminal and a ground terminal, comprising: a fuse device having a resistance component connected to the power supply voltage terminal; A first load device connected in series with the fuse device and outputting a voltage divided by the proper distribution ratio with the resistance component of the fuse device; Second and third load devices connected in series between the power supply voltage terminal and the ground terminal; And a switching circuit provided between the second and third load devices, the switching device configured to receive the divided voltage and perform an open / close operation to generate an output signal in response to connection / disconnection of the fuse device. When incompletely cut, malfunction of the semiconductor device is prevented.

In a preferred embodiment of this aspect, the resistance value of the first load device has a resistance value that is greater than or equal to the resistance value of the state before the fuse device is cut, and the resistance value of the third load device is the second value. It has a resistance value that is greater than or equal to the resistance value of the load device.

In a preferred embodiment of this aspect, the output signal further includes a boosting circuit for boosting and outputting the output signal when the output signal is output as a signal having a level smaller than that of the logic logic high level signal.

Therefore, according to the present invention, the state before the fuse device is cut and the state when the fuse device is cut in accordance with the voltage divided by the fuse device and the first load device are clearly distinguished, thereby preventing malfunction of the fuse device in the incomplete cutting state. do.

(Example)

DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 shows a configuration of a fuse circuit for a semiconductor device according to an embodiment of the present invention.

Referring to the drawings, the fuse circuit 10 includes three, i.e., first to third, fixed resistors R2, R3, and R4 between the power supply voltage terminal VDD and the ground terminal GND. The fuse device F4 and one PMOS transistor TR3.

The fuse device F4 includes a resistance component (hereinafter referred to as a fuse resistor) and is connected in series with the second resistor R3. That is, one end is connected to the power supply voltage terminal VDD and the other end is connected to one end of the second resistor R3.

One end of the first resistor R2 is connected to a power supply voltage terminal VDD and the other end thereof is connected to a source terminal of the PMOS transistor TR3. The second resistor R3 is provided between the fuse device F4 and the ground terminal GND. One end of the third resistor R4 is connected to the drain terminal of the PMOS transistor TR3 and the other end is grounded.

Here, the second resistor R3 should be larger than the fuse resistor value of the uncut fuse device F4, and the resistance of the third resistor R4 should be larger than the first resistor value R2.

The PMOS transistor TR3 is connected in series with the first resistor R2, and a voltage divided by the fuse resistor and the second resistor R3 from a power supply voltage terminal VDD is applied to the PMOS transistor TR3. Is input to the gate terminal. The output signal Output of the fuse circuit 10 is generated from the drain terminal of the PMOS transistor TR3.

Therefore, when the fuse device F4 is not cut at the beginning, the power supply voltage VDD is supplied to the fuse resistor and the second resistor R3 in series. At this time, the voltage value Vnod1 of the node 1 nod1 is expressed by Equation 1 according to Ohm's law.

[Equation 1]

The voltage value Vnod1 obtained in Equation 1 is a voltage divided by the fuse resistor and the second resistor R3 from the power supply voltage VDD, and is supplied to the gate terminal of the PMOS transistor TR3. Therefore, the PMOS transistor TR3 is opened between the source terminal and the drain terminal. Since the voltage value Vnod1 of the node 1 nod1 opens between the source terminal and the drain terminal of the PMOS transistor TR3, the value of the second resistor R3 should be greater than or equal to the fuse resistance value. . At this time, the node 2 nod2 is opened from the power supply voltage terminal VDD and is connected to the ground GND to have a voltage close to 0V.

When the fuse device F4 is completely disconnected, the voltage value Vnod1 of Equation 1 becomes 0 V, whereby the PMOS transistor TR3 is activated and short circuited. That is, when the PMOS transistor TR3 is activated, the power supply voltage VDD is connected in series with the first resistor R2 and the third resistor R4, and the voltage value Vnod2 output to the node 2 nod2. Is equal to Equation 2 according to Ohm's law.

[Equation 2]

Vnod2 = saturation current value of PMOS transistor × third resistance value

Here, since the value of the third resistor R4 is larger, the voltage value before the fuse device F4 is cut and the level difference thereof are clearly distinguished, thereby implementing a fuse circuit having better characteristics.

For example, the resistance value of the first resistor R2 is 20 Ω, the second resistor R3 is 30 Ω and the third resistor R4 is 10 Ω, and the PMOS transistor TR3 is the NMOS of FIG. 1. In the case of having the same size as the transistor TR1 but having the opposite channel length and channel width of the NMOS transistor TR1, simulation results according to the change interval of the fuse resistance value are shown in Table 2.

TABLE 2

Fuse resistance A B C D E F Output voltage value 7.6 ㎵ 7.6 ㎵ 25 ㎷ 94 ㎷ 104 ㎷ 104 ㎷

Here, the fuse resistance value of each section is changed to a log scale, which is the same as the section of Table 1. Comparing Table 2 with Table 1, in the conventional fuse circuit 2a, the resistance value must be high between the interval E and the interval F to logically distinguish the high level (logical value 1) and the low level (logical value 0). The fuse circuit 10 of the present invention can distinguish logical values 0 and 1 from the interval B and the interval C.

If the output value of the node 2 (nod2) representing the logic value 1 is small, the fuse circuit 20 for solving this problem further includes a boosting circuit 22 at the output terminal Output, as shown in FIG. .

Referring to FIG. 3, the second resistor R3 is a resistor connected to a gate terminal of the PMOS transistor TR3 to adjust a level of a voltage for activating the PMOS transistor TR3, as shown in FIG. 2. It is equal to or greater than the resistance value. Since it is difficult to make a fuse resistor with a very precise target value in the semiconductor manufacturing process, the resistance value should be enough to compensate for this.

In addition, the first resistor R2 may have a resistance value of 0 or more, and the third resistor R4 may be provided as another semiconductor element (for example, a pull-down device) that serves as a resistor.

As described above, the present invention can prevent the malfunction of the semiconductor device caused by the incomplete cutting of the fuse device, and can be used without changing the circuit by adjusting the resistance value of the load device according to various types of fuse devices. Do.

The complementary yield can be improved by using the amplification concept of the transistor in the repair structure of the fuse circuit.

Claims (3)

In a fuse circuit of a semiconductor device provided between a power supply voltage terminal and a ground terminal: A fuse device having a resistance component connected to the power supply voltage terminal; A first load device connected in series with the fuse device and outputting a voltage obtained by dividing the power supply voltage together with a resistance component of the fuse device by an appropriate distribution ratio; Second and third load devices connected in series between the power supply voltage terminal and the ground terminal; A switching circuit provided between the second and third load devices, the switching circuit configured to receive the divided voltage and perform an open / close operation to generate an output signal in response to connection / disconnection of the fuse device; And a fuse circuit which prevents a malfunction of the semiconductor device when the fuse device is incompletely cut. The method of claim 1, The resistance value of the first load device has a resistance value that is greater than or equal to the resistance value of the state before the fuse device is cut off, And the resistance value of the third load device has a resistance value greater than or equal to the resistance value of the second load device. The method of claim 1, And a booster circuit for boosting and outputting the output signal when the output signal is output as a signal having a level smaller than that of a logic logic high level signal.