KR100429493B1 - Switching control circuit using an electric fuse - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching control circuit using an electrical fuse, comprising: a first switching element having a fuse resistor, one end connected to one end of the fuse resistor, a control terminal to which a fusing signal is applied, and the other terminal to which a power supply voltage is applied; A second switching element having one end connected to the other end and a control terminal connected to the control terminal of the first switching element and to which a fusing signal is applied; receiving and latching an input voltage from the other end of the second switching element and inverting the voltage And a latch circuit for receiving and outputting the output of the latch circuit to the internal circuit of the semiconductor device, wherein the first and second switching elements are turned off by the fusing signal during the fusing operation. Fusing the fuse resistor is characterized by.

The switching control circuit using the electrical fuse according to the present invention can adjust the resistance value without damaging the internal circuit of the semiconductor device, it is possible to adjust the current radiation amount of the current mirror circuit.

Description

Switching control circuit using electrical fuses {SWITCHING CONTROL CIRCUIT USING AN ELECTRIC FUSE}

The present invention relates to a switching control circuit, and more particularly to a switching control circuit using an electrical fuse.

Where a precise resistance value such as a reference circuit is required in a semiconductor device, the resistance inside the chip is trimmed and used. Conventional methods of trimming resistors include a fuse link method and a zener zapping method, which are shown in FIGS. 1 (a) and 1 (b), respectively.

Hereinafter, a conventional resistance trimming method will be described with reference to FIGS. 1A and 1B.

FIG. 1A illustrates a fuse link method in which fuses F1, F2, and F3 are connected in parallel to resistors R1, R2, and R3 constituting a trimming resistor, and are connected to both ends of each of the fuses F1, F2, and F3. A high current will cause the fuse to blow. When the fuses F1, F2, and F3 are all connected, a short circuit is formed between the A terminal and the D terminal, and the resistance value is zero. If only fuse (F3) is blown, only resistor (R3) acts as a resistor between terminal A and D. If fuse (F3) and fuse (F2) are blown, resistor (R2) and resistor ( R3) acts as a resistance. In addition, when the fuses F1, F2, and F3 are all blown, the resistors R1, R2, and R3 constituting the trimming resistor all act as resistors. That is, the fuse link method may increase the resistance value by breaking the fuse.

FIG. 1B illustrates a zener zapping method, in which zener diodes Z1, Z2, and Z3 are connected in parallel to resistors R1, R2, and R3 constituting a trimming resistor, and each zener diodes Z1, Z2, Z3) If a high current flows through both ends, the zener diode is short-circuited. When none of the Zener diodes Z1, Z2, Z3 is short-circuited, the resistors R1, R2, R3 constituting the trimming resistor all act as resistors. When only Zener diode Z3 is shorted, resistor R2 and R3 act as resistances between the A and D terminals, and when Zener diode Z3 and Zener diode Z2 are shorted, between A and D terminals. Only resistor R1 acts as a resistor. That is, the zener zapping method can reduce the resistance by shorting the zener diode.

However, in the conventional method as described above, there is a possibility that the high current used to blow the fuse enters the power line inside the semiconductor device and destroys the circuit implemented in the chip. In addition, the fuse link method shown in FIG. 1A can only increase the resistance value by making it open in a short state, and the fuse link method shown in FIG. 1B can only reduce the resistance from a large resistance value to a small resistance value. That is, none of the above-described conventional methods can implement both a function of changing from a low resistance value to a high resistance value and a function of changing from a high resistance value to a low resistance value.

An object of the present invention is to provide a switching control circuit using an electrical fuse that can adjust the resistance value without damaging the internal circuit of the semiconductor device.

Another object of the present invention is to provide a switching control circuit using an electrical fuse that can adjust the current radiation amount of the current mirror circuit.

1A illustrates a fuse link method as a conventional resistance trimming method.

1B is a diagram illustrating a zener zapping method as a conventional resistance trimming method.

2 is a diagram illustrating a resistance trimming apparatus using a switching control circuit according to the present invention.

3 is a view showing a switching control circuit according to the present invention.

FIG. 4 is a circuit diagram of the latch circuit block illustrated in FIG. 3 using a semiconductor device.

5 is a view showing a reference voltage generation circuit using a switching control circuit according to the present invention.

6 is a view showing a current mirror circuit using a switching control circuit according to the present invention.

<Description of Symbols for Main Parts of Drawings>

10: control circuit 11: buffer circuit

12: latch circuit 13, 14: protection resistor

15: fuse resistance 20: operational amplifier

The switching control circuit using the electrical fuse according to the present invention includes a fuse resistor; A first switching element having one end connected to one end of the fuse resistor, a control terminal to which a fusing signal is applied, and the other terminal to which a power supply voltage is applied; A second switching element having one end connected to the other end of the fuse resistor and a control terminal connected to a control terminal of the first switching element and to which the fusing signal is applied; And a latch circuit for receiving and latching an input voltage from the other end of the second switching element and inverting the voltage. And a buffer circuit configured to receive the output of the latch circuit and transmit the output to the internal circuit of the semiconductor device, and during the fusing operation, turn off the first and second switching elements by the fusing signal to fuse the fuse resistor. It is characterized by.

The latch circuit includes a first pull-up transistor having a source to which a power voltage is applied and a gate to which an input signal is applied; A first pull-down transistor having a drain connected to the drain of the first pull-up transistor, a gate to which the input signal is applied, and a source to which a ground voltage is applied; A second pull-up transistor having a source to which the power supply voltage is applied, a gate connected to a drain of the first pull-up transistor, and a drain to which the input signal is applied; And a second pull-down transistor having a drain to which the input signal is applied, a gate connected to an output terminal, and a source to which a ground voltage is applied, wherein the first, second pull-up and pull-down transistors have the same length, and the first pull-down transistor has the same length. The width of the pull-up transistor is larger than the width of the first pull-down transistor, characterized in that the width of the second pull-down transistor is equal to or greater than the width of the second pull-up transistor.

Hereinafter, a switching control circuit according to the present invention will be described with reference to the accompanying drawings.

2 is a diagram illustrating a resistance trimming apparatus using a switching control circuit according to the present invention.

The resistance trimming device of FIG. 2 includes switching elements Q1, Q2 and Q3 connected in parallel to each of the series connected resistors R1, R2 and R3 and the resistors R1, R2 and R3 constituting the trimming resistor. And a switching control circuit 10 connected to the control terminals of the switching elements Q1, Q2, and Q3, respectively.

The operation of the resistance trimming apparatus of FIG. 2 is as follows.

When the output voltage of the switching control circuit 10 is low, the switching element connected to the switching control circuit 10 is turned on. When the output voltage of the switching control circuit 10 is high, it is connected to the switching control circuit 10. The switching element is off. When the output voltages of the switching control circuits 10 connected to each of the switching elements Q1, Q2, and Q3 are all low, the switching elements Q1, Q2, and Q3 connected to each of the switching control circuits 10 are low. All of them are turned on, and a short circuit is formed between the A terminal and the B terminal, and the resistance value becomes zero. When the output voltages of the switching control circuits 10 connected to the switching element Q1 and the switching element Q2 are low, the switching elements Q1 and Q2 connected to the switching control circuit 10 are turned on and the resistance ( Only R3) acts as a resistance. In addition, when the output voltages of the switching control circuits 10 connected to each of the switching elements Q1, Q2, and Q3 are all high, the switching elements Q1, Q2, which are connected to each of the switching control circuits 10, respectively. Q3) is all off so that resistors R1, R2, and R3 all act as resistors. Therefore, the resistance in the circuit can be increased or decreased by the switching control circuit according to the present invention.

3 is a diagram illustrating a control circuit using an electrical fuse according to an embodiment of the present invention, in which a switching element having a fuse resistor 15, one end connected to one end of the fuse resistor 15, and a control terminal to which a fusing signal Vf is applied; Q5, a protection resistor 14 having one end connected to the other end of the switching element Q5 and the other end to which the power supply voltage Vdd is applied, and one end connected to the other end of the fuse resistor 15 and the switching element Q5. A switching element Q4 having a control terminal connected to a control terminal of the control element and having a fusing signal Vf applied thereto, and a protection resistor 13 and a protection resistor 13 having one end connected to the other end of the switching element Q4. A latch circuit 12 connected to the other end of the circuit to receive and latch a high or low signal, and receive the output of the latch circuit 12 and transmit the output to the control terminal of the control switch (Q1, Q2, Q3 in FIG. 2). Is connected to the input of the buffer circuit 11 and the latch circuit 12 for fusing It consists of a capacitor (C1) to mitigate the noise.

Hereinafter, the operation of the control circuit using the electrical fuse according to the present invention shown in FIG. In the control circuit of the present invention shown in FIG. 3, a P-type metal oxide semiconductor (PMOS) transistor is used as the switching elements Q4 and Q5, and polysilicon having a low resistance value is used as the fuse resistor 15. .

When not fusing, power is not applied between the two pads T1 and T2 that are outside the semiconductor chip, and a low fusing voltage Vf is applied to the control terminals of the switching elements Q4 and Q5. Q4 and Q5 are turned on and the fuse resistor 15 acts as a resistor. At this time, the power supply voltage Vdd is supplied to the latch circuit 12 through the protection resistor 14, the switching element Q5, the fuse resistor 15, the switching element Q4, and the protection resistor 13. The latch circuit 12 latches the input signal and outputs the inverted signal. Therefore, when a high in signal is input, the latch circuit 12 outputs a low in signal, which is applied to the control terminal of the control switches (Q1, Q2, and Q3 in FIG. 2) via the buffer circuit 11. . In this embodiment, since the PMOS transistor is used as the switching element, the control switches (Q1, Q2, and Q3 in FIG. 2) are turned on so that the resistors (R1, R2, and R3 in FIG. 2) that constitute the trimming resistor are short-circuited. do.

In the case of fusing, a high current power is applied between the two pads T1 and T2 extending out of the semiconductor chip to turn off the fuse resistor 15. At this time, a high fusing voltage Vf is applied to the control terminals of the switching elements Q4 and Q5 to turn off the switching elements Q4 and Q5. By turning off the switching elements Q4 and Q5, the circuit inside the semiconductor chip can be protected and the current consumed during fusing can be reduced. At this time, a potential that is low is formed at an input terminal of the latch circuit 12, and the output of the latch circuit 12 becomes high, and this signal passes through the buffer circuit 11 to control switches (Q1, Q2, Q3 in FIG. 2). Is applied to the control terminal. In this embodiment, since the PMOS transistor is used as the switching element, the control switches (Q1, Q2, and Q3 in FIG. 2) are turned off so that the resistors (R1, R2, and R3 in FIG. 2) that constitute the trimming resistor are used as resistors. It will work.

FIG. 4 is a circuit in which the latch circuit 12 block shown in FIG. 3 is implemented using a semiconductor element, and is composed of NMOS transistors Q7 and Q9 and PMOS transistors Q6 and Q8.

The latch circuit 12 shown in FIG. 4 includes a first pull-up transistor Q6 and a first pull-up transistor Q6 having a source to which a power supply voltage Vdd is applied and a gate to which an input signal is applied at a node N1. A first pull-down transistor Q7 having a drain connected to the drain and a gate to which an input signal is applied at a node N1 and a source to which a ground voltage is applied, and a drain of a source and a first pull-up transistor Q6 to which a power supply voltage is applied. And a second pull-up transistor having a connected gate and a drain to which the input signal is applied, and a second pull-down transistor having a drain to which the input signal is applied and a gate connected to the output node N2 and a source to which a ground voltage is applied.

The operation of the latch circuit 12 shown in FIG. 4 will be described below.

When a high voltage is applied to the node N1 between the drain of the second pull-up transistor Q8 and the drain of the second pull-down transistor Q9, the gate terminal of the first pull-up transistor Q6 and the first pull-down transistor Q7 is applied. Since the state becomes high, the first pull-up transistor Q6 is turned off and the first pull-down transistor Q7 is turned on so that the node N2 which is an output terminal of the latch circuit 12 is turned low. When a low voltage is applied to the node N1 between the drain of the second pull-up transistor Q8 and the drain of the second pull-down transistor Q9, the gate terminal of the first pull-up transistor Q6 and the first pull-down transistor Q7 is applied. Since the state becomes low, the first pull-up transistor Q6 is turned on and the first pull-down transistor Q7 is turned off so that the node N2, which is an output terminal of the latch circuit 12, is turned high. The latch circuit 12 maintains the current state unless a voltage of another logic state is applied to the node N1.

However, when the fuse is completed and the fuse resistor 15 is opened in the switching control circuit according to the present invention shown in Fig. 3, the state of the latch circuit 12 becomes a problem. In the present invention, in order to ensure the state of the latch circuit 12, the size of the first pull-up transistor Q6 shown in FIG. 4 is made larger than that of the first pull-down transistor Q6, and the size of the second pull-down transistor Q9 is made. Is made equal to the size of the second pull-up transistor Q8. In this embodiment, the lengths of the first, second pull-up and pull-down transistors are equal to L, the width of the first pull-up transistor Q6 is 6W, the width of the first pull-down transistor Q7 is W, and the second pull-up transistor ( The width of Q8) is 2W and the width of the second pull-down transistor Q9 is 2W. Increasing the size of the pull-up transistor improves the pull-up characteristic, while increasing the size of the pull-up transistor improves the pull-down characteristic. Even if the size of the second pull-down transistor Q9 is made the same as the size of the second pull-up transistor Q8, the pull-down characteristic is improved because the electron mobility is three times or more than the mobility of the hole. Therefore, in the switching control circuit according to the present invention, when the fuse resistor 15 is opened and the power supply voltage Vdd is not applied to the input node N1 of the latch circuit 12, the node N2 is kept in a high state. The state of node N1 is kept low.

5 is a view showing a reference voltage generation circuit using a switching control circuit according to the present invention.

In the reference voltage generating circuit according to the present invention shown in FIG. 5, an operational amplifier 20 for receiving an input voltage Vin and generating a reference voltage Vref is connected to an output terminal of the operational amplifier 20. Fixed resistor Rb, a trimming resistor 30 connected to the other end of the fixed resistor Rb, the other end of the trimming resistor 30 and a fixed input connected to the inverting input terminal of the operational amplifier 20. MOS transistors Q1, Q2, and Q3 connected to both ends of the resistors Ra, the resistors R1, R2, and R3 constituting the trimming resistor 30 to perform an on / off operation, and the MOS transistors. (Q1, Q2, Q3) are provided with control circuits 10 using electrical fuses connected to the respective gates to control each of the MOS transistors Q1, Q2, Q3.

Hereinafter, the operation of the reference voltage generation circuit according to the present invention shown in FIG. 5 will be described.

Since the operational amplifier 20 is an amplifier having a large voltage gain, the reference voltage Vref, which is the output of the operational amplifier 20, is determined by the values of the resistors connected to the output of the operational amplifier 20.

If the output voltage of the control circuit 10 is low, the switching element connected to the control circuit 10 is on. If the output voltage of the control circuit 10 is high, the switching element connected to the control circuit 10 is off. do. When the output voltages of the switching control circuits 10 connected to each of the switching elements Q1, Q2, and Q3 are all low, the switching elements Q1, Q2, and Q3 connected to each of the control circuits 10 are All are on and the trimming resistance is zero. When the output voltages of the control circuits 10 connected to the switching element Q1 and the switching element Q2 are low, the switching elements Q1 and Q2 connected to the control circuit 10 are turned on and the resistor R3 is turned on. Only acts as a resistance. In addition, when the output voltages of the control circuits 10 connected to each of the switching elements Q1, Q2, and Q3 are all high, the switching elements Q1, Q2, and Q3 connected to each of the control circuits 10 are high. These are all off so that resistors R1, R2, and R3 all act as resistors.

When the switching elements Q1, Q2, and Q3 connected to each of the control circuits 10 are all turned off so that the resistors R1, R2, and R3 all function as resistors, the reference voltage Vref is Vref = Vin x (1 + (Rb + R1 + R2 + R3) / Ra). When all of the switching elements Q1, Q2, and Q3 connected to each of the control circuits 10 are turned on, the reference voltage Vref becomes Vref = Vin x (1 + Rb / Ra).

Accordingly, in the reference voltage generating circuit according to the present invention shown in FIG. 5, the reference voltage Vref is controlled by controlling the value of the trimming resistance by turning on and off the switching elements Q1, Q2 and Q3 by the control circuit 10. Can be determined.

6 is a current mirror circuit using a switching control circuit according to the present invention, and is composed of NMOS transistors Q10 to Q13 and PMOS transistors Q14 and Q15.

The current mirror circuit of FIG. 6 has an NMOS transistor Q10 having a drain and a gate to which an input reference current In is applied, and a source to which a ground voltage is applied, and a gate and mirrored current Iout connected to the gate of the NMOS transistor Q10. ) Is connected in series between the NMOS transistor Q11 having a drain to which a ground voltage is applied and a source to which a ground voltage is applied, and a drain and a ground voltage of the NMOS transistor Q11, each gate being an output terminal and an NMOS of the switching control circuit 10. A PMOS transistor Q14 and an NMOS transistor Q12 connected to the gate of the transistor Q10, and a drain and ground voltage of the NMOS transistor Q11 are connected in series, and each gate is connected to an output terminal of the switching control circuit 10 and It is composed of a PMOS transistor Q15 and an NMOS transistor Q13 connected to the gate of the NMOS transistor Q10.

Hereinafter, the operation of the current mirror circuit according to the present invention shown in FIG. 6 will be described.

When the PMOS transistor Q14 and the PMOS transistor Q15 are in the on state by the control circuit 10, assuming that the sizes of the NMOS transistors Q10, Q11, Q12, and Q13 are the same, the output current Iout Iout = 3 x Iin, and the output current Iout becomes Iout = Iin when the PMOS transistor Q14 and the PMOS transistor Q15 are in the off state by the control circuit 10. Therefore, the amount of current radiation of the current mirror circuit can be adjusted by the control circuit according to the present invention.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

As described above, the switching control circuit using the electrical fuse according to the present invention can adjust the resistance value without damaging the internal circuit of the semiconductor device, it is possible to adjust the current radiation amount of the current mirror circuit.

Claims (9)

Fuse resistance; A first switching element having one end connected to one end of the fuse resistor, a control terminal to which a fusing signal is applied, and the other terminal to which a power supply voltage is applied; A second switching element having one end connected to the other end of the fuse resistor and a control terminal connected to a control terminal of the first switching element and to which the fusing signal is applied; And a latch circuit for receiving and latching an input voltage from the other end of the second switching element and inverting the voltage. And A buffer circuit for receiving the output of the latch circuit and transferring the output to the internal circuit of the semiconductor device, And controlling the fuse resistor to turn off the first and second switching elements by the fusing signal during the fusing operation. The method of claim 1, The other end of the first switching device is applied to the power supply voltage through a first protection resistor, and further comprising a second protection resistor disposed between the second switching device and the latch circuit. Control circuit used. The method according to claim 1 or 2, And a capacitor for mitigating noise at an input terminal of the latch circuit. The method of claim 1, And the first switching element and the second switching element are MOS transistors. The method of claim 1, wherein the latch circuit A first pull-up transistor having a source to which a power supply voltage is applied and a gate to which an input signal is applied; A first pull-down transistor having a drain connected to the drain of the first pull-up transistor, a gate to which the input signal is applied, and a source to which a ground voltage is applied; A second pull-up transistor having a source to which the power supply voltage is applied, a gate connected to a drain of the first pull-up transistor, and a drain to which the input signal is applied; And A second pull-down transistor having a drain to which the input signal is applied, a gate connected to an output terminal, and a source to which a ground voltage is applied; The length of the first, second pull-up and pull-down transistors is the same, the width of the first pull-up transistor is larger than the width of the first pull-down transistor, the width of the second pull-down transistor is the width of the second pull-up transistor Control circuit using an electrical fuse, characterized in that the same or more than. 6. The control circuit according to claim 5, wherein the width of the first pull-up transistor is four to eight times the width of the first pull-down transistor. 6. The control circuit according to claim 5, wherein the width of the second pull-down transistor is equal to the width of the second pull-up transistor. First switching elements connected in series and having one end connected to the high potential side and the other end connected to the low potential side; Control circuits connected to a control terminal of each of the first switching elements, Each of the control circuits Fuse resistance; A second switching element having one end connected to one end of the fuse resistor, a control terminal to which a fusing signal is applied, and the other terminal to which a power supply voltage is applied; A third switching element having one end connected to the other end of the fuse resistor and a control terminal connected to a control terminal of the second switching element and to which the fusing signal is applied; A latch circuit for receiving and latching an input voltage from the other end of the third switching element, and inverting and outputting the voltage; And A buffer circuit for receiving the output of the latch circuit and transferring the output to the internal circuit of the semiconductor device, And each of the first switching elements is turned on or off according to a state of a signal respectively received from the control circuits. The method of claim 8, And the first switching elements are MOS transistors.