KR100487500B1 - Buffer circuit of semiconductor apparatus - Google Patents

Abstract

The present invention relates to a buffer circuit having a slew rate adjustment function, comprising: an output driver 220 comprising transistors PM25 and NM25 complementary to each other; And a slew rate controller 210 for adjusting a slew rate, wherein the slew rate controller 210 includes: first and second inverters 211 and 212 for inverting and outputting an input signal; A first slew rate control unit (213) for turning on the transistor PM25 when the output terminal voltage level of the first inverter 211 is changed from a high level to a low level; And a second slew rate controller 214 for turning on the transistor NM25 when the output terminal voltage level of the second inverter 212 is changed from a low level to a high level, so that the input signal is at a low level from a high level. Is changed to, the transistor NM25 is turned on after the transistor PM25 is turned off; When the input signal is changed from the low level to the high level, the transistor NM25 is turned on after the transistor PM25 is turned off, thereby controlling the slew rate. Therefore, since there is no section in which the transistors PM25 and NM25 are turned on at the same time, the amount of current is remarkably reduced during switching, and thus the slew rate control effect is large. In particular, the slew rate can be adjusted by adjusting only the sizes of the transistors NM23 and PM23 composed of a transmission gate. Therefore, in the case of I / O cells having easy transistor sizing and having a gate array structure, a reduction in layout area can be obtained.

Description

BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer circuit of a semiconductor device, and more particularly to a buffer circuit having a slew rate adjustment function.

1 is a circuit diagram illustrating an example of a buffer circuit of a semiconductor device having a conventional slew rate controller.

As shown in FIG. 1, a buffer circuit of a semiconductor device including a conventional slew rate control unit includes a slew rate control unit 110 including first to fourth inverters 111 to 114. And an output driver 120 including a PMOS transistor PM10, an NMOS transistor NM10, a PMOS transistor PM11, and an NMOS transistor NM11, each of which outputs of the first to fourth inverters 111 to 114 are input to corresponding gate terminals thereof. do.

The PMOS transistor PM10 and the NMOS transistor NM10 are configured in series between a power supply voltage VDD and a power supply ground VSS, and outputs of the first and second inverters 111 and 112 are respectively applied to gate terminals. The PMOS transistor PM11 and the NMOS transistor NM11 are configured in series between a power supply voltage VDD and a power supply ground VSS, and outputs of the third and fourth inverters 113 and 114 are applied to the gate terminals, respectively.

The sizes of the first to fourth inverters 111 to 113 are adjusted so that the first and third inverters 111 and 113 switch faster than the second and fourth inverters 112 and 114. Therefore, each input signal supplied to the output driver 120 has a time difference. Therefore, the peak value of the switching current of the output driver 120 is reduced and a slew rate control effect is obtained.

However, in such a conventional case, it is very inconvenient because each inverter configured in the slew rate control circuit for providing an input signal to the output driver to be sized to suit the characteristics. In sizing, the size of the transistor configured in the output driver must also be considered.

In addition, depending on the sizing results of the four inverters, the layout size may be increased. In particular, in an I / O cell of a gate array structure, the number of transistors may be so large that the entire circuit may not be implemented in a limited region, and the slew rate cannot be adjusted as necessary. Cases frequently occurred.

Accordingly, an object of the present invention has been proposed to solve the above-mentioned problems, and is a buffer circuit of a semiconductor device having a slew rate control circuit capable of easily sizing for slew rate control and reducing a layout when the semiconductor circuit is implemented. To provide.

According to an aspect of the present invention for achieving the object of the present invention as described above, the output driver comprising a transistor complementary to each other; A buffer circuit of a semiconductor device comprising a slew rate controller for adjusting a slew rate, the slew rate controller comprising: (a) first and second inverters for inverting and outputting an input signal; (b) a first slew rate control unit for turning on one first conductive transistor configured in the output driver when the output terminal voltage level of the first inverter is changed from the first voltage level to the second voltage level; (c) a second slew rate control unit for turning on another second conductive transistor configured in the output driver when the output terminal voltage level of the second inverter is changed from the second voltage level to the first voltage level; And the second conductivity type transistor is turned on after the first conductivity type transistor is turned off when the voltage level of the input signal is changed from the first voltage level to the second voltage level. When the level is changed from the second voltage level to the first voltage level, the second conductivity type transistor is turned on after the first conductivity type transistor is turned off to adjust the slew rate.

In this embodiment, the first slew rate control unit: a transmission means for transmitting the output of the first inverter is connected to one end of the channel to the output terminal of the first inverter; A third inverter for inverting and outputting the output of the first inverter; The first conductivity type is applied to the gate terminal the output of the third inverter, the first power supply voltage is applied to one end of the channel and the other end is connected to the other end of the transmission means and the gate of the first conductivity type transistor of the output driver It includes a transistor.

In this embodiment, the transmission means is composed of a transmission gate in which a first power supply voltage is applied to the gate terminal to form a current path.

In this embodiment, the transmission gate consists of an NMOS transistor.

In this embodiment, the second slew rate control unit: transmission means for transmitting the output of the second inverter is connected to one end of the channel to the output terminal of the second inverter; A fourth inverter for inverting and outputting the output of the second inverter; The second conductive type is provided with the output of the fourth inverter applied to the gate terminal, the second power supply voltage applied to one end of the channel, and the other end connected to the other end of the transmission means and the gate of the second conductive transistor of the output driver. It includes a transistor.

In this embodiment, the transmission means comprises a transmission gate in which a second power supply voltage is applied to the gate terminal to form a current path.

In this embodiment, the transmission gate is comprised of PMOS transistors.

According to another feature of the present invention, there is provided an output driver including a first conductive transistor and a second conductive transistor complementary to each other; A buffer circuit of a semiconductor device comprising a slew rate controller for adjusting a slew rate, the slew rate controller comprising: first and second inverters for inputting and inverting the same signal; First transmission means connected to an output terminal of the first inverter to transmit an output of the first inverter; A third inverter for inverting and outputting the output of the first inverter; A first conductive voltage is applied to a gate terminal, a first power supply voltage is applied to one end of the channel, and the other end is connected to the other end of the transmission means and the gate terminal of the first conductivity type transistor of the output driver. A transistor; Second transmission means connected to an output terminal of the second inverter to transmit an output of the second inverter; A fourth inverter for inverting and outputting the output of the second inverter; An output of the fourth inverter is applied to a gate terminal, a second power supply voltage is applied to one end of the channel, and the other end is connected to the other end of the second transfer means and the gate terminal of the second conductivity type transistor of the output driver; It includes a two-conductor transistor.

In this embodiment, the first transfer means comprises a transmission gate in which a first power supply voltage is applied to the gate terminal to form a current path.

In this embodiment, the transmission gate consists of an NMOS transistor.

In this embodiment, the second transfer means comprises a transmission gate in which a second power supply voltage is applied to the gate terminal to form a current path.

In this embodiment, the transmission gate is comprised of PMOS transistors.

According to the present invention as described above, since there is no section in which the PMOS transistor PM25 and the NMOS transistor NM25 configured at the same time are turned on at the same time, the amount of current is significantly reduced during switching, so that the slew rate control effect can be obtained. In particular, since only the size of the two transistors composed of the transmission gate is adjusted, the slew rate can be adjusted. Compared to the conventional slew rate control unit, an I / O cell having a easier sizing and a gate array structure can greatly reduce the layout area.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of a buffer circuit of a semiconductor device having a slew rate controller according to a preferred embodiment of the present invention.

As shown in FIG. 2, the novel buffer circuit of the present invention is largely composed of a slew rate controller 210 and an output driver 220. The output driver 220 includes a PMOS transistor PM25 and an NMOS transistor NM25 configured in series between a power supply voltage VDD and a ground voltage VSS. The connection node of the PMOS transistor PM25 and the NMOS transistor NM25 is connected to the output terminal 202.

The slew rate controller 210 includes first and second inverters 211 and 212 for inputting and inverting the same signal; An NMOS transistor NM23 having one end connected to an output terminal of the first inverter 211 and having a transmission gate for transmitting an output of the first inverter 211; A third inverter 215 for inverting and outputting the output of the first inverter 211; The output of the third inverter 215 is applied to the gate terminal, the power supply voltage VDD is applied to one end of the channel, and the other end is the other end of the NMOS transistor NM23 and the gate terminal of the PMOS transistor PM25 of the output driver 220. A PMOS transistor PM24 connected to the; A PMOS transistor PM23 composed of a transmission gate having one end connected to an output terminal of the second inverter 212 and transmitting an output of the second inverter 212; A fourth inverter 216 for inverting and outputting the output of the second inverter 212; The output of the fourth inverter 216 is applied to the gate terminal, the ground voltage VSS is applied to one end of the channel, and the other end is the other end of the PMOS transistor PM23 and the gate terminal of the PMOS transistor PM25 of the output driver 220. It is configured to include a PMOS transistor PM24 connected to.

The operating characteristics of the slew rate adjusting unit 210 configured as described above are as follows.

Referring to FIG. 2, the NMOS transistor NM23 transmits a signal of a ground voltage (VSS) level well but a signal of a power supply voltage (VDD) level as a voltage lower than a threshold voltage. At this time, when a signal having a ground voltage (VSS) level is applied to the gate terminal of the PMOS transistor PM24 through the third inverter 215, the PMOS transistor PM24 is turned on to a node Y1 connected to the gate terminal of the PMOS transistor PM25. A signal having a sufficient power supply voltage VDD level is applied.

On the contrary, the PMOS transistor PM23 transmits a signal of a power supply voltage (VDD) level well, but transmits a signal of a ground voltage (VSS) level to a voltage as high as a threshold voltage. At this time, when a signal having a power supply voltage (VDD) level is applied to the gate terminal of the NMOS transistor NM24 through the fourth inverter 216, the NMOS transistor NM24 is turned on to a node Y2 connected to the gate terminal of the NMOS transistor NM25. The signal of sufficient ground voltage (VSS) level is applied. The slew rate adjusting unit 210 as described above inverts the input signal A input to the input terminal 201 and outputs it to the two nodes Y1 and Y2.

The overall operation of the above circuit will be described with reference to FIGS. 2 to 3.

FIG. 3 is a waveform diagram illustrating changes of two nodes Y1 and Y2 according to a change in an input signal of an input terminal of the buffer circuit shown in FIG. 2.

First, referring to FIGS. 2 to 3, the operation when the input signal A progresses from the low level to the high level is as follows.

The output of the first inverter 211 proceeds from a high level to a low level, and a high level signal is applied to the gate terminal of the PMOS transistor PM24 through the third inverter 215. Therefore, the PMOS transistor PM24 proceeds from the turned on state to the turned off state. Therefore, a signal is transferred from the high level to the low level through the NMOS transistor NM23. At this time, if the size of the NMOS transistor NM23 is adjusted to be small, the transmission gate resistance value is increased, so that a delay time for transferring the change of the input signal A to the node Y1 is increased.

In addition, the output of the second inverter 212 also progresses from a high level to a low level, and a high level signal is applied to the gate terminal of the NMOS transistor PM24 through the fourth inverter 216. Accordingly, the NMOS transistor NM24 proceeds from a turn off state to a turn on state. Therefore, the signal of the level of the ground voltage VSS is output to the node Y2 through the NMOS transistor NM24. In this case, the signal is transferred from the high level to the low level through the PMOS transistor PM23 composed of the transmission gate later than that by the NMOS transistor NM24. Therefore, the delay time at which the change of the input signal A is transmitted to the node Y2 becomes short.

Therefore, as shown in FIG. 3, when the input signal is changed from the low level to the high level 310, the node Y2 first changes from the high level to the low level, and after a certain time, the node Y1 changes from the high level to the low level. Is changed to 320. Therefore, the output driver outputs a high level signal.

Again, when the input signal A is changed from high level to low level, the operation is as follows.

An output of the first inverter 211 proceeds from a low level to a high level, and a high level signal is applied to the gate terminal of the PMOS transistor PM24 through the third inverter 215. Accordingly, the NMOS transistor NM24 proceeds from a turn off state to a turn on state. Therefore, a signal having a power supply voltage (VDD) level is output to the node Y1 through the PMOS transistor PM23. In this case, it is later than that by the PMOS transistor PM24 that the signal is transferred from the low level to the high level through the NMOS transistor NM23 having the transmission gate. Therefore, the delay time at which the change of the input signal A is transmitted to the node Y1 becomes short.

In addition, the output of the second inverter 212 proceeds from a low level to a high level, and a low level signal is applied to the gate terminal of the NMOS transistor NM24 through the fourth inverter 216. Accordingly, the NMOS transistor NM24 proceeds from a turn on state to a turn off state. Therefore, a signal is transferred from the low level to the high level through the PMOS transistor PM23. At this time, if the size of the PMOS transistor PM23 is adjusted to be small, the transmission gate resistance value is increased, and thus the delay time for transmitting the change of the input signal A to the node Y2 is increased.

Therefore, as shown in FIG. 3, when the input signal is changed from the high level to the low level 350, the node Y1 is first changed from the low level to the high level, and after a predetermined time, the node Y2 is changed from the low level to the high level. The level is changed to 360. Therefore, the output driver outputs a high level signal.

According to the present invention as described above, since there is no section in which the PMOS transistor PM25 and the NMOS transistor NM25 configured in the output driver 220 are turned on at the same time, the amount of current is significantly reduced during switching, so that the slew rate control effect can be obtained. . In particular, since only the size of the two transistors composed of the transmission gate is adjusted, the slew rate can be adjusted. In addition, compared to the conventional slew rate control unit, an I / O cell having an easy sizing and having a gate array structure has an effect of greatly reducing the layout area.

1 is a circuit diagram illustrating an example of a buffer circuit of a semiconductor device having a conventional slew rate controller;

2 is a circuit diagram of a buffer circuit of a semiconductor device having a slew rate control unit according to a preferred embodiment of the present invention; And

3 is a waveform diagram showing changes in two nodes Y1 and Y2 according to a change in an input signal of an input terminal of the buffer circuit shown in FIG.

* Description of the symbols for the main parts of the drawings *

110, 210: slew rate control unit 120, 220: output drive unit

111 to 114, 211 to 214: inverter

Claims (12)

An output driver 220 composed of complementary transistors PM25 and NM25; In the buffer circuit of the semiconductor device comprising a slew rate control unit 210 for adjusting the slew rate, The slew rate adjusting unit 210 is: (a) first and second inverters 211 and 212 for inverting and outputting an input signal; (b) When the output terminal voltage level of the first inverter 211 is changed from the first voltage level (high level) to the second voltage level (low level), one first conductivity configured in the output driver 220 A first slew rate controller 213 for turning on the type transistor PM25; (c) Another second conductivity type transistor NM25 configured in the output driver 220 when the output terminal voltage level of the second inverter 212 is changed from the second voltage level to the first voltage level. Including a second slew rate control unit 214 to turn on, When the voltage level of the input signal is changed from the first voltage level to the second voltage level, the second conductivity type transistor NM25 is turned on after the first conductivity type transistor PM25 is turned off. When the voltage level of the input signal is changed from the second voltage level to the first voltage level, after the first conductivity type transistor PM25 is turned off, the second conductivity type transistor NM25 is turned on so that the slew rate is reduced. A buffer circuit, characterized in that the adjustment. The method of claim 1, The first slew rate adjusting unit 213 is: One end of a channel is connected to an output terminal of the first inverter 211 to transfer the output of the first inverter NM23; A third inverter 215 for inverting and outputting the output of the first inverter 211; The output of the third inverter 215 is applied to the gate terminal, the first power supply voltage VDD is applied to one end of the channel, and the other end thereof is the other end of the transmission means NM23 and the first end of the output driver 220. And a first conductive transistor (PM24) connected to the gate of the conductive transistor (PM25). The method of claim 2, The delivery means NM23 A buffer circuit comprising a transmission gate (NM23) in which a first power supply voltage (VDD) is applied to a gate terminal to form a current path. The method of claim 3, wherein And the transmission gate (NM23) is an NMOS transistor. The method of claim 1, The second slew rate control unit 214 is: One end of a channel is connected to an output terminal of the second inverter 212 to transfer the output of the second inverter PM23; A fourth inverter 216 for inverting and outputting the output of the second inverter 212; The output of the fourth inverter 216 is applied to the gate terminal, the second power supply voltage VSS is applied to one end of the channel, and the other end thereof is the other end of the transmission means PM23 and the second end of the output driver 220. And a second conductive transistor (NM24) connected to the gate of the conductive transistor (NM25). The method of claim 5, wherein The delivery means PM23 A buffer circuit comprising a transmission gate (PM23) in which a second power supply voltage (VSS) is applied to the gate terminal to form a current path. The method of claim 6, The transmission gate (PM23) is a buffer circuit, characterized in that the PMOS transistor. An output driver 220 including a first conductive transistor PM25 and a second conductive transistor NM25 complementary to each other; In the buffer circuit of the semiconductor device comprising a slew rate control unit 210 for adjusting the slew rate, The slew rate adjusting unit 210 is: First and second inverters 211 and 212 which input, invert, and output the same signal; First transmission means (NM23) connected at one end to an output terminal of the first inverter (211) to transmit an output of the first inverter (211); A third inverter 215 for inverting and outputting the output of the first inverter 211; The output of the third inverter 215 is applied to the gate terminal, the first power supply voltage VDD is applied to one end of the channel, and the other end is the other end of the transmission means NM23 and the first of the output driver 220. A first conductive transistor PM24 connected to the gate terminal of the conductive transistor PM25; Second transmission means (PM23) connected at one end to an output terminal of the second inverter (212) to transfer an output of the second inverter (212); A fourth inverter 216 for inverting and outputting the output of the second inverter 212; The output of the fourth inverter 216 is applied to the gate terminal, the second power supply voltage VSS is applied to one end of the channel, and the other end of the second transmission means PM23 and the output driver 220 And a second conductive transistor (PM24) connected to the gate terminal of the second conductive transistor (PM25). The method of claim 8, The first delivery means NM23 And a transmission gate configured to apply a first power supply voltage (VDD) to the gate terminal to form a current path. The method of claim 9, And said transmission gate is an NMOS transistor. The method of claim 8, The second delivery means PM23 And a transmission gate configured to apply a second power supply voltage (VSS) to the gate terminal to form a current path. The method of claim 11, And said transmission gate is a PMOS transistor.

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