JPH0993116A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for timing adjustment accompanying the adjustment of a slew rate by revising a power supply voltage for a pre-stage inverter gate and a post-stage inverter gate in opposite directions with the same quantity. SOLUTION: A 1st inverter gate 5 is provided in a 1st path 2 and a 2nd inverter gate 6 is provided in a 2nd path 3. A 3rd inverter gate 8 is provided in the post stage of the 1st inverter gate 5 and a 4th inverter gate 9 is provided in a post stage of the 2nd inverter gate 6. That is, two stages of the inverter gates of the same configuration are provided in each path. A control signal is provided reversely in the 1st inverter gate 5 and the 2nd inverter gate 6 with each other and a control signal is provided reversely in the 2nd inverter gate 6 and the 4th inverter gate 9 with each other. That is, the delay in the pre-stage and the post-stage inverter gates is set complementarily.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit equipped with a slew rate adjusting function for output signals. In recent years, the operating speed of semiconductor integrated circuits has been remarkably improved, and for example, CPUs exceeding 100 MHz (clock speed) are not uncommon, but when such a high-speed type semiconductor integrated circuit is mounted on a printed circuit board, the system may depend on the design of the printed circuit board. The operation sometimes became unstable. Most of the output signals from the high-speed type semiconductor integrated circuit are synchronized with the clock speed of the semiconductor integrated circuit, and the rising and falling edges of the signal are extremely sharp. In general, it is known that a signal waveform that changes abruptly (typically, a square wave) includes n times (n is an integer) higher harmonics around the repetition frequency of the signal, and the maximum value of n is , The larger the waveform changes, the larger it becomes. Therefore, an electromagnetic radiation wave is generated from the transmission line of the printed circuit board on which the high-speed type semiconductor integrated circuit is mounted, and for example, noise may be induced in the adjacent transmission line, resulting in unstable system operation. there were.
Therefore, it is necessary to select a printed circuit board on which a high-speed type semiconductor integrated circuit is mounted, which is close to a dedicated product that has effective frequency countermeasures by widening the transmission line intervals and providing electromagnetic shielding. However, since a general-purpose printed circuit board cannot be used, there are inconveniences such as an increase in system cost and a loss of flexibility in system configuration.

[0002]

2. Description of the Related Art FIG. 3 is a known so-called "slew rate adjusting circuit" devised to solve the above-mentioned inconvenience. In FIG. 3, IN is a signal created inside the semiconductor integrated circuit, and as described above, IN is a signal having an extremely steep rise and fall waveform. Signal IN
Is inverted in the buffer 1 and then divided into two paths (referred to as a first path 2 and a second path 3 for convenience),
Finally, it is taken out from the buffer 4 as the output signal OUT.

A first inverter gate 5 is provided on the first path 2. In addition, the second route 3 has a second
Inverter gate 6 is provided. These two inverter gates 5 and 6 have the same structure and integrally form a slew rate adjusting means. The structure of the first inverter gate 5 will be described as a representative.
Is a P channel MOS transistor T _P51 and an N channel M
A general CMOS inverter gate portion consisting OS transistor T _{N5 1,} the variable resistive load unit 5b of the high potential side between the T _P51 the high potential power supply Vcc is, also, T _N51
The variable resistance load unit 5c on the low potential side is connected between the low potential power supply (typically ground) and the low potential power supply. The first subscript of the transistor represents the code of the first or second inverter gate. For example, the first subscript of T _N51 is "5", so this T _N51 is the first
Inverter gate 5 CMOS inverter gate unit 5
It is shown to be an N-channel MOS transistor of a. The two variable resistance load units 5b and 5c are composed of a plurality (three, although not particularly limited) of MOS transistors connected in parallel, and the channel type (conductivity type) of the transistors is not on the high potential side. P channel (T
_P52 , _TP53 , _TP54 ) and, on the low potential side, N channels ( _TN52 , _TN53 , _TN54 ).

Here, one transistor (the transistor at the left end in the figure) of each variable resistance load section 5b, 5c is C
It is designed to turn on at the same time as the transistors of the same conductivity type of the MOS inverter gate section 5a, that is, T
The gate of _P52 is connected to the low potential power supply and T _N52
Has its gate connected to Vcc, and further other transistors (in the figure, the center and rightmost transistors; T _P53 ,
T _P54 , T _N53 , T _{N5 4} , T _P63 , T _P64 , T _N63 , T
_N64 ) is turned on / off according to the logic of predetermined control signals T _C1 , T _C2 and its inverted signals T _C1 bar, T _C2 bar. Specifically, T _P53 and T _P63 are turned on and off according to the logic of T _C1 bar, T _P54 and T _{P6 4} are turned on and off according to the logic of T _C2 bar, and T _N53 and T _N63 are turned on and off according to the logic of T _C1 , T _N54 and T _N64 are turned on and off according to the logic of T _C2 . Note that FIG. 4 shows the predetermined control signals T _C1 and T _C2 and their inverted signals T _C1 and T _C2.
It is a circuit diagram for generating a bar. Control signals T _C1 , T
_C2 is taken out as it is, and the inverter gate 7a,
The inverse logic signals T _C1 and T _C2 are taken out via 7b.

The following Tables 1 and 2 show the logics of the control signals T _C1 and T _C2 and the transistors (T _P53 , T _P54 , T _N53 , T _N54 and T _{P63) of} the variable resistance load units 5a, 5b, 6a and 6b. T
_P64 , _TN63 , _TN64 ) on / off operation. However, ON represents an ON state and − represents an OFF state.

In Tables 1 and 2, control No. = 0 (T _C1 ,
When both T _C2 are "L" logic, all the transistors are off. Therefore, at this time, the first
And only one transistor (T _P52 , T _N52 , T _P62 , T _N62 ) at the left end of each variable resistance load section 5b, 5c, 6b, 6c of the second inverter gates 5, 6 is turned on. Resistive load parts 5b, 5c, 6b, 6c
The resistance value of 1 is given by the value of the channel on resistance of one transistor (represented by R ₀ for convenience).

Next, when the control No. = 1, in addition to the above-mentioned one transistor (T _P52 , T _N52 , T _P62 , T _N62 ), the central transistor (T _P53 , T _N53 , T _P63 ,
T _{N6 3} ) is also turned on. Therefore, the resistance value of each variable resistance load unit 5b, 5c, 6b, 6c at this time is a parallel combined value of the channel on resistance of one transistor and the channel on resistance of the central transistor (for convenience, R
Represented by ₁ ).

Next, when the control No. = 2, in addition to the above-mentioned one transistor (T _P52 , T _N52 , T _P62 , T _N62 ), the rightmost transistor (T _P54 , T _N54 , T _P64 ,
T _{N6 4} ) is also turned on. Therefore, the resistance value of each variable resistance load unit 5b, 5c, 6b, 6c at this time is a parallel combined value of the channel on resistance of one transistor and the channel on resistance of the transistor at the right end (for convenience, R
Represented by ₂ ).

Finally, when the control No. = 3, the above-mentioned one transistor (T _P52 , T _N52 , T _P62 , T
_N62 ), central transistor (T _P53 , T _N53 , T
_P63 , T _N63 ) and the rightmost transistor (T _P54 , T
_N54 , T _P64 , T _N64 ) are all turned on. Therefore, at this time, the variable resistance load units 5b, 5c, 6
The resistance values of b and 6c are the channel on resistance of one transistor and the channel on resistance of the central transistor,
It is given by a parallel combined value (represented by R ₃ for convenience) with the channel on resistance of the transistor at the right end.

From the above, assuming that the channel on resistances of the respective transistors are substantially equal to each other, the following equation holds. R ₀ > R ₁ (= R ₂ ), and R ₁ (= R ₂ )> R ₃ ...... Therefore, according to the equation, the CMOS inverter gate section 5 a of the first and second inverter gates 5 and 6 is obtained. , 6a
The power supply voltage applied to the high (R ₃ ), medium (R ₂ or R
₁ ) and small (R ₀ ) can be switched to three stages, so the slope of rising and falling of the input signal IN can be changed in three stages according to the magnitude of the power supply voltage, and the slew rate can be changed. It is possible to obtain the output signal OUT which is adjusted.

FIG. 5 is a correspondence diagram of the input signal IN and the output signal OUT. As the output signal OUT, three waveforms A, B, and
C is shown. The waveform A has almost the same rising slope as the input signal IN, but the rising is gentle in the order of the waveform B and the waveform C. Waveform A is control N
When o. = 3 (R ₃ ), waveform B is control No. = 2
In the case of (or 1) (R ₂ or R ₁ ), the waveform C is in the case of control No. = 0 (R ₀ ). It is sufficient to select the optimum control No. that corresponds to the characteristics of the printed circuit board.

[0012]

However, in such a conventional semiconductor integrated circuit, the rise and fall of the output signal OUT is controlled by adjusting the power supply voltage of the first and second inverter gates 5 and 6. Since the slew rate is controlled by adjusting the slope of the output signal OUT, there is a disadvantage that the signal delay increases as the rising or falling slope of the output signal OUT becomes gentle as shown in FIG. In order to avoid the skew, there is a problem that the signal timing between the semiconductor integrated circuits must be finely adjusted.

Therefore, an object of the present invention is to eliminate the need for timing adjustment associated with slew rate adjustment.

[0014]

In order to achieve the above-mentioned object, the present invention changes the power supply voltage of the inverter gate so that the slope of rising or falling of a signal output through the inverter gate is changed. In a semiconductor integrated circuit having a slew rate adjusting means for adjusting, the inverter gate has a two-stage configuration, and the power supply voltages of both the front-stage inverter gate and the second-stage inverter gate can be changed in the same amount and in opposite directions. A power supply voltage changing means is provided.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a semiconductor integrated circuit according to the present invention. In the following description,
The same components as those of the conventional example are designated by the same reference numerals, and the description thereof will be omitted.

The first path 2 is provided with a first inverter gate 5 similar to the conventional example, and the second path 3 is also provided with a second inverter gate 6 similar to the conventional example. Although provided, in the present embodiment, a third inverter gate 8 is further provided after the first inverter gate 5 and a fourth inverter gate 9 is provided after the second inverter gate 6. There is. That is, two stages of inverter gates having the same structure are provided for each path.
Also in this embodiment, the first subscript of the transistor indicates the reference numeral of the first to fourth inverter gates. For example, since the first subscript of T _N82 is "8", this _indicates that T _N81 is the N-channel MOS transistor of the CMOS inverter gate portion 8a of the third inverter gate 8.

Here, the first inverter gate 5 and the third inverter gate 5
Control signal (T_C1, T_C2,
T_C1Bar, T_C2The way of giving a bar is the opposite. Similarly, the
2 inverter gates 6 and 4th inverter gate 9
The method of giving the same control signal to the opposite is also the reverse. For example, the first
In the variable resistance load section 5b on the high potential side of the inverter gate 5,
Is T_C1Bar and T_C2Variable resistance on the low potential side given the bar
The load section 5c has a T_C1And T_C2Is given, but the third
In the variable resistance load section 8b on the high potential side of the inverter gate 8
Is T_C1And T_C2Variable resistance load unit 8 on the low potential side
T for c_C1Bar and T_C2A bar is given. like this
By applying an inverse logic control signal to the
Power supply for both the inverter gate and the inverter gate in the latter stage
The pressure can be changed in the same amount and in the opposite direction. did
Therefore, the control signal T_C1, T_C2, T _C1Bar, T_C2Bar and
And each of the first to fourth inverter gates 5, 6, 8, 9
Variable resistance load parts 5b, 5c, 6b, 6c, 8b, 8c,
9b and 9c are integrated as a power supply voltage described in the gist of the invention.
It has a function as a changing means.

Next, the operation will be described. In Tables 1 and 2 above, if control No. = 0, the first inverter gate 5
Alternatively, the slope of rising and falling of the signal appearing at the output of the second inverter gate 6 becomes the gentlest, and the delay amount of the signal becomes maximum, and the control No. =
When it is set to 3, the slope of the rising or falling of the signal appearing at the output of the first inverter gate 5 or the second inverter gate 6 becomes the steepest and the delay amount of the signal becomes the minimum. The operations of the inverter gate 8 and the fourth inverter gate 9 are completely opposite.

That is, when the control No. = 0, the third
Of the signal appearing at the output of the inverter gate 8 or the fourth inverter gate 9 becomes steepest, and the amount of delay of the signal becomes the smallest,
Further, when the control No. = 3, the rising or falling slope of the signal appearing at the output of the third inverter gate 8 or the fourth inverter gate 9 becomes the gentlest, and the delay amount of the signal becomes maximum. Become. Table 3 below shows the control
This is a summary of the relationship between No. and delay amount.

[0020] As can be seen from Table 3, the delay amounts of the first and second inverter gates (5, 6) and the third and fourth inverter gates (8, 9) are in a mutually complementary relationship. is there. Therefore, the output signal OUT of the present embodiment has the control No. as shown by the three waveforms A ', B', and C'in FIG.
With reference to the waveform B'when = 1 (2), the waveform A'is located before it and the waveform C'is located after it. As a result, the slew rate is adjusted by changing the slope of the waveform. Even in this case, the delay time can be made constant and the timing adjustment can be made unnecessary.

In the above embodiment, the variable resistance load unit 5
Although the transistors b, 5c, 6b, 6c, 8b, 8c, 9b, and 9c have the same channel on-resistance, they have the same magnitude, but the present invention is not limited to this. It is possible to obtain the number of slew rate adjustment stages corresponding to the control No. (4 stages if the No. is 0 to 3) by making an appropriate difference in the channel on resistance.

[0022]

According to the present invention, the delay amounts of the front and rear inverter gates complement each other. Therefore, even when the slew rate is adjusted, the delay time can be kept constant and the timing adjustment can be made. Can be eliminated.

[Brief description of drawings]

FIG. 1 is a configuration diagram of one embodiment.

FIG. 2 is a signal waveform diagram of an example.

FIG. 3 is a configuration diagram of a conventional example.

FIG. 4 is a circuit diagram of a control signal generation circuit.

FIG. 5 is a signal waveform diagram of a conventional example.

[Explanation of symbols]

5: 1st inverter gate (slew rate adjusting means) 6: 2nd inverter gate (slew rate adjusting means) 5a, 6a, 8a, 9a: CMOS inverter gate part (inverter gate) 5b, 5c, 6b, 6c, 8b, 8c, 9b, 9c: Variable resistance load section (power supply voltage changing means)

Claims (1)

[Claims] 1. A semiconductor integrated circuit having slew rate adjusting means for adjusting the slope of rising or falling of a signal output via the inverter gate by changing the power supply voltage of the inverter gate. And a power supply voltage changing means capable of changing the power supply voltages of both the front-stage inverter gate and the rear-stage inverter gate by the same amount and in opposite directions.