JP2827473B2 - Variable delay circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a variable delay circuit. More specifically, the present invention relates to a variable delay circuit which is one of semiconductor integrated circuits, and relates to a novel circuit configuration capable of changing a propagation delay time.

2. Description of the Related Art Generally, in a conventional variable delay circuit, no means is provided for changing the delay time. Therefore, when it is necessary to change the delay time of the logic gate, a method of increasing the delay time by reducing the power consumption of the variable delay circuit is used.

However, according to the conventional method of increasing the delay time by reducing the power consumption of the circuit, the logic amplitude inside the variable delay circuit also decreases as the power consumption decreases, so that noise is affected. And the jitter increases.

Accordingly, an object of the present invention is to provide a completely new variable delay circuit that can change the delay time while securing a sufficient logic amplitude as a variable delay circuit.

Means for Solving the Problems According to the present invention, there is provided a variable delay circuit for holding an input signal for a certain delay time and outputting the held signal. The variable delay circuit has an input signal connected to an input, and one input has An exclusive OR circuit to which an input signal is connected and a delay time control signal input to the other input; a capacitor coupling an output of the buffer circuit and an output of the exclusive OR circuit; A variable delay circuit configured to extract an output signal from an output of the circuit is provided.

Here, the variable delay circuit according to the present invention can be used by connecting a plurality of the variable delay circuits in cascade. Further, in the variable delay circuit according to the present invention, the buffer circuit and the exclusive OR circuit are used as both-phase outputs, and the positive-phase outputs and the negative-phase outputs are connected via capacitors, respectively, so that the variable delay circuits of both phases are connected. It can be a circuit. Further, in the variable delay circuit according to the present invention, the exclusive OR circuit may be an analog circuit.

The main feature of the variable delay circuit according to the present invention is that the variable delay circuit includes an exclusive OR circuit that controls the delay time of the circuit by an input delay time control signal, together with a buffer circuit that itself functions as a logic gate. Features.

That is, the variable delay circuit according to the present invention includes an exclusive OR circuit in which an input signal to the buffer circuit is connected to one input and a delay time control signal is connected to the other input. The output of the exclusive OR circuit is connected to the output of the buffer circuit via a capacitor.

In the variable delay circuit configured as described above, for example, when the delay time control signal is at a low level, the exclusive OR circuit has the same phase as the output of the buffer circuit. Therefore, the voltage across the capacitor always fluctuates in phase and does not affect the output of the buffer circuit.

On the other hand, when the delay time control signal is at a high level, the exclusive OR circuit operates as an inverter and becomes a complementary signal of the output of the buffer circuit. Therefore, the voltage across the capacitor always fluctuates in the opposite phase, acts as a capacitance with respect to the output of the buffer circuit, and the output delay time increases.

With such an operation, in the variable delay circuit according to the present invention, the delay time of the output signal can be changed by selecting the low level or the high level of the delay time control signal. Here, in the operation of the variable delay circuit according to the present invention as described above, the logical amplitude of the output signal is
It should be noted that it does not change irrespective of the delay time, and therefore no increase in jitter or the like occurs.

In the variable delay circuit according to the present invention, if the exclusive OR circuit is operated in an analog manner, the delay time control signal continuously changes from a voltage corresponding to a low level to a voltage corresponding to a high level. Can be done. That is, the delay time in this circuit can be continuously changed from the minimum to the maximum. Further, by using a plurality of variable delay circuits having variable delay amounts as described above connected in cascade, the variable range of the delay amount can be increased.

Hereinafter, the present invention will be described more specifically with reference to examples. However, the following disclosure is merely an example of the present invention, and does not limit the technical scope of the present invention.

Embodiment 1 FIG. 1 is a diagram showing a basic configuration of a variable delay circuit according to the present invention.

As shown in FIG. 1, the variable delay circuit mainly includes a buffer circuit 1 and an exclusive OR circuit 2.
An input signal is commonly connected to an input of the buffer circuit 1 and one input of the exclusive OR circuit 2, and a delay time control signal to be described later is coupled to the other input of the exclusive OR circuit 2. Have been. On the other hand, the output of the exclusive OR circuit 2 is connected to the output of the buffer circuit 1 via the capacitor 3.

The variable delay circuit configured as described above operates as follows.

Now, assuming that the delay time control signal input to the exclusive OR circuit 2 is at a low level, the output of the exclusive OR circuit 2 is the same as the output of the buffer circuit 1. Therefore,
The voltage across the capacitor 3 always fluctuates in phase, and the input signal to the buffer circuit 1 is output as it is.

On the other hand, if the delay time control signal input to the exclusive OR circuit 2 is at a high level, the exclusive OR circuit 2
Is a signal having a phase opposite to that of the input signal. That is, here, the exclusive OR circuit 2 operates as an inverter.
Therefore, since the voltage across the capacitor 3 always fluctuates in the opposite phase, the capacitor 3 acts as a capacitance with respect to the output of the buffer circuit 1. That is, the output signal of the buffer circuit 1 is output after being delayed according to the charging time of the capacitor 3.

In the operation of the variable delay circuit shown in FIG. 1 as described above, the delay time of the output signal is determined solely by the charging time of the capacitor 3. Therefore, even if the delay time changes, the signal output from the buffer circuit 1 does not change. The amplitude does not change.

For the sake of convenience, in the above description, the exclusive OR circuit 2 has been described as operating in a binary manner. However, as shown in FIG. 2, the exclusive OR circuit 2 operates in an analog manner. By doing so, the delay time can be continuously changed from the delay time corresponding to the low level of the delay time control signal to the delay time corresponding to the high level.

Further, as shown in FIG. 3, by connecting the variable delay circuits shown in FIG. 1 in a plurality of columns, the variable range of the delay time can be further expanded.

Embodiment 2 FIG. 4 is a diagram showing a basic configuration in a case where a variable delay circuit according to the present invention is configured by a two-phase output circuit. The configuration and operation of this circuit are substantially the same as those in the example shown in FIG. 1, and therefore detailed description is omitted. However, in this circuit, a buffer circuit 1a and an exclusive OR circuit 2a each have a complementary pair. And the respective outputs are connected via capacitors 3a and 3b.

FIG. 5 shows the variable delay circuit shown in FIG.
FIG. 4 is a circuit diagram showing a specific configuration example when formed by a urce couple FET logic configuration.

As shown in the figure, this variable delay circuit mainly includes a buffer circuit 1a for each phase, an exclusive OR circuit 2a, capacitors 3a and 3b, and an output circuit 4.

Buffer circuit 1a is composed of FETs Q ₁ and Q ₂ of a pair connected in parallel to the source in common between the power supply and ground. Input signal is connected to the gate of the FETs Q _1, a predetermined reference voltage Ref _.1 to the gate of the FETs Q ₂ is applied. Therefore, when the input signal is high level, FETQ
₁ becomes conductive, the drain of the FETs Q ₁ becomes the high level. On the other hand, when the input signal is low, the FET Q ₂ conducts,
The drain of ETQ ₂ goes high.

On the other hand, the exclusive OR circuit 2a is composed of three pairs of FETs Q ₃ -Q ₄ , Q ₅ -Q ₆ and Q ₇ -Q ₈ whose sources are connected in common, and the input signal is the FET Q ₃ and to the gate of Q _6,
Delay time control signals are connected to the gates of the FETs Q _7. The predetermined reference voltage Ref _.1 to the gates of the FETs Q ₄ and Q ₅ are given the reference voltage Ref _.2 to the gate of the FETs Q ₈
Is applied. More in exclusive OR circuit 2a having such a constitution, the drain signal corresponding to the exclusive OR of FETs Q ₅ the input signal and the delay time control signals, also complementary to the drain of the FETs Q ₅ signal is generated in the drain of FETQ _6.

Drain of FETs Q ₅ is connected to the drain of the FETs Q ₁ via the capacitor 3a, the drain of the FETs Q ₆ is capacitor 3
connected to the FETQ ₂ drain via
It is connected to an external output via an output circuit 4 including a source follower constituted by TQ ₉ and Q ₁₀ and a level shift circuit constituted by diode groups D ₁ and D ₂ .

Incidentally, FETs Q ₁₁ to Q, which is inserted between the power source and the circuit
₁₄ constitutes a current source of each circuit.

The operation of this circuit is substantially the same as that already set in the first embodiment, and a description thereof will be omitted.

The circuit according to the present invention described above is a completely novel variable delay circuit whose delay time can be continuously or discretely changed by a delay time control signal.

Further, in the variable delay circuit according to the present invention, since the logic amplitude does not change regardless of the delay time, the variable delay circuit is not easily affected by the nozzle due to the change in the delay time, thereby preventing an increase in jitter.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of a variable delay circuit according to the present invention. FIG. 2 is a diagram showing a delay time control signal and a delay time which can be applied to the variable delay circuit shown in FIG. FIG. 3 is a diagram showing one embodiment of the variable delay circuit according to the present invention, and FIG. 4 is a graph showing another embodiment of the variable delay circuit according to the present invention. FIG. 5 is a circuit diagram showing a specific configuration example of the variable delay circuit shown in FIG. [Main reference numbers and reference numerals] 1, 1a ...... buffer circuit, 2, 2a ...... exclusive OR circuit, 3, 3a, 3b ...... condenser, 4 ...... output circuit, Q ₁ to Q _8, Q _{11 ~Q 14 ...... FET, D 1} , D 2 ...... diode

Claims (1)

(57) [Claims] 1. A variable delay circuit for holding an input signal for a certain delay time and outputting the same, comprising: a buffer circuit having an input connected to an input signal; one input connected to the input signal; An exclusive-OR circuit to which a delay time control signal is input, and a capacitor that couples the output of the buffer circuit and the output of the exclusive-OR circuit, and extracts an output signal from the output of the buffer circuit. A variable delay circuit having a configuration as described above.