JP3008697B2 - Logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a logic circuit, and more particularly to a logic circuit in an n-type JFET integrated circuit.

[0002]

2. Description of the Related Art A conventional n-type JFET uses SCFL (Sou).
FIG. 2 shows a logic circuit of the R.sub.Coupled FET Logic.

Conventional SCFL logic circuits of n-type JFETs include n-type JFETs 1 to 7, diodes 10 to 13,
It consists of resistors 14 and 15.

In order to generate positive and negative phase signals of an input voltage with respect to a reference voltage using a differential pair including n-type JETs 1 to 3 and resistors 14 and 15, and obtain an interface with an input level of another logic circuit, n-type JFETs 4-7 and diode 1
Level shift is performed by a level shift circuit composed of 0 to 13 and output.

When there is a load capacitance and the output is at a high level, the upper n-type JFETs 4 and 5 of the level shift circuit are provided.
And when the output is at the low level, the load capacitance is discharged by the lower n-type JFETs 6 and 7 of the level shift circuit.

[0006]

The conventional n-type J described above.
The logic circuit of the FET and SCFL converts the current of the output level shift circuit to the n-type JFET and its bias voltage (Vbi).
As), the constant current is used irrespective of the output High and Low levels. Therefore, the constant current must be increased by the output load current, and there is a problem that the current increases. Also, unless the constant current is increased,
There was a problem that the speed was slow.

An object of the present invention is to provide a logic circuit whose operating speed is increased without increasing current consumption.

[0008]

In order to achieve the above object, a logic circuit according to the present invention is a logic circuit having a differential pair and a level shift circuit, wherein the differential pair has an input.
Based on the comparison result between the voltage and the reference voltage,
Against and outputs a positive-phase signal and the phase signal, before
The level shift circuit receives the positive-phase signal and the negative-phase signal.
Output signals, level-shifted individually and output terminals individually
And a power supply line for supplying a power supply voltage.
A first transistor connected in parallel with the output terminal;
A first transistor having a first transistor and a second transistor.
Is on or off depending on the logic level of the input signal
And the second transistor outputs an output signal to the output terminal.
Only when the signal changes to the logic level corresponding to the power supply voltage
It is controlled to turn on . In addition, the present invention relates to
Logic circuit has a differential pair and a level shift circuit
A logic circuit, wherein the differential pair includes an input voltage and a reference voltage.
A positive-phase signal for the input voltage based on the comparison result
And and outputs a phase signal, said level shift
The circuit receives the positive-phase signal and the negative-phase signal as input signals, and
Output each to the output terminal after level shift
Wherein the level shift circuit shifts the in-phase signal.
First level to be bell-shifted and output to the first output terminal
A shift circuit and a second level shifter for level shifting the inverted phase signal.
A second level shift circuit that outputs to the output terminal of
Each of the first and second level shift circuits is
Parallel between a power supply line for supplying the power supply voltage and the output terminal.
Column-connected first and second transistors
And the first transistor has a logic level of the input signal.
On or off according to the first transistor
Between one electrode and the gate electrode of the second transistor;
The first transistor is turned on from on due to capacitive coupling.
The second transistor is turned on at the time of transition to
It is.

Further, the differential pair is provided for two input signals.
And it has a function of OR (NOR) gates Te.

[0010]

The operation speed is increased by increasing the charging current to the load capacitance only when the level shift circuit changes to the high level.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

(Embodiment 1) FIG. 1 is a circuit diagram showing Embodiment 1 of the present invention.

In FIG. 1, the present invention relates to an n-type JFET 1 having a gate connected to an input terminal, an n-type JFET 2 having a gate connected to a reference voltage and a source connected to the source of the n-type JFET 1, and a drain connected to an n-type JFET 1. An n-type JFET 3 connected to the sources of the type JFETs 1 and 2, the gates are connected to the bias voltage, and the source is grounded;
14 connected to the drain of the other end and connected to the power supply
And a resistor 15 having one end connected to the drain of the n-type JFET 2 and the other end connected to a power supply. Ie figure
And a parallel-connected JFET 1 forming a differential pair shown in FIG.
JFET2 has its drain connected through resistors 14 and 15
Each is connected to the power supply side and its source is JFET3
Connected to the ground side via
Input signal is input to the gate, and reference to the gate of JFET2
Voltage is input.

Further, an n-type JFET having a gate connected to the drain of the n-type JFET 1 and a drain connected to the power supply.
4, an n-type JFET 5 having a gate connected to the drain of the n-type JFET 2 and a drain connected to the power supply, and a diode 10 having an anode connected to the source of the n-type JFET 4.
And a diode 11 having an anode connected to the cathode of the diode 10 and a cathode connected to the negative-phase output terminal Q (negative phase), and a drain connected to the negative-phase output terminal Q (negative phase) and the gate connected to the bias voltage. N-type JFET 6 whose source is grounded, diode 12 whose anode is connected to the source of n-type JFET 5, and whose anode is connected to the cathode of diode 12 and whose cathode is the positive-phase output terminal Q
(Positive phase), an n-type JFET 7 whose drain is connected to the positive phase output terminal Q (positive phase), whose gate is connected to the bias voltage and whose source is grounded, and whose drain is connected to the power supply and the source is Is an n-type JFET 8 connected to the anode of the diode 11, an n-type JFET 9 whose drain is connected to the power supply and whose source is connected to the anode of the diode 13, and one end is connected to the source of the n-type JFET 4 and the other end is n-type. A capacitor 18 connected to the gate of JFET 8, a capacitor 19 having one end connected to the source of n-type JFET 5 and the other end connected to the gate of n-type JFET 9, and one end connected to the gate of n-type JFET 8 and the other end A resistor 16 connected to the negative phase output terminal Q (negative phase) and one end of an n-type J
A resistor 17 is connected to the gate of the FET 9 and the other end is connected to the positive-phase output terminal Q (positive phase). That is, in FIG.
The level shift circuit shown in FIG.
The level shift of each signal output from the drain
Output to the positive-phase output terminal Q and the negative-phase output terminal Q respectively.
A first level shift circuit and a second level shift circuit
The first level shift circuit and the second level shift circuit.
Is a JFET that performs a level shift.
8 and 9 have the same configuration. The first and second
JFETs 8 and 9 included in each level shift circuit of FIG.
Capacitance coupling between gate and source by capacitors 18 and 19
Between the gate and the positive-phase output terminal Q and the negative-phase output terminal Q
Are connected via resistors 16 and 17, respectively,
1 and the change in the output from JFET 2 and the resistance 16,1
7 and the time constant of capacitors 18 and 19,
The pressure changes.

Since the differential pair of the input section is the same as that of the conventional example, the level shift circuits (n-type JFETs 4 to 4) which operate differently.
9, diodes 10 to 13, resistors 16 and 17, capacitance 1
8, 19) will be described. (See Fig. 3)

In the steady state, n-type JFETs 8 and 9
Is in the OFF state (Vgs <threshold voltage) and is in the same state as the conventional example.

When the output changes to a high level, the voltage is increased due to the voltage-capacitance coupling between the gates and sources of the n-type JFETs 8 and 9 and turned on to supply a current for charging the load capacitance. After the change, the change of the output and the resistance 16,1
7 and the time constants of the capacitors 18, 19, the n-type JFET 8,
9, the gate-source voltage becomes small, and the steady state O
The state becomes the FF state.

When the output changes to a low level, the n-type J
The gate-source voltage of the FETs 8 and 9 becomes small,
It does not change in the FF state. The gate-source voltage is
It returns to the original state after a certain time as in the case where the level has changed to the High level.

(Embodiment 2) FIG. 4 is a circuit diagram showing Embodiment 2 of the present invention.

In this embodiment, as shown in FIG.
T1 to 9, 20; diodes 10 to 13;
OR (NOR) of 2 to 17 and capacity 18, 19
And a gate . 2-input OR (NOR) gate
Indicates that n-type JFET1 and n-type JFET20 are connected in parallel.
N-type JFET 1 and n-type JFET
The input terminals were connected to the gates with 20, respectively.
It has a configuration. Other configurations are the same as the first embodiment, and have the same effects as the first embodiment.

[0021]

As described above, according to the present invention, the current consumption is increased more than the conventional level shift of the constant current by increasing the charge current to the load capacitance only when the level shift circuit changes to the high level. There is an effect that the operation speed can be increased without performing.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional example.

FIG. 3 is an operation explanatory diagram.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

[Explanation of symbols]

 1-9,20 n-type JFET 10-13 diode 14-17 resistor 18,19 capacitance

Claims (3)

(57) [Claims] 1. A logic circuit having a differential pair and a level shift circuit, wherein the differential pair is based on a comparison result between an input voltage and a reference voltage.
And outputs a positive-phase signal and a negative-phase signal with respect to the input voltage.
The level shift circuit converts the positive-phase signal and the negative-phase signal
Input signals, level-shifted individually and output individually
Power supply line that outputs power to the
A first transistor connected in parallel between
A first transistor and a second transistor.
The transistor is turned on or off according to the logic level of the input signal
And the second transistor outputs an output signal to the output terminal.
Only when the signal changes to the logic level corresponding to the power supply voltage
A logic circuit controlled to be turned on . 2. It has a differential pair and a level shift circuit.
A logic circuit, The differential pair is based on a comparison result between an input voltage and a reference voltage.
And outputs a positive-phase signal and a negative-phase signal with respect to the input voltage.
To do The level shift circuit converts the in-phase signal and the in-phase signal
Input signals, level-shifted individually and output individually
Output to the child, The level shift circuit shifts the level of the positive-phase signal.
First level shift circuit for outputting to a first output terminal
And a second output terminal for level-shifting the inverted phase signal.
And a second level shift circuit that outputs the Each of the first and second level shift circuits is
Parallel between a power supply line for supplying the power supply voltage and the output terminal.
Column-connected first and second transistors
And the first transistor has a logic level of the input signal.
On or off according to the first transistor
Between one electrode and the gate electrode of the second transistor;
The first transistor is turned on from on due to capacitive coupling.
The second transistor is turned on during a transition to
A logic circuit characterized by the following. Wherein the differential pair, the logic circuit according to claim 1 or 2, characterized in that it has the function of OR (NOR) gates for two input signals.