JPH0491511A - Variable delay circuit - Google Patents

Abstract

PURPOSE:To allow a variable delay circuit to change delay time while the circuit secures a sufficient logical amplitude as a variable delay circuit by providing a buffer circuit which functions as a logical gate and exclusive OR circuit which controls the delay time. CONSTITUTION:When a delay time control signal inputted to an exclusive OR circuit 2 is low in level, the output of the circuit 2 becomes the same as that of a buffer circuit l and the voltage across both ends of capacitor 3 always fluctuates in the same phase, with input signals to the circuit l being outputted as they are. On the other hand, when the delay time control signal inputted to the circuit 2 is high in level, the output of the circuit 2 becomes opposite in phase to input signals. Therefore, the voltage across both ends of the capacitor 3 always fluctuates in the opposite phase and acts on the output of the buffer circuit 1 as a capacitance. In other words, the output signal of the circuit l is outputted after it is delayed in accordance with the charging time of the capacitor 3.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to variable delay circuits. More specifically, the present invention relates to a variable delay circuit, which is one of semiconductor integrated circuits, in which the propagation delay time thereof can be changed.Conventional technology Generally speaking, in a conventional variable delay circuit, it is not possible to change the propagation delay time. There are no specific means to do so. Therefore, when it is necessary to change the delay time of a logic gate, the delay time is increased by reducing the power consumption of the variable delay circuit.

Problems to be Solved by the Invention However, according to the conventional method of increasing the delay time by reducing the power consumption of the circuit, the logic amplitude inside the variable delay circuit also decreases as the power consumption decreases, which affects noise. There was a problem that jitter increased.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a completely new variable delay circuit that can vary delay time while ensuring sufficient logic amplitude as a variable delay circuit.

Means for solving the problem, that is, according to the present invention, is a variable delay circuit that outputs an input signal after holding it for a certain delay time, the buffer circuit having the input signal connected to its input, and the buffer circuit having the input signal connected to one input. comprising an exclusive OR circuit connected to an input signal and having a delay time control signal input to the other input, and a capacitor coupling the 8 outputs of the buffer circuit and the output of the exclusive OR circuit,
A variable delay circuit is provided, characterized in that it is configured to extract an output signal from the output of the amplifier circuit.

Here, the variable delay circuit according to the present invention can be used by connecting a plurality of variable delay circuits in series. Further, in the variable delay circuit according to the present invention, the buffer circuit and the exclusive OR circuit have two-phase outputs, and the positive-phase outputs and the negative-phase outputs are connected via capacitors, respectively, to provide a variable delay for both phases. It can be a circuit. Furthermore,
In the variable delay circuit according to the present invention, the exclusive OR circuit may be an analog circuit.

The main feature of the variable delay circuit according to the present invention is that it includes a buffer circuit that itself functions as a logic gate, and an exclusive OR circuit that controls the delay time of the circuit using an input delay time control signal. It is a feature.

That is, the variable delay circuit according to the present invention includes an exclusive OR circuit having one input connected to the input signal for the buffer circuit and the other input connected to the delay time control signal. The output of this exclusive OR circuit is connected to the output of the buffer circuit via a capacitor.

In the variable delay circuit configured as described above, for example, when the delay time control signal is at a low level, the exclusive OR circuit is in phase with the output of the buffer circuit. Therefore, the voltage across the capacitor always fluctuates in phase and does not affect the output of the buffer circuit.

On the other hand, when the delay time control signal is at a high level, the exclusive OR circuit operates as an inverter and becomes a complementary signal to the output of the buffer circuit. Therefore, the voltage across the capacitor always fluctuates in opposite phases, acts as a capacitor for the output of the buffer circuit, and the output delay time increases.

With such an operation, the variable delay circuit according to the present invention can change the delay time of the output signal by selecting whether the delay time control signal is at a low level or a high level. Here, in the operation of the variable delay circuit according to the present invention as described above, the logical amplitude of the output signal is
It should be noted that it does not change regardless of the delay time, and therefore no increase in jitter or the like occurs.

In addition, in the variable delay circuit according to the present invention, if the exclusive OR circuit is operated in an analog manner, the delay time control signal can be continuously changed from a voltage equivalent to a low level to a voltage equivalent to a high level. can be done. That is, the delay time in this circuit can be changed continuously from the minimum to the maximum. In addition, by connecting multiple variable delay circuits with variable delay amounts in cascade as described above,
The variable range of the delay amount can be increased.

EXAMPLES Hereinafter, the present invention will be described in more detail with reference to Examples, but the following disclosure is merely an example of the present invention and does not limit the technical scope of the present invention in any way.

Embodiment 1 FIG. 1 is a diagram showing the basic configuration of a variable delay circuit according to the present invention.

As shown in the figure, this variable delay circuit is mainly composed of a buffer circuit 1 and an exclusive OR circuit 2.

An input signal is commonly connected to the input of the buffer circuit 1 and one input of the exclusive OR circuit 2, and a delay time control signal, which will be described later, is connected to the other input of the exclusive OR circuit 2. has been done. On the other hand, the output of the exclusive OR circuit 2 is connected to the output of the buffer circuit 1 via a capacitor 3.

The variable delay circuit configured as described above operates as follows.

Now, assuming that the delay time control signal input to the exclusive OR circuit 2 is at a low level, the output of the exclusive OR circuit 2 will be the same as the output of the buffer circuit 1. Therefore, the voltage across the capacitor 3 always fluctuates in the same phase, and the input signal to the buffer circuit 1 is output as is.

On the other hand, if the delay time control signal input to the exclusive OR circuit 2 is at a high level, the output of the exclusive OR circuit 2 will be a signal with the opposite phase to the input signal. That is, here, the exclusive OR circuit 2 operates as an inverter. Therefore, since the voltage across the capacitor 3 always fluctuates in opposite phases, the capacitor 3 acts as a capacitor for the eight elements of the buffer circuit 1. That is, the output signal of the buffer circuit 1 is output with a delay depending on the charging time of the capacitor 3.

In the operation of the variable delay circuit shown in FIG. 1 as described above, the delay time of the output signal is determined exclusively by the charging time of the capacitor 3, so even if the delay time changes, the signal output from the buffer circuit 1 The amplitude does not change.

For convenience of explanation, in the above description, the exclusive OR circuit 2 was explained as operating in binary mode, but as shown in FIG. By operating the delay time, the delay time can be continuously changed from a delay time corresponding to a low level of the delay time control signal to a delay time corresponding to a high level.

Furthermore, as shown in FIG. 3, by connecting a plurality of variable delay circuits shown in FIG. 1 in series, the variable range of the delay time can be further expanded.

Embodiment 2 FIG. 4 is a diagram showing a basic configuration when a variable delay circuit according to the present invention is configured with a dual-phase output circuit. The configuration and operation of this circuit are substantially the same as the example shown in FIG. 1, so a detailed explanation will be omitted. The outputs are connected via capacitors 3a and 3b.

FIG. 5 shows the variable delay circuit shown in FIG.
(Source Couple FET Log
ic) is a circuit diagram showing a specific example of the configuration when formed according to the configuration.

As shown in the figure, this variable delay circuit is mainly composed of a dual-phase huffing circuit la, an exclusive OR circuit 2a, capacitors 3a and 3b, and an output circuit 4.
Ru.

The buffer circuit 1a is composed of a pair of FETQ and Q2 whose sources are commonly connected in parallel between a power supply and ground. The input signal is connected to the gate of FET Q + , and a predetermined reference voltage Ref, , is applied to the gate of FET Q. Therefore, when the input signal is at high level, FETQ becomes conductive and FET
The drain of FET Q is at the /"t level. On the other hand, when the input signal is low level, FET Q2 is conductive and the FET
The drain of Q2 becomes high level.

On the other hand, the exclusive OR circuit 2a includes three pairs of FETs Q3-Q, , Qs-Q6, Q whose sources are connected in common.
, -Q8, the input signal is connected to the gates of FETQ3 and Q6, and the delay time control signal is connected to the gate of FETQ. Also, FETQ,
And a predetermined reference voltage Ref, l is applied to the gate of Q5.
However, a predetermined reference voltage Ref,
2 is applied. In the exclusive OR circuit 2a configured as described above, a signal corresponding to the exclusive OR of the input signal and the delay time control signal is connected to the drain of FETQS and complementary to the drain of FETQS. A signal is generated at the drain of FETQ6.

The drain of FETQS is connected to the FET via capacitor 3a.
The drain of FETQ6 is connected to the drain of FETQ through a capacitor 3b, and the source follower and diode group, each formed by FETQ9, Q, and o, are connected to the drain of FETQ, D,
Output circuit 4 consisting of a levelnft circuit configured by
Connected to external output via.

Furthermore, FETQ is inserted between the power supply and each circuit.

~Q1. constitutes a current source for each circuit.

The operation of this circuit is substantially the same as that already explained in the first embodiment, so the explanation will be omitted.

The circuit according to the present invention described in detail is a completely new variable delay circuit whose delay time can be changed continuously or discretely by a delay time control signal.

Furthermore, since the variable delay circuit according to the present invention does not change the logic amplitude regardless of the delay time, it is not susceptible to noise due to changes in the delay time, and an increase in jitter can be prevented. .

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of a variable delay circuit according to the present invention, and FIG. 2 shows delay time control signals and delay times that can be applied to the variable delay circuit shown in FIG. FIG. 3 is a diagram showing one embodiment of the variable delay circuit according to the present invention, and FIG. 4 is a diagram showing another embodiment of the variable delay circuit according to the present invention. FIG. 5 is a circuit diagram showing a specific configuration example of the variable delay circuit shown in FIG. 4. 5 Main reference numbers and reference symbols] 1.1a... Buffer circuit, 2.2a... Exclusive OR circuit, 3.3a, 3b... Capacitor, 4... Output circuit, Ql ~ Q , ,Q,, ~Q1. ...FET. D+, D2...diode

Claims (1)

[Claims] A variable delay circuit that outputs an input signal after holding it for a certain delay time, comprising: a buffer circuit whose input is connected to the input signal; An exclusive OR circuit to which a delay time control signal is input, and a capacitor that couples the output of the buffer circuit and the output of the exclusive OR circuit, and extracts an output signal from the output of the buffer circuit. A variable delay circuit configured to: