JPH07273619A - Buffer circuit - Google Patents

Abstract

PURPOSE:To realize a buffer circuit in which production of a skew is prevented, a timing margin is reduced and a high processing speed is obtained. CONSTITUTION:A push-pull circuit 20 providing an output signal in phase to an output signal of a CMOS inverter 1 is provided in parallel with a CMOS inverter 3 between an output of a CMOS inverter 1 being a component of an input gate stage and an input of a CMOS inverter 2 being a positive phase output gate stage as a signal path, and number of the gate stages to set equal to both the positive phase output and the negative phase output. As a result, a delay time difference between the positive phase output and the negative phase output is eliminated, resulting that production of a skew is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer circuit applied to a decoder circuit or the like.

[0002]

2. Description of the Related Art FIG. 8 is a circuit diagram showing a configuration example of a conventional buffer circuit. This buffer circuit has a power supply voltage V _DD
Of the CMOS inverters 1, 2, 3 and 4 as a gate circuit, which are connected in series between the supply line and the ground line and have gates connected to each other, and which are PMOS transistors PT and NMOS transistors NT.

A CMOS inverter 2, a CMOS inverter 3 and a CMOS inverter 4 are connected in parallel to the CMOS inverter 1. Then, the input signal A is input to the CMOS inverter 1, and the in-phase output A is obtained from the output of the CMOS inverter 2. Also, CM
The node N1, which is the midpoint of connection between the output of the OS inverter 1 and the input of the CMOS inverter 2, is the CMOS inverter 3
Is connected to the input of the Is obtained from the output of the CMOS inverter 4.

As described above, in the buffer circuit of FIG. 8, the in-phase output A is obtained by passing the input signal A through the two-stage gate circuit of the CMOS inverter 1 and the CMOS inverter 2, and the CMOS inverter 1, the CMOS inverter 3 and By passing through the three-stage gate circuit of the CMOS inverter 4, the reverse phase output A Is obtained.

[0005]

As described above, in the conventional buffer circuit, the number of gate stages through which the signal passes is one more in the reverse phase output than in the in-phase output. Delay time becomes large. As a result, problems such as skew occur. Hereinafter, this problem will be described more specifically with reference to FIGS. 9 and 10 by taking the case where the circuit of FIG. 8 is applied to a decoder circuit as an example.

FIG. 9 shows a configuration example of a decoder circuit corresponding to two inputs A0 and A1 by arranging the buffer circuits of FIG. 8 in two stages in parallel. In this circuit, the output of the CMOS inverter 4-0 in the input stage of the signal A0 located on the lower side in the figure and the C of the input stage of the signal A1 located in the upper side in the figure
The output of the MOS inverter 4-1 is a 2-input NAND gate 5
Connected to each input. Further, the output of the CMOS inverter 2-0 at the input stage of the signal A0 and the signal A1
The output of the CMOS inverter 4-1 in the input stage of the input signal is connected to the input of the 2-input NAND gate 6, and the output of the CMOS inverter 4-0 in the input stage of the signal A0 and the signal A1.
The output of the CMOS inverter 2-1 of the input stage is connected to the input of the 2-input NAND gate 7, and the output of the CMOS inverter 2-0 of the input stage of the signal A0 and the signal A1
The outputs of the CMOS inverters 2-1 in the input stage are connected to the inputs of the 2-input NAND gate 8, respectively. The outputs of the NAND gates 5-8 are inverters 9-12.
, And decoder outputs W0 to W3 are obtained from the inverters 9 to 12, respectively.

In such a structure, for example, FIG.
As shown in, when the input signals A0 and A1 at the low level simultaneously transit to the high level, the decoder output W0 changes from the high level to the low level, and the decoder output W3 changes from the low level to the high level. However, since the number of gate stages of the signal path for obtaining the decoder output W0 is 5 and the number of gate stages of the signal path for obtaining the decoder output W3 is 4, the decoder output is W3.
Changes the fastest and W0 changes the slowest. That is,
There will be skew.

In fact, in this case all NAND gates 5-8
Of the decoder output W1 and W2, a glitch corresponding to one stage of gate delay occurs, and all the decoder outputs W0 to W3 become high level. Therefore, the decoder output is not fixed during the period from the decoder output W3 being fixed to the decoder output W0 being fixed. As described above, in the decoder circuit of FIG. 9, the timings at which the outputs W0 to W3 become active or inactive vary, so it is necessary to take a timing margin accordingly, for example, the hold time of the address input must be made larger. It has to be a hindrance to speeding up.

The present invention has been made in view of such circumstances, and an object thereof is to provide a buffer circuit capable of preventing the occurrence of skew, reducing the timing margin, and increasing the speed. Especially.

[0010]

To achieve the above object, a buffer circuit of the present invention includes a first gate circuit which receives an input signal and outputs a signal having a phase opposite to that of the input signal,
The output signal of the first gate circuit is input, a signal having a phase opposite to that of the input signal is obtained, and the second gate circuit that outputs the same phase and the output signal of the first gate circuit are input and input. A third gate circuit that outputs a signal that is in anti-phase with the input signal, and an output signal of the third gate circuit that is input, obtain a signal that is in anti-phase with the input signal, and output a signal that is in anti-phase. The gate circuit and the signal output from the first gate circuit to the second gate circuit are delayed by at least a time corresponding to the signal transit time of the third gate circuit, and then delayed by the second gate circuit. And a time adjustment circuit for inputting.

The time adjustment circuit of the buffer circuit of the present invention is composed of a buffer that outputs a signal in phase with the output signal of the first gate circuit.

[0012]

According to the buffer circuit of the present invention, the input signal is input to the first gate circuit, and the signal having a phase opposite to the input signal is output from the first gate to the time adjustment circuit and the third gate circuit. . In the time adjustment circuit, the input output signal of the first gate circuit is delayed by at least the time corresponding to the signal passage time of the third gate circuit. Then, the delayed signal is input to the second gate circuit as a signal in phase with the output signal of the first gate circuit. In the second gate circuit, a signal having a reverse phase of the input signal is obtained. As a result, a signal in phase with the input signal is output from the second gate circuit. Further, in the third circuit, a signal having an opposite phase to the input output signal of the first gate circuit is obtained, and this signal is output to the fourth gate circuit. In the fourth gate circuit, a signal having a reverse phase of the input signal is obtained. As a result, a signal having a phase opposite to the input signal is output from the fourth gate circuit.

As described above, in the present buffer circuit, the signal path from the signal input terminal to the in-phase output has the three-stage gate circuits of the first gate circuit, the time adjustment circuit and the second gate circuit. In addition, in the signal path from the signal input terminal to the negative phase output, there are three stages of gate circuits of the first gate circuit, the third gate circuit, and the fourth gate circuit. As described above, in the present buffer circuit, since the number of gate stages for the in-phase output and the anti-phase output is equal to three, there is no delay time difference between the in-phase output and the anti-phase output, and the occurrence of skew is prevented. It

[0014]

First Embodiment FIG. 1 shows a first buffer circuit according to the present invention.
FIG. 9 is a circuit diagram showing the embodiment of FIG. That is, 1 to 4
Is a CMOS inverter as a gate circuit, 20 is a push-pull circuit as a time adjustment circuit, 30 is a level adjustment circuit, and V _DD is a power supply voltage.

The push-pull circuit 20 includes an NM connected in series between a supply line of the power supply voltage V _DD and a ground line.
Between the output of the CMO inverter 1 which is composed of the OS transistors NT21 and NT22 and constitutes the input gate stage, and the input of the CMOS inverter 2 which is the in-phase output gate stage, it is arranged in parallel with the CMOS inverter 3 as a signal path. Connected, CMOS inverter 1
The signal in phase with the output signal of is output.

The gate of the NMOS transistor NT21 of the push-pull circuit 20 is the PMO of the CMOS inverter 1.
S transistor PT1 and NMOS transistor NT
Node ND1 connected to the midpoint of the connection between the drains of 1
It is connected to the. This node N1 is connected to the PMOS transistors PT3 and N
The gates of the MOS transistors NT3 are connected to the connection midpoint. The gate of the NMOS transistor NT22 is connected to the input node N _IN of the input signal A. The connection midpoint between the NMOS transistors NT21 and NT22 is connected to the connection midpoint between the gates of the PMOS transistor PT2 and the NMOS transistor NT2, which are the inputs of the CMOS inverter 2.

The level adjusting circuit 30 includes a supply line of the power supply voltage V _DD , an output of the push-pull circuit 20 and a CMOS.
The CMOS inverter 2 is configured by a PMOS transistor PT31 connected between the input of the inverter 2 and a node N2 which is a connection midpoint, and holds the high-level output signal level of the push-pull circuit 20 at the voltage voltage _VDD level. To enter. The gate of the PMOS transistor PT31 of the level adjusting circuit 30 has the output of the CMOS inverter 3 and the CMOS inverter 4 arranged in the negative phase output path.
Is connected to the node N3, which is the midpoint of connection with the input. Therefore, the PMOS transistor PT31 is
When the output signal level of the MOS inverter 3 is low level (ground level), it becomes conductive and supplies the power supply voltage V _DD to the node N2 to raise the input signal level to the CMOS inverter 2 to V _DD level. At this time, input signal A
Is low level and the output signal level of the CMOS inverter 1 is high level, the NMOS transistor NT21 of the push-pull circuit 20 is in a conductive state, and the output level of the push-pull circuit 20 is high level.
The actual level is a level (V _DD −V _TH ) which is lower than the power supply voltage V _DD level by the threshold voltage V _TH of the NMOS transistor NT21.

Next, the operation of the above configuration will be described. The signal A input to the input node N _IN is input to the CMOS inverter 1 and the push-pull circuit 20.

Here, for example, when the level of the input signal A is low, the PMOS of the CMOS inverter 1 is
The transistor PT1 becomes conductive and the NMOS transistor NT1 becomes non-conductive. As a result, CMOS
The output of the inverter 1 is output to the push-pull circuit 20 and the CMOS inverter 3 at the V _DD level, that is, the high level.

In the push-pull circuit 20, the NMOS transistor NT22 is held in the non-conducting state when the low-level signal A is input, and the NMOS transistor NT22 is input when the high-level output signal of the CMOS inverter 1 is input.
21 becomes conductive. As a result, the push-pull circuit 2
The output level of 0 is in phase with the output of the CMOS inverter 1 and is a high level, but the actual level is the power supply voltage V _DD.
The signal is output at a level (V _DD -V _TH ) that is lower than the level by the threshold voltage V _TH of the NMOS transistor NT21.

Further, in the CMOS inverter 3, as the output signal of the high-level CMOS inverter 1 is input,
The PMOS transistor PT3 becomes non-conductive, and NM
The OS transistor NT3 becomes conductive. as a result,
The output of the CMOS inverter 3 is output to the level adjusting circuit 30 and the CMOS inverter 4 at the ground level, that is, the low level.

In the level adjusting circuit 30, a low level C
With the input of the output signal of the MOS inverter 3, the PMOS
The transistor PT31 becomes conductive. As a result, the power supply voltage V _DD is supplied to the node N2, and the output signal level (V _DD −V _TH ) of the push-pull circuit 20 is raised to the level V _DD and input to the CMOS inverter 2.

In the CMOS inverter 2, the PMOS transistor PT2 becomes non-conductive and the NMOS transistor NT2 becomes conductive in response to the input of a high level signal. As a result, the CMOS inverter 2 outputs a low-level signal A in phase with the input signal A. Also,
In the CMOS inverter 4, the PMOS transistor PT4 becomes conductive in accordance with the input of the output signal of the low-level CMOS inverter 3 and the NMOS transistor NT.
4 is in a non-conducting state. As a result, the CMOS inverter 4 outputs a high-level signal A having a phase opposite to that of the input signal A. Is output.

On the other hand, when the level of the input signal A is high, the PMOS transistor PT1 of the CMOS inverter 1 becomes non-conductive and the NMOS transistor N
T1 becomes conductive. As a result, the output of the CMOS inverter 1 is output to the push-pull circuit 20 and the CMOS inverter 3 at the ground level, that is, the low level.

In the push-pull circuit 20, the NMOS transistor NT22 becomes conductive with the input of the high-level signal A, and the NMOS transistor NT21 becomes non-conductive with the input of the output signal of the low-level CMOS inverter 1. As a result, the output level of the push-pull circuit 20 is in phase with the output of the CMOS inverter 1, and is output at the low level of the ground level.

Further, in the CMOS inverter 3, as the output signal of the low-level CMOS inverter 1 is input,
The PMOS transistor PT3 becomes conductive and the NMO
The S transistor NT3 is turned off. as a result,
The output of the CMOS inverter 3 is output to the level adjusting circuit 30 and the CMOS inverter 4 at the V _DD level, that is, the high level.

In the level adjusting circuit 30, a high level C
With the input of the output signal of the MOS inverter 3, the PMOS
The node N2 in which the transistor PT31 is not turned off
The power supply voltage V _DD is not supplied to the power supply.

In the CMOS inverter 2, the PMOS transistor PT2 becomes conductive and the NMOS transistor NT2 becomes nonconductive in response to the input of a low level signal. As a result, the CMOS inverter 2 outputs a high-level signal A in phase with the input signal A. Also,
In the CMOS inverter 4, the PMOS transistor PT4 becomes non-conductive with the input of the output signal of the high-level CMOS inverter 3, and the NMOS transistor N
T4 becomes conductive. As a result, the CMOS inverter 4 outputs a low-level signal A having a phase opposite to that of the input signal A. Is output.

In the buffer circuit that operates as described above,
In the signal path from the input node N _IN to the common mode output A, C
MOS inverter 1, push-pull circuit 20 and CM
There are three stages of gate circuits of the OS inverter 2. In addition, the opposite phase output A from the input node N _IN In the signal path up to, there are three-stage gate circuits of the CMOS inverter 1, the CMOS inverter 3, and the CMOS inverter 4. As described above, in the present buffer circuit, since the number of gate stages for the in-phase output and the in-phase output are both equal to three, there is no delay time difference between the in-phase output and the in-phase output, and the skew is effectively generated. To be prevented.

FIG. 2 is a diagram showing the results of simulations performed using the buffer circuits of FIGS. 1 and 8, in which the horizontal axis represents time and the vertical axis represents voltage. As can be seen from FIG. 2, the circuit of FIG. 1 according to the present embodiment has almost no skew as compared with the conventional circuit.

FIG. 3 is a diagram showing a configuration example of a decoder circuit corresponding to two inputs A0 and A1 by arranging the buffer circuits of FIG. 1 in parallel in two stages. The connection form of FIG. 9 uses a conventional circuit. Since it is similar to the circuit, its detailed description is omitted here. 4 is a timing chart showing the operation timing of the circuit of FIG. 3 and corresponds to FIG. In the decoder circuit using this buffer circuit, since the number of gates arranged in the in-phase output path and the number of gates in the anti-phase output path are the same, the in-phase output and the anti-phase output are output with the same delay. As a result, as shown in FIG. 4, all the decoder outputs are switched at the same timing, glitches do not occur in the decoder outputs W1 and W2, and there is no uncertain period as in the conventional circuit, so high-speed operation is realized. it can.

As described above, according to this embodiment,
Between the output of the CMO inverter 1 that constitutes the input gate stage and the input of the CMOS inverter 2 that is the in-phase output gate stage, a signal in phase with the output signal of the CMOS inverter 1 is provided in parallel with the CMOS inverter 3 as a signal path. Since the push-pull circuit 20 for outputting is provided, the number of gate stages for the in-phase output and the anti-phase output is equal to 3, and as a result, the delay time difference between the in-phase output and the anti-phase output can be eliminated, and the skew is generated. Can be prevented. Therefore,
The timing margin can be reduced, and the circuit speed can be increased. In addition, the push-pull circuit 20
Since the level adjusting circuit 30 for holding the high level output signal level of the power supply voltage _VDD level and inputting it to the CMOS inverter 2 is provided, the PM of the CMOS inverter 2
OS transistor PT2 and NMOS transistor N
It is possible to prevent a through current from flowing in T2.

[0033]

Second Embodiment FIG. 5 shows a second embodiment of the buffer circuit according to the present invention.
3 is a circuit diagram showing an embodiment of FIG. The present embodiment is different from the above-described first embodiment in that the push-pull circuit is composed of two PMOS transistors PT21 and PT22 instead of being composed of two NMOS transistors, and the level adjusting circuit is accordingly composed of the power supply voltage V _DD. Supply line and node N
Instead of the PMOS transistor connected between the NMO and the NMO connected between the node N2 and the ground line
It is configured by the S transistor NT31.

The gate of the PMOS transistor PT21 forming the push-pull circuit 20a is connected to the input node N _IN, and the gate of the PMOS transistor PT22 is connected to the node N1.

In such a structure, when the output signal of the push-pull circuit 20a is at the low level, it is reliably pulled down to the ground level by the NMOS transistor NT31 of the level adjusting circuit 30a and input to the CMOS inverter 2.

Also in this embodiment, it is possible to obtain the same effects as those of the first embodiment described above.

[0037]

Third Embodiment FIG. 6 shows a third embodiment of the buffer circuit according to the present invention.
3 is a circuit diagram showing an embodiment of FIG. The present embodiment is different from the above-described first embodiment in that instead of the NMOS transistor NT21 of the push-pull circuit, the NMOS transistor NT having a lower threshold voltage V _THL and set to a value near zero is provided.
23 is used.

As a result, the level of the push-pull circuit 20b at the time of high-level output (V _DD -V _THL ) becomes higher than that of the circuit of FIG. 1, so that the circuit of FIG. 1 is not suitable for low voltage operation. Can be realized.

[0039]

Fourth Embodiment FIG. 7 shows a fourth embodiment of the buffer circuit according to the present invention.
3 is a circuit diagram showing an embodiment of FIG. The present embodiment is different from the above-described first embodiment in that the gate of the PMOS transistor PT31 of the level adjusting circuit 30 is not the node N3 connected to the output of the CMOS inverter 3 but the in-phase output connected to the output of the CMOS inverter 2. It is connected to the node N _OUT .

Also in this embodiment, the same effects as those of the above-described first embodiment can be obtained.

[0041]

As described above, according to the present invention,
Since the number of gate stages for the in-phase output and the anti-phase output can be the same, it is possible to prevent the occurrence of skew and reduce the timing margin. As a result, the operating speed can be increased.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a buffer circuit according to the present invention.

FIG. 2 is a diagram showing operating waveforms of the circuits of FIGS. 1 and 8;

FIG. 3 is a circuit diagram showing a configuration example of a decoder circuit to which the circuit of FIG. 1 is applied.

FIG. 4 is a diagram showing operation waveforms of the circuit of FIG.

FIG. 5 is a circuit diagram showing a second embodiment of the buffer circuit according to the present invention.

FIG. 6 is a circuit diagram showing a third embodiment of the buffer circuit according to the present invention.

FIG. 7 is a circuit diagram showing a fourth embodiment of the buffer circuit according to the present invention.

FIG. 8 is a circuit diagram showing a configuration example of a conventional buffer circuit.

9 is a circuit diagram showing a decoder circuit to which the circuit of FIG. 8 is applied.

10 is a diagram showing operation waveforms of the circuit of FIG.

[Explanation of symbols]

 1 to 4 ... CMOS inverter 20, 20a, 20b ... Time adjusting circuit NT21 to NT23 ... NMOS transistor PT21, PT22 ... PMOS transistor 30, 30a ... Level adjusting circuit PT31 ... PMOS transistor NT31 ... NMOS transistor

Claims (2)

[Claims] 1. A buffer circuit for obtaining an in-phase output and an anti-phase output for an input signal, the first gate circuit receiving the input signal and outputting a signal in a phase opposite to the input signal, and the first gate circuit. The second gate circuit, which receives the output signal of the gate circuit, obtains a signal having a phase opposite to the input signal, and outputs the same phase, and the input signal which receives the output signal of the first gate circuit. A third gate circuit for outputting a reverse phase signal; and a fourth gate circuit for inputting an output signal of the third gate circuit to obtain a reverse phase signal to the input signal and outputting the reverse phase output. A time for delaying the signal output from the first gate circuit to the second gate circuit by at least a time corresponding to the signal passage time of the third gate circuit and inputting the signal to the second gate circuit Buffer circuit with adjusting circuit . 2. The buffer circuit according to claim 1, wherein the time adjustment circuit includes a buffer that outputs a signal in phase with the output signal of the first gate circuit.