KR20010084629A - a thin film transistor array panel for a liquid crystal display - Google Patents

Abstract

PURPOSE: A TFT(Thin Film Transistor) substrate for LCD is provided to improve an aperture ratio of an LCD by forming common electrodes and pixel electrodes having an inclination to a gate line. CONSTITUTION: A multitude of gate line(21,22,23), a multitude of common line(24,25,241,251,253,26,27,28,29), and a data repair line(281) are formed on a substrate(10). The gate lines(21,22,23) are formed on a lateral direction of the substrate(10). An upper and a lower common signal line(24,25) are formed parallel to the gate line(21). The upper and the lower common signal lines(24,25) are connected with a common signal line connection portion(26). The lower common signal line(25) is connected with a common electrode pad(253). The first to the third common electrodes(27,28,29) are connected between the common signal lines(24,25). The first to the third common electrodes(27,28,29) has an inclination of 3 to 45 degrees to the gate lines(21,22,23). A multitude of data line(61,62,63,64) is insulated with the gate lines(21,22,23) and the common lines(24,25,241,251,26,27,28,29). A TFT transistor receives the gate lines(21,22,23) and switches pixel signals from the data lines(61,62,63,64). A multitude of pixel electrode portion(651,652,653,654,655,656,657) is formed on a pixel region. An upper and a lower pixel electrode portion(651,652) are overlaid with the common signal lines(24,25). The upper and the lower electrode portions(651,652) are connected by a pixel signal line connection portion(653). The first to the fourth pixel electrodes(654,655,656,657) are formed parallel to the first and the third common electrode(27,29). The pixel electrodes(654,655,656,657) has an inclination of 10 to 50 degrees to the gate lines(21,22,23).

Description

A thin film transistor array panel for a liquid crystal display}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a wide viewing angle.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates having electrodes formed thereon and a liquid crystal layer interposed therebetween, by rearranging the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. A device for displaying an image by adjusting the amount of light transmitted.

The liquid crystal display has a disadvantage of having a narrow viewing angle. One of the problems is to form linear electrodes parallel to each other on one of the two substrates of the liquid crystal display and to form a horizontal electric field by applying a voltage to the electrodes. There is a liquid crystal display device for rearranging liquid crystal molecules arranged parallel to the plane of two substrates.

The liquid crystal driving method using the horizontal electric field is shown in US Pat. Nos. 5,598,285 and 5,745,207.

However, the liquid crystal display device disclosed in U.S. Patent No. 5,598,285 has uneven rubbing in the process of rubbing an alignment film formed on the electrode by the step between the two electrodes, ie, the common electrode and the pixel electrode, for applying a horizontal electric field. This leaked US Patent No. 5,745,207 has a problem that the aperture ratio is lowered and color inversion occurs at a specific angle.

An object of the present invention is to improve the aperture ratio of a liquid crystal display device.

Another object of the present invention is to prevent light leakage of the liquid crystal display device.

Another object of the present invention is to remove color inversion of the liquid crystal display.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 1;

3 is a layout view of a thin film transistor substrate in a first step of manufacturing according to the first embodiment of the present invention,

4 is a cross-sectional view taken along line IV-IV 'of FIG. 3,

FIG. 5 is a layout view of a thin film transistor substrate in a next step of FIG. 4;

FIG. 6 is a cross-sectional view taken along line VI-VI ′ in FIG. 5;

FIG. 7 is a layout view of a thin film transistor substrate in a next step of FIG. 6;

FIG. 8 is a cross-sectional view taken along line VII-VII ′ in FIG. 7,

FIG. 9 is a layout view of a thin film transistor substrate in a next step of FIG. 8;

FIG. 10 is a cross-sectional view taken along line VII-VII ′ in FIG. 9,

11 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

In order to solve this problem, in the present invention, the common electrode and the pixel electrode are formed to be inclined at a predetermined angle with the horizontal direction, so that the upper side and the lower side are inclined in different directions with respect to the center of the pixel area.

In the thin film transistor substrate according to the present invention, a plurality of gate lines having a horizontal direction on the transparent substrate, a common signal line parallel to the gate lines, a vertical signal line connection part and a common signal line connection part connected to the common signal line, and connected to the gate line The common wiring including the common electrode inclined at an angle of 3 degrees to 45 degrees is formed. A thin film comprising a plurality of data lines insulated from the gate line and the common line and intersecting the gate line to form a pixel region, and including a gate electrode that is part of the gate line, a source electrode connected to the data line, and a drain electrode separated from the source electrode. The transistor receives the scan signal from the gate line and switches the image signal from the data line. In addition, the pixel signal line in the horizontal direction connected to the drain electrode and overlapping the common signal line, the pixel signal line connection part connected to the pixel signal line, and the pixel signal line connection part are inclined at an angle of 3 degrees to 45 degrees with respect to the gate line. The pixel electrode is formed. Here, the common electrode and the pixel electrode on the upper side and the lower side are inclined in different directions with respect to the horizontal line passing through the center portion of the pixel region.

The substrate according to the present invention may further include an alignment layer. The rubbing direction of the alignment layer may be parallel to the gate line.

In addition, the pixel electrode and the common electrode may be parallel to each other, and the distance between the pixel electrode and the common electrode may be 5 to 20 μm.

In the present invention, the pixel electrode and the common electrode may be vertically symmetrical with respect to a line passing through the center portion of the pixel area, respectively.

When the common signal line is formed obliquely with respect to the gate line, the thin film transistor is preferably positioned at the farthest distance between the gate line and the common signal line.

On the other hand, the liquid crystal display is formed in pixel units, the magnitude of the inclination angle of the common electrode may be different between the neighboring pixels.

In the present invention, a portion connecting the common electrode and the common signal line connection part may be inclined at an angle of 10 to 50 degrees with respect to the gate line, and a portion connecting the pixel electrode and the pixel signal line connection part may be inclined at an angle of 10 to 50 degrees. .

In the present invention, the pixel electrode and the common electrode are formed to be inclined at the same angle and inclined at a predetermined angle. Therefore, the aperture ratio is improved. In addition, when the alignment layer is formed on the thin film transistor substrate and then rubbed in a direction parallel to the gate line, the common electrode and the pixel electrode are formed in both directions in the rubbing direction, so that defects such as color inversion and light leakage do not occur.

Next, a liquid crystal display and a manufacturing method thereof according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, FIG. 1 illustrates a substrate including a thin film transistor of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II 'of FIG. 1.

Gate wirings 21, 22, 23, common wirings 24, 25, 241, 251, 253, 26, 27, 28, 29, and data repair lines 281 are formed on the transparent substrate 10. The gate wires 21, 22, and 23 are connected to one end of the gate line 21 and the gate line 21 formed in the horizontal direction, and transmit a signal from the outside to the gate line 21. ) And part of the gate line 21 becomes the gate electrode 22. Upper and lower common signal lines 24 and 25 are formed under the gate line 21 and parallel to the gate line 21, and the upper and lower common signal lines 24 and 25 are connected to the common signal line connection part 26. have. The inner sides 241 and 251 of the upper and lower common signal lines 24 and 25 are formed in diagonal lines so that the portion that meets the common signal line connecting portion 26 is wider than the other portion and becomes narrower toward the right side. One end of the lower common signal line 25 is connected to a common electrode pad 253 for transmitting a signal from the outside. The first to third common electrodes 27, 28, and 29 are connected between the common signal lines 24 and 25 and are connected to the common signal line connection part 26 and formed in the horizontal direction. The upper and lower sides of the second common electrode 28 in the center between the two common signal lines 24 and 25 are respectively upper and lower common signal lines 24 and 25 toward the right from where they meet the common signal line connecting portion 26. Since the sidewalls 241 and 251 are formed side by side with the same inclination, the thickness of the second common electrode 28 is increased. Meanwhile, the first common electrode 27 between the upper common signal line 24 and the second common electrode 28 is formed to have the same slope as the inner side 241 of the upper common signal line 24. The third common electrode 29 between the two common electrodes 28 and the lower common signal line 25 has the same slope as the inner side 251 of the lower common signal line 25. The upper and lower sides of the first and third common electrodes 27 and 29 and the second common electrode 28 form an angle with an imaginary line perpendicular to the common signal line connector 26, in a range of 3 to 45 degrees. On the other hand, both ends of the common electrodes 27, 28, 29 are bent more and more inclined, which is for the smooth arrangement of the liquid crystal molecules, the angle of this portion is preferably 10 to 50 degrees. Here, the spacing between the inner portion 241 of the upper common signal line 24 and the first common electrode 27, the first common electrode 27 and the second common electrode 28 is equal, which is also the second common electrode The common wirings 24, 25, 241, 251, and 253 have the same spacing as the inner portion 251 of the 28, the third common electrode 29, the third common electrode 29, and the lower common signal line 25. , 26, 27, 28, and 29 are symmetrical with respect to the center portion of the second common electrode 28. Although only three common electrodes 27, 28, and 29 are shown between the upper common signal line 24 and the lower common signal line 25, the inclination angles of the common electrodes 27, 28, and 29, and the properties of the liquid crystal molecules may be used. It may be formed in a larger number or in a smaller number. Further, the data repair line 281 is formed in the vertical direction to the right of the first to third common electrodes 27, 28, and 29, and the common wirings 24, 25, 241, 251, 253, 26, 27, 28 , 29). The data repair line 281 can be repaired by shorting both ends of the disconnected part with the data repair line 281 using a laser when the main data line 81 on the upper part is disconnected.

The gate insulating film 30 is formed on the gate wirings 21, 22, 23, the common wirings 24, 25, 241, 251, 253, 26, 27, 28, 29, and the data repair line 281 to cover them. The semiconductor layer 40 and the ohmic contact layer patterns 51 and 52 are formed on the gate insulating layer 30 at the portion where the gate electrode 22 is positioned.

The auxiliary data line 61, 62, formed of an auxiliary data line 61, a source electrode 62 connected to the auxiliary data line 61, a drain electrode 63 spaced apart from the auxiliary data line 61, and a data pad 64. The drain electrode 63 is formed in the pixel region in which 63 and 64 are formed, and the common wirings 24, 25, 241, 251, 253, 26, 27, 28, and 29 except the common electrode pad 253 are formed. Pixel electrode portions 651, 652, 653, 654, 655, 656, and 657 are formed. The pixel electrode portions 651, 652, 653, 654, 655, 656, and 657 may include upper and lower pixel signal lines 651 and 652 completely overlapping the upper and lower common signal lines 24 and 25, and two pixel signal lines 651 and 652. A pixel signal line connection part 653 connecting the 652, and between the upper and lower pixel signal lines 651 and 652, connected to the pixel signal line connection part 653, and connected to the first or third common electrodes 27 and 29. The first to fourth pixel electrodes 654, 655, 656, and 657 are arranged side by side. The first pixel electrode 654 is formed at the center between the upper common signal line 24 and the first common electrode 26, and the second pixel electrode 655 is the first common electrode 27 and the second common electrode. In the center between the 28, the third pixel electrode 656 is in the center between the second common electrode 28 and the third common electrode 29, and the fourth pixel electrode 657 is the third common electrode ( 29 is formed at the center between the lower common signal line 25 and symmetrical with respect to the second common electrode 28. The distance between the pixel electrodes 654, 655, 656, and 657 and the common electrodes 27, 28, and 29 may be 5 to 20 μm.

Like the common electrodes 27, 28, and 29, the pixel electrodes 654, 655, 656, and 657 are inclined at an angle of 10 degrees to 50 degrees at both ends.

Here, the upper and lower common electrodes 27, 28, and 29 and the pixel electrodes 654, 655, 656, and 657 are not necessarily symmetrical with respect to the second common electrode 28.

On the other hand, the source and drain electrodes 62 and 63 and the contact layer patterns 51 and 52 face each other with respect to the gate electrode 22.

In the present invention, the upper portion of the upper common signal line 24 is horizontally formed, but in order to secure the space of the thin film transistor, the thin line transistor is formed at the furthest distance between the upper common signal line 24 and the gate line 21. do.

A protective insulating layer 70 is formed on the auxiliary data wires 61, 62, 63, and 64 and the pixel electrode parts 651, 652, 653, 654, 655, 656, and 657 to cover the gate pads 23, First to sixth contact holes 71, 72, 73, 74, 75, and 76 are formed on the common electrode pad 253, the data pad 64, and the auxiliary data line 61.

Subsequently, a main data line 81 is formed on the protective insulating layer 70 on the auxiliary data line 61 and the data repair line 281. The auxiliary data line 61 is formed through the fifth contact holes 75 and 76. And a data pad 64 through a fourth contact hole 74.

After forming an alignment layer (not shown) on the thin film transistor substrate formed as described above, rubbing is performed. When the rubbing direction is parallel to the gate line 21, the common electrodes 27, 28, and 29 and the pixel electrode 654 are rubbed. 655, 656, and 657 are formed in both directions in the rubbing direction, so that defects such as color inversion and light leakage do not occur.

In addition, in the present invention, since the common electrodes 27, 28, 29 and the pixel electrodes 654, 655, 656, 657 are formed in the horizontal direction, the distance between the electrodes can be formed constant, and the aperture ratio is improved.

A method of manufacturing a thin film transistor substrate for a liquid crystal display according to the present invention will be described with reference to FIGS. 3 to 10 and FIGS. 1 and 2.

First, as shown in FIG. 3, chromium and aluminum are deposited and patterned on the substrate 10 to a thickness of about 500 kPa and 2000 kPa, respectively, to form the gate wirings 21, 22, 23, and the common wirings 24, 25, 241, and 251. , 253, 26, 27, 28, and 29 and a data repair line 281 are formed. The gate lines 21, 22, and 23 include a gate line 21 and a gate pad 23, and part of the gate line 21 is used as the gate electrode 22. The common electrode wirings 24, 25, 241, 251, 253, 26, 27, 28, and 29 may have upper and lower common signal lines 24 and 25 parallel to the gate line 21 under the gate line 21, and may be connected to each other. The first to third common electrodes 27, 28, and 29, which are connected to the common signal line connector 26, the common signal line connector 26, and are symmetrically formed with a predetermined slope in the horizontal direction, respectively, and the lower common signal line 25. ) And a common electrode pad 253 formed at one end thereof. The data repair line 281 is formed vertically to the right of the common electrodes 27, 28, 29 between the common signal lines 24, 25.

Next, as shown in FIGS. 5 and 6, the gate wirings 21, 22, and 23, the common wirings 24, 25, 241, 251, 253, 26, 27, 28, and 29, and the data repair line 281. After depositing the gate insulating film 30 with a material such as silicon nitride on the top and successively depositing the semiconductor layer 40 and the contact layer 50, and patterning the semiconductor layer 40 and the contact on the gate electrode 22 Form layer 50. The semiconductor layer 40 is formed of a material such as amorphous silicon, and the contact layer 50 is formed of a material such as amorphous silicon that is heavily doped.

Next, as shown in FIGS. 7 and 8, chromium is sputtered at about 1000 microseconds and then patterned to form the auxiliary data wirings 61, 62, 63, and 64 and the pixel electrode portions 651, 652, 653, 654, 655, 656, and the like. 657). The auxiliary data wires 61, 62, 63, and 64 may include an auxiliary data line 61, a source electrode 62 connected to the auxiliary data line 61, a drain electrode 63 and a data pad separated from the auxiliary data line 61. 64). The pixel electrode portions 651, 652, 653, 654, 655, 656, and 657 are connected to the drain electrode 63, and the upper and lower pixel signal lines 651 and 652 overlapping the upper and lower common signal lines 24 and 25. ), First to fourth pixel electrodes formed between the pixel signal line connecting portion 653 and the upper and lower pixel signal lines 651 and 652 and parallel to the first or third common electrodes 27 and 29. 654, 655, 656, 657).

Next, as shown in FIGS. 9 and 10, the protective insulating layer 70 is deposited and etched to form contact holes 73, 74, 75, and 76 that expose the data pad 64 and the auxiliary data line 61, respectively. Thereafter, the gate insulating layer 30 is subsequently etched to form contact holes 71 and 72 exposing the gate pad 23 and the common electrode pad 253, respectively.

1 and 2, the main data line 81 is formed on the auxiliary data line 61 and the data repair line 281 to have a thickness of 1500 to 2500 Å. The main data line 81 may be formed of chromium or aluminum, but when formed of aluminum, the main data line 81 may be thicker than that of chromium.

In the present invention, when the auxiliary data lines 61, 62, 63, and 64 are formed, the data pads 64 are formed to be connected to the main data lines 81 through the contact holes 74. Similarly, when the main data line 81 is formed, the data pad 864 may be formed. At this time, the contact hole 74 may not be formed.

The liquid crystal display is formed in pixel units, which correspond to red, green, and blue color filters. In this case, the inclination angles of the common electrodes 27, 28, and 29 and the pixel electrodes 654, 655, 656, and 657 formed in the pixel region may be different from each other to adjust the response speed of each region.

In the present invention, the common electrode and the pixel electrode are formed to be vertically symmetric in the horizontal direction with a constant inclination so that the aperture ratio is improved and light leakage and color inversion do not occur.

Claims (9)

Transparent substrate, A plurality of gate lines formed in the horizontal direction on the substrate, A common signal line formed on the substrate and parallel to the gate line, a common signal line connection part in a vertical direction connected to the common signal line, and connected to the common signal line connection part and inclined at an angle of 3 degrees to 45 degrees with respect to the gate line; A common wiring comprising a common electrode, A plurality of data lines insulated from the gate line and the common line and crossing the gate line to form a pixel area; A thin film transistor including a gate electrode which is a part of the gate line, a source electrode connected to the data line, and a drain electrode separated from the source electrode, and receiving a scan signal from the gate line to switch an image signal from the data line; A pixel signal line connected to the drain electrode and overlapping with the common signal line and formed in a horizontal direction, a pixel signal line connection part connected to the pixel signal line, and a pixel signal line connection part, and being connected to the gate line by 3 degrees to 45 degrees; Pixel electrode tilted at an angle of degrees Including; A thin film transistor substrate for liquid crystal display devices, wherein the common electrode and the pixel electrode on the upper side and the lower side are inclined in different directions with respect to a horizontal line passing through the center portion of the pixel area. In claim 1, The substrate further includes an alignment layer, and the rubbing direction of the alignment layer is a direction parallel to the gate line. In claim 1, And the common electrode and the pixel electrode are parallel to each other. In claim 1, The pixel electrode and the common electrode are vertically symmetrical with respect to a line passing through a central portion of the pixel area, respectively. In claim 1, The distance between the pixel electrode and the common electrode is 5 to 20 ㎛ thin film transistor substrate for a liquid crystal display device. In claim 1, The thin film transistor substrate of claim 1, wherein the thin film transistor is positioned at a distance between the gate line and the common signal line when the common signal line is diagonally formed with respect to the gate line. In claim 1, The liquid crystal display device is a pixel unit, and the thin film transistor substrate for a liquid crystal display device, wherein the angle of the inclination of the common electrode is different between the neighboring pixels. In claim 1, And a portion which connects the common electrode and the common signal line connection part and is inclined at an angle of 10 to 50 degrees with respect to the gate line. In claim 8, And a portion which connects the pixel electrode and the pixel signal line connection part and is inclined at an angle of 10 to 50 degrees with respect to the gate line.