KR20010083658A - Energy Recovery Apparatus in Plasma Display Panel - Google Patents

Abstract

PURPOSE: A power retrieval apparatus of a PDP(Plasma Display Panel) is provided, which can perform a high speed addressing. CONSTITUTION: An address driving part(36A) supplies a data pulse to an address electrode line, and a power retrieval apparatus withdraws a voltage charged in a capacitive load formed between the address electrode lines and charges it to an external capacitor. The power retrieval apparatus comprises at least more than two power retrieval units which generate a data voltage using the voltage charged in the capacitive load and also supply the data voltage to the address driving part. Each of the first and the second power retrieval unit(42,44) supplies the data voltage alternatively, and the data voltages generated from the first and the second power retrieval units are overlapped during the charging/discharging period of the capacitive load. The power retrieval apparatus also comprises a switching device to switch the data voltage by being connected between the power retrieval units and the address driving part. The switching device is a field effect transistor which is switched according to the existence of the data voltage.

Description

Power recovery device of plasma display panel {Energy Recovery Apparatus in Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power recovery apparatus for a plasma display panel, and more particularly, to a power recovery apparatus for a plasma display panel capable of high speed addressing.

Plasma Display Panel (hereinafter referred to as "PDP") is a display device using visible light generated from a phosphor when ultraviolet light generated by gas discharge excites the phosphor. PDP is thinner and lighter than Cathode Ray Tube (CRT), which has been the mainstay of display means, and has the advantage of being able to realize high definition large screen. PDP is composed of a plurality of discharge cells arranged in a matrix form, one discharge cell constitutes a pixel of the screen.

1 is a perspective view showing a conventional AC surface discharge PDP.

Referring to FIG. 1, a discharge cell of a three-electrode alternating surface discharge type PDP is formed on a scan / sustain electrode 12Y and a common sustain electrode 12Z formed on an upper substrate 10, and a lower substrate 18. An address electrode 20X is provided. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan / sustain electrode 12Y and the common sustain electrode 12Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan / sustain electrode 12Y and the common sustain electrode 12Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

Referring to FIG. 2, a conventional AC surface discharge type PDP driving apparatus includes m / n discharge cells 1 having scan / sustain electrode lines Y1 to Ym, common sustain electrode lines Z1 to Zm, and A PDP 30 arranged in a matrix so as to be connected to the address electrode lines X1 to Xn, a scan / sustain driver 32 for driving the scan / sustain electrode lines Y1 to Ym, and a common sustain; The common sustain driver 34 for driving the electrode lines Z1 to Zm, the odd-numbered address electrode lines X1, X3, ..., Xn-3, Xn-1 and the even-numbered address electrode lines X2. First and second address drivers 36A and 36B for dividing and driving .X4, ..., Xn-2, Xn are provided. The scan / sustain driver 32 sequentially supplies scan pulses and sustain pulses to the scan / sustain electrode lines Y1 to Ym so that the discharge cells 1 are sequentially scanned in line units, and m × n The discharge in each of the four discharge cells 1 is continued. The common sustain driver 34 supplies a sustain pulse to all of the common sustain electrode lines Z1 to Zm. The first and second address drivers 36A and 36B supply image data to the address electrode lines X1 through Xn in synchronization with the scan pulse. The first address driver 36A supplies image data to the odd-numbered address electrode lines X1, X3, ..., Xn-3, Xn-1, and the second address driver 36B supplies the even-numbered address electrode lines ( Image data is supplied to X2, X4, ..., Xn-2, Xn).

In the AC surface discharge PDP thus driven, a high voltage of several hundred volts or more is required for the address discharge and the sustain discharge. Accordingly, in order to minimize the driving power required for the address discharge and the sustain discharge, a power recovery device is added to the scan / sustain driver 32, the common sustain driver 34, and the address drivers 36A and 36B. The power recovery apparatus recovers the voltage charged between the scan / sustain electrode line (Y) and the common sustain electrode line (Z) and the voltage charged between the address electrode lines (X) and reuses it as a driving voltage at the next discharge. .

3 is a view showing a driving circuit of a conventional AC surface discharge PDP provided with a power recovery device in front of a scanning / sustain driving unit.

Referring to FIG. 3, the power recovery device 38 installed at the front end of the scan / sustain driver 32 includes an inductor L connected between the panel capacitor Cp and the source capacitor Cs, and a source capacitor Cs. And first and third switches S1 and S3 connected in parallel between and inductor L. The scan / sustain driver 32 includes second and fourth switches S2 and S4 connected in parallel between the panel capacitor Cp and the inductor L. The panel capacitor Cp equivalently represents the capacitance formed between the scan / sustain electrode line Y and the common sustain electrode line Z. FIG. The second switch S2 is connected to the sustain voltage source Vsus, and the fourth switch S4 is connected to the ground voltage source GND. The source capacitor Cs recovers and charges the voltage charged to the panel capacitor Cp during the sustain discharge, and supplies the charged voltage to the panel capacitor Cp again. The source capacitor Cs has a very large capacitance value to charge a voltage of Vsus / 2 corresponding to half of the sustain voltage Vsus. The inductor L forms a resonance circuit together with the panel capacitor Cp. The first to fourth switches S1 to S4 control the flow of current. The power recovery device 38 formed in the common sustain driver 34 is formed symmetrically with the scan / sustain driver 32 around the panel capacitor Cp.

4 is a timing diagram and waveform diagrams illustrating on / off timing of the switches illustrated in FIG. 3 and output waveforms of the panel capacitor.

The operation of the power recovery device 38 will be described with reference to FIGS. 3 and 4. First, it is assumed that the voltage charged between the scan / sustain electrode line Y and the common sustain electrode line Z, that is, the voltage charged in the panel capacitor Cp, before the T1 period is 0 volts. In addition, it is assumed that the source capacitor Cs is charged with a voltage of Vsus / 2. In the T1 period, the first switch S1 is turned on to form a current path from the source capacitor Cs to the first switch S1, the inductor L, and the panel capacitor Cp. At this time, the inductor L and the panel capacitor Cp form a series resonant circuit. Since the source capacitor Cs is charged with a voltage of Vsus / 2, the voltage of the panel capacitor Cp is increased to Vsus which is twice the voltage of the source capacitor Cs by the current charge / discharge of the inductor L in the series resonant circuit. Will rise. In the period T2, the second switch S2 is turned on. When the second switch S2 is turned on, the sustain voltage Vsus is supplied to the scan / sustain electrode line Y. The sustain voltage Vsus supplied to the scan / sustain electrode line Y prevents the voltage of the panel capacitor Cp from falling below the sustain voltage Vsus so that the sustain discharge occurs normally. At this time, since the voltage of the panel capacitor Cp rises to Vsus in the T1 period, the driving power supplied from the outside to minimize the sustain discharge is minimized. In the T3 period, the first switch S1 is turned off and maintains the sustain voltage supplied to the scan / sustain electrode line Y. In the T4 period, the second switch S2 is turned off and the third switch S3 is turned on. When the third switch S3 is turned on, a current path is formed from the panel capacitor Cp to the source capacitor Cs through the inductor L and the third switch S3 to charge the panel capacitor Cp. The voltage is recovered to the source capacitor Cs. As the panel capacitor Cp is discharged, the voltage of the panel capacitor Cp drops, and at the same time, the voltage of Vsus / 2 is charged to the source capacitor Cs. After the voltage of Vsus / 2 is charged to the source capacitor Cs, the third switch S3 is turned off and the fourth switch S4 is turned on. In the period T5 when the fourth switch S4 is turned on, a current path is formed from the panel capacitor Cp to the base voltage source GND, so that the voltage of the panel capacitor Cp drops to zero volts. In the T6 period, the state of the T5 period is maintained for a predetermined time. The AC drive pulses supplied to the actual scan / sustain electrode line Y and the common sustain electrode line Z are obtained by periodically repeating the operation process for the periods T1 to T6.

5 is a diagram illustrating a conventional AC surface discharge PDP provided with a power recovery device in front of an address driver.

Referring to FIG. 5, the conventional power recovery device 40 installed in front of the first address driver 36A includes an inductor L connected between the first address driver 36A and the source capacitor Cs, and a source. First and third switches S1 and S3 connected in parallel between the capacitor Cs and the inductor L, and second and third connected in parallel between the inductor L and the first address driver 36A. Four switches S2 and S4 are provided. The first address driver 36A includes fifth and sixth switches S5 and S6 connected in parallel between the panel capacitor Cp and the power recovery device 40. The panel capacitor Cp equivalently represents the capacitance formed between the address electrode lines X1 to Xn. The second switch S2 is connected to the voltage source Vd, and the fourth and sixth switches S4 and S6 are connected to the ground voltage source GND. The source capacitor Cs recovers and charges the voltage charged in the panel capacitor Cp during the address discharge, and supplies the charged voltage to the panel capacitor Cp again. The source capacitor Cs has a large capacitance so as to charge a voltage of Vd / 2 corresponding to half of the address voltage Vd. The inductor L forms a resonance circuit together with the panel capacitor Cp. The fifth switch S5 is turned on when the data pulse is supplied and is turned off when the data pulse is not supplied. The second address driver 36B and the power recovery device, which are connected to the first address driver 36A and the power recovery device 40 around the panel capacitor Cp, are connected to the first address driver 36B and the power recovery device. It has the same structure as 40.

6 is a timing diagram and waveform diagrams illustrating on / off timings of the switches illustrated in FIG. 5 and output waveforms of panel capacitors.

5 and 6 will be described in the operation of the power recovery device 40. First, it is assumed that the voltage charged between the address electrode lines X before the T1 period, that is, the voltage charged in the panel capacitor Cp is 0 volts. It is also assumed that the source capacitor Cs is charged with a voltage of Vd / 2. In the T1 period, the first and fifth switches S1 and S5 are turned on. At this time, if the discharge cell is not selected, that is, no data pulse is supplied to the address electrode line, the fifth switch S5 maintains the turn-off state. When the first and fifth switches S1 and S5 are turned on, a current path from the source capacitor Cs to the first switch S1, the inductor L, the fifth switch S5, and the panel capacitor Cp is obtained. Is formed. At this time, the inductor L and the panel capacitor Cp form a series resonant circuit. Since the source capacitor Cs is charged with a voltage of Vd / 2, the voltage of the panel capacitor Cp is increased to Vd twice the voltage of the source capacitor Cs by the current charge / discharge of the inductor L in the series resonant circuit. Will rise. In the T2 period, the second switch S2 is turned on. When the second switch S2 is turned on, the address voltage Vd is supplied to the address electrode line X. The address voltage Vd supplied to the address electrode line X prevents the voltage of the panel capacitor Cp from dropping below Vd so that address discharge occurs normally. At this time, since the voltage of the panel capacitor Cp increases to Vd in the T1 period, the driving power supplied from the outside to minimize the address discharge is minimized. In the T3 period, the first switch S1 is turned off and maintains the address voltage supplied to the address electrode line. In the T4 period, the second switch S2 is turned off and the third switch S3 is turned on. When the third switch S3 is turned on, a current path is formed from the panel capacitor Cp to the source capacitor Cs through the fifth switch S5, the inductor L, and the third switch S3. The voltage charged in the capacitor Cp is recovered to the source capacitor Cs. As the panel capacitor Cp is discharged, the voltage of the panel capacitor Cp drops, and at the same time, the voltage of the source capacitor Cs is charged with Vd / 2. In the T5 period, the third and fifth switches S3 and S5 are turned off, and the fourth and sixth switches S4 and S6 are turned on. When the fourth and sixth switches S4 and S6 are turned on, a current path is formed between the base voltage source GND and the panel capacitor Cp to lower the voltage of the panel capacitor Cp to 0 volts. If a data pulse is supplied in the next address period, the operation of T1 to T5 is repeated. The data pulses supplied to the actual address electrode lines X are obtained by periodically repeating the operation process for the periods T1 to T5.

In the conventional AC surface discharge PDP driven as described above, an address section is used at 2.5 ms or more. However, in the case where the pulse width Td of the address discharge pulse is increased to 2.5 ms or more, the ratio of sustain period which determines the brightness of the actual screen in one frame is 30 in the state that the duration of one frame is fixed to 16.67 ms. Falls below% In addition, in the current PDP driving method, the number of subfields per frame is increased from 8 to 10 to 12 in order to reduce contour noise generated in a moving picture. However, when the number of subfields increases during a fixed frame period, the period of each subfield is shortened by that much. Even in this case, the address period is fixed for each subfield for stable discharge, and only the sustain period is shortened. In a high-resolution PDP with an increased number of scan / sustain electrode lines, the sustain period becomes too short and the display itself becomes impossible. In the high resolution PDP, since the number of scan / sustain electrode lines is much larger, the address period in which the scan / sustain electrode lines are sequentially driven in each subfield is longer. Accordingly, the sustain period is inevitably reduced during the fixed one frame period. In order to solve this problem, fast addressing is required.

7 is a waveform diagram showing a conventional data pulse.

Referring to FIG. 7, a data pulse is obtained by recovering a source of T1 during which a voltage is charged in the panel capacitor Cp, a period of T2 during which a data pulse is supplied to the address electrode line X, and a voltage charged in the panel capacitor Cp. T3 period for charging the capacitor Cs, and T4 period for lowering the voltage of the panel capacitor Cp to 0 volts. At this time, the period required for the actual address discharge is the T2 period, and the T1, T3, and T4 periods are preliminary sections for charging the capacitors Cs and Cp. The preliminary sections T1, T3, and T4 occupy a greater proportion as fast addressing. That is, while the period T2, which is a period required for the actual address discharge, is reduced, the preliminary sections T1, T3, and T4 for charging the capacitors Cs and Cp are not reduced. Therefore, high speed addressing for a predetermined time or less is impossible by the preliminary sections T1, T3, and T4 for charging the capacitors Cs and Cp.

Accordingly, an object of the present invention is to provide a power recovery apparatus for a plasma display panel capable of high speed addressing.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode PDP.

FIG. 2 is a plan view showing an arrangement of electrode lines and discharge cells of the PDP shown in FIG. 1; FIG.

3 is a view showing a conventional power recovery device installed at the front end of the sustain drive unit.

FIG. 4 is a timing diagram and waveform diagram showing on / off timing of the switches shown in FIG. 3 and an output waveform of the panel capacitor. FIG.

5 is a view showing a conventional power recovery device installed in front of the address driver.

FIG. 6 is a timing diagram and waveform diagram showing on / off timing of the switches shown in FIG. 5 and an output waveform of the panel capacitor. FIG.

7 is a waveform diagram showing a data pulse generated by the power recovery device shown in FIG.

8 is a diagram showing a power recovery device of the present invention installed in front of an address driver.

9 and 10 are timing diagrams and waveform diagrams showing on / off timing of the switches shown in FIG. 8 and output waveforms of the panel capacitor.

FIG. 11 is a waveform diagram showing data pulses generated by the power recovery device shown in FIG. 8; FIG.

FIG. 12 shows the switch shown in FIG. 8; FIG.

<Description of Symbols for Main Parts of Drawings>

1: discharge cell 10: upper substrate

12Y: scan / sustain electrode 12Z: common sustain electrode

14,22 dielectric layer 16: protective film

18: lower substrate 20X: address electrode

24: partition 26: phosphor

30: PDP 32: scan / sustain drive unit

34: common sustain driver 36A: first address driver

36B: second address driver 38, 40, 42, 44: power recovery device

50,52: field effect transistor

In order to achieve the above object, the power recovery device of the display panel of the present invention is alternately driven to generate data voltage using a voltage charged in a capacitive load, and at least two or more powers to supply the data voltage to the address driver. Recovery means is provided.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 8 to 12.

Fig. 8 is a diagram showing an AC surface discharge PDP of the present invention in which a power recovery device is installed at the front end of the address driver.

Referring to FIG. 8, the first power recovery device 42 of the present invention installed at the front end of the first address driver 36A may include a first inductor connected between the seventh switch S7 and the first source capacitor Cs1. (L1), eleventh and thirteenth switches S11 and S13 connected in parallel between the first source capacitor Cs1 and the first inductor L1, and the first inductor L1 and the seventh switch S7. ) And a twelfth and fourteenth switch (S12, S14) connected in parallel to each other, and a seventh switch (S7) connected in series between the first power recovery device 42 and the first address driver (36A) do. The first address driver 36A includes fifth and sixth switches S5 and S6 connected between the panel capacitor Cp and the seventh switch S7. The second power recovery device 44 of the present invention has the same structure as the first power recovery device 42. That is, the 21st inductor L2 connected between the eighth switch S8 and the second source capacitor Cs2 and the 21st in parallel connected between the second source capacitor Cs2 and the second inductor L2 And twenty-second and twenty-second switches S22 and S24 connected in parallel between the twenty-third switches S21 and S23, the second inductor L2, and the eighth switch S8, and the second power recovery device 42. ) And an eighth switch S8 connected in series between the first address driver 36A. The first and second power recovery devices 42 and 44 of the present invention are operated alternately. Compared with the conventional power recovery device, in the present invention, the second power recovery device 44, the seventh and eighth switches provided between the power recovery devices 42 and 44 and the first address driver 36A It can be seen that S7, S8) is further provided. The panel capacitor Cp equivalently represents the capacitance formed between the address electrode lines X1 to Xn. The twelfth and twenty-second switches S12 and S22 are connected to the voltage source Vd, and the fourteenth switch S14, the twenty-fourth switch S24, and the sixth switch S6 are connected to the base voltage source GND. The first and second source capacitors Cs1 and Cs2 recover and charge the voltage charged in the panel capacitor Cp during address discharge, and re-supply the charged voltage to the panel capacitor Cp. The first and second source capacitors Cs1 and Cs2 have a large capacitance value to charge a voltage of Vd / 2 corresponding to half of the address voltage Vd. The first and second inductors L1 and L2 form a resonance circuit together with the panel capacitor Cp. The seventh and eighth switches S7 and S8 repeat the turn-on and turn-off operations depending on whether the first and second power recovery devices 42 and 44 are operated. The fifth switch S5 is turned on when the data pulse is supplied and is turned off when the data pulse is not supplied. The second address driver 36B and the power recovery devices, which are connected to the first address driver 36A and the power recovery devices 42 and 44 around the panel capacitor Cp, are connected to the first address driver 36A and the power recovery devices. It has the same configuration as the power recovery devices 42 and 44.

9 and 10 are timing and waveform diagrams illustrating on / off timings of the switches illustrated in FIG. 8 and output waveforms of panel capacitors.

8 to 10, the operation of the power recovery devices 42 and 44 will be described. First, it is assumed that the voltage charged between the address electrode lines X before the T1 period, that is, the voltage charged in the panel capacitor Cp is 0 volts. In addition, it is assumed that the source capacitors Cs1 and Cs2 are charged with a voltage of Vd / 2. In the T1 period, the eleventh, seventh, and fifth switches S11, S7, and S5 are turned on. At this time, if the discharge cell is not selected, that is, no data pulse is supplied to the address electrode line X, the fifth switch S5 maintains the turn-off state. When the eleventh, seventh, and fifth switches S11, S7, and S5 are turned on, the eleventh switch S11, the first inductor L1, the seventh switch S7, from the first source capacitor Cs1, A current path is formed that leads to the fifth switch S5 and the panel capacitor Cp. At this time, the first inductor L1 and the panel capacitor Cp form a series resonant circuit. Since the voltage of Vd / 2 is charged to the first source capacitor Cs1, the voltage of the panel capacitor Cp is changed by the current charge / discharge of the first inductor L1 in the series resonant circuit. It rises to Vd, which is twice the voltage. In the T2 period, the twelfth switch S12 is turned on. When the twelfth switch S12 is turned on, the address voltage Vd is supplied to the address electrode line X. The address voltage Vd supplied to the address electrode line X prevents the voltage of the panel capacitor Cp from falling below Vd so that address discharge occurs normally. At this time, since the voltage of the panel capacitor Cp increases to Vd in the T1 period, the driving power supplied from the outside to minimize the address discharge is minimized. In the T3 period, the eleventh switch S11 is turned off and the address voltage Vd supplied to the address electrode line X is maintained. In the T4 period, the twelfth switch S12 is turned off and the thirteenth switch S13 is turned on. When the thirteenth switch S13 is turned on, a current path is formed from the panel capacitor Cp to the fifth switch S5, the seventh switch S7, the first inductor L1, and the thirteenth switch S13. As a result, the voltage charged in the panel capacitor Cp is recovered to the first source capacitor Cs1. In the T4 period, the twenty-first switch S21 and the eighth switch S8 are turned on. When the twenty-first switch S21 and the eighth switch S8 are turned on, the twenty-first switch S21, the second inductor L2, the eighth switch S8, and the fifth switch from the second source capacitor Cs2. A current path is formed that leads to S5 and the panel capacitor Cp. At this time, the second inductor L2 and the panel capacitor Cp form a series resonant circuit. Since the voltage of Vd / 2 is charged to the second source capacitor Cs2, the voltage of the panel capacitor Cp is changed by the current charge / discharge of the second inductor L2 in the series resonant circuit. It rises to Vd, which is twice the voltage. That is, in the T4 period, the thirteenth switch S13, the seventh switch S7, the fifth switch S5, the eighth switch S8, and the twenty-first switch S21 are turned on to the panel capacitor Cp. The panel capacitor Cp is charged with the voltage charged in the second source capacitor Cs2 while recovering the charged voltage to the first source capacitor Cs1. In the T4 period, the first and second power recovery devices 42 and 44 overlap each other by the period in which the address voltage Vd changes. In the T5 period, the twenty-second switch S22 is turned on to supply the address voltage Vd to the address electrode line X. At this time, since the voltage of the panel capacitor Cp rises to Vd in the T4 period, the driving power supplied from the outside to minimize the address discharge is minimized. In the period T6, the twenty-first switch S21 is turned off and the address voltage Vd supplied to the address electrode line X is maintained. In the T7 period, the twenty-second switch S22 is turned off and the twenty-third switch S23 is turned on. When the twenty-third switch S13 is turned on, a current path is formed from the panel capacitor Cp to the fifth switch S5, the eighth switch S8, the second inductor L2, and the twenty-third switch S23. As a result, the voltage charged in the panel capacitor Cp is recovered to the second source capacitor Cs2. During the T7 period, the voltage charged in the panel capacitor Cp is recovered to the second source capacitor Cs2 as in the T4 period, and the panel capacitor Cp is charged with the voltage charged in the first source capacitor Cs1. That is, in the T7 period, similarly to the T4 period, the first second power recovery devices 42 and 44 operate to overlap. When no data pulse is supplied in the address period, the fourteenth switch S14, the twenty-fourth switch S24, and the sixth switch S6 are connected to the ground voltage source GND.

11 is a waveform diagram illustrating a voltage applied to a panel capacitor.

Referring to FIG. 11, the voltage Vcp1 applied by the first power recovery device 42 to the panel capacitor Cp, and the voltage applied to the panel capacitor Cp by the second power recovery device 44 Vcp2) and the voltage Vcp applied to the panel capacitor Cp by the first and second power recovery devices 42 and 44 are shown. The voltage Vcp1 applied to the panel capacitor Cp by the first power recovery device 42 is a data voltage generated in the periods T1 to T4 shown in FIG. 9. The voltage Vcp2 generated in the second power recovery device 44 is a data voltage generated in the periods T4 to T7 shown in FIG. 10. The voltages Vcp generated by the first and second power recovery devices 42 and 44 are data voltages input to the first address driver 36A. Contrast this with the waveform of the conventional power recovery device 40, it can be seen that the addressing time is shortened by the T4 period in which the first and second power recovery devices 42 and 44 operate in an overlapping manner.

FIG. 12 is a diagram illustrating a seventh switch and an eighth switch shown in FIG. 8.

12 will be described with reference to FIGS. 9 and 10.

Referring to FIG. 12, the seventh and eighth switches S7 and S8 of the present invention are composed of two field-effect transistors (hereinafter referred to as "FETs") 50 and 52. The first FET 50 is turned on in the T1 to T4 periods in which the first power recovery device 42 operates, and the second FET 52 in the T4 to T7 period in which the second power recovery device 44 operates. Is turned on. That is, in the T4 period, the first and second FETs 50 and 52 are turned on at the same time.

As described above, according to the power recovery device of the plasma display panel according to the present invention, the two power recovery devices are operated to overlap each other for a predetermined time. As a result, the pulse width of the data pulse can be shortened by the time that the power recovery device overlaps, thereby enabling high speed addressing. In addition, the voltage charged in the panel capacitor can be arbitrarily adjusted by connecting the switch of the power recovery device which is not operated to the ground voltage source.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (4)

An address driver for supplying a data pulse to an address electrode line and a power recovery device for recovering a voltage charged in a capacitive load formed between the address electrode lines and charging an external capacitor, At least two power recovery means for generating a data voltage using the voltage alternately driven and charged to the capacitive load, and supplying the data voltage to the address driver. Power recovery system. The method of claim 1, Each of the first and second power recovery means, Alternately supplying the data voltage to the address driver; And the data voltages respectively generated from the first and second power recovery means overlap each other by a period during which the capacitive load is charged / discharged. The method of claim 1, And a switching element connected between the at least two power recovery means and the address driver to switch a data voltage. The method of claim 3, wherein The switching device, And a field effect transistor switched according to whether or not the data voltage is supplied.