KR20010074948A - Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks - Google Patents
Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks Download PDFInfo
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- KR20010074948A KR20010074948A KR1020017002809A KR20017002809A KR20010074948A KR 20010074948 A KR20010074948 A KR 20010074948A KR 1020017002809 A KR1020017002809 A KR 1020017002809A KR 20017002809 A KR20017002809 A KR 20017002809A KR 20010074948 A KR20010074948 A KR 20010074948A
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- layer
- metal silicide
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- antireflective material
- depositing
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- 239000000463 material Substances 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 53
- 230000003667 anti-reflective effect Effects 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000003672 processing method Methods 0.000 title claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 52
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 41
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 29
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 16
- 239000001301 oxygen Substances 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 238000000059 patterning Methods 0.000 claims abstract 4
- 230000008021 deposition Effects 0.000 claims description 31
- 238000000137 annealing Methods 0.000 claims description 18
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 239000007787 solid Substances 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 95
- 238000006243 chemical reaction Methods 0.000 description 7
- 239000006117 anti-reflective coating Substances 0.000 description 6
- 230000005855 radiation Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 238000009828 non-uniform distribution Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000008033 biological extinction Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000010791 quenching Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
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- G—PHYSICS
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- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/091—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers characterised by antireflection means or light filtering or absorbing means, e.g. anti-halation, contrast enhancement
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
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- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
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Abstract
한 태양에서, 기판 위에 실리콘, 질소, 산소를 증착할 때 기체형태의 실리콘, 질소, 산소를 고밀도 플라즈마에 노출시키는 단계를 포함하는 반도체 공정법이 공개된다. 또하나의 태양에서 발명은, a) 기판(52) 위에 폴리실리콘층(56)을 형성하고, b) 폴리실리콘층(56) 위에 금속 실리사이드층(58)을 형성하며, c) 고밀도 플라즈마를 이용하여 금속 실리사이드층(58) 위에 반사방지 물질층(60)을 증착하고, d) 반사방지 물질층(60) 위에 포토레지스트층(62)을 형성하며, e) 포토레지스트층(62)으로부터 패턴처리된 마스크층을 형성하기 위해, 포토레지스트층(62)을 포토리소그래피 방식으로 패턴처리하고, 그리고 f) 반사방지 물질층, 금속 실리사이드층, 폴리실리콘층을 게이트 적층구조로 패턴처리하기 위해, 패턴처리된 마스크층(62)으로부터 반사방지 물질층(60), 금속 실리사이드층(58), 폴리실리콘층(56)까지 패턴을 전이하는, 이상의 단계를 포함하는 게이트 적층구조 형성 방법을 포함한다.In one aspect, a semiconductor processing method is disclosed that includes exposing a gaseous form of silicon, nitrogen, oxygen to a high density plasma when depositing silicon, nitrogen, oxygen on a substrate. In another aspect, the invention provides a process for a) forming a polysilicon layer 56 on a substrate 52, b) forming a metal silicide layer 58 on a polysilicon layer 56, and c) using a high density plasma. Thereby depositing an antireflective material layer 60 on the metal silicide layer 58, d) forming a photoresist layer 62 on the antireflective material layer 60, and e) patterning the photoresist layer 62. Pattern the photoresist layer 62 in a photolithographic manner to form a mask layer, and f) patterning the patterned antireflective material layer, metal silicide layer, and polysilicon layer into a gate stacked structure. And a method of forming a gate stacked structure including the above steps of transferring a pattern from the mask layer 62 to the antireflective material layer 60, the metal silicide layer 58, and the polysilicon layer 56.
Description
반도체 공정은 기판 위에 포토레지스트층을 제공하는 과정을 자주 포함한다. 포토레지스트층 부분은 마스크 처리된 광원을 통해 광에 노출된다. 마스크는 포토레지스트층에 생성될 패턴을 형성하는 투명 및 불투명 영역을 포함한다. 광에 노출되는 포토레지스트층 영역은 용매에 가용성이거나 불용성이도록 만들어진다. 노출된 영역이 가용성일 경우, 마스크의 양의 상이 포토레지스트에 생성된다. 따라서 포토레지스트는 양성 프로토레지스트로 불린다. 이에 반해, 비방사 영역이 용매에 의해 반응하지 않을 경우, 음의 상이 생긴다. 따라서, 이때 포토레지스트는 음성 포토레지스트로 불린다.Semiconductor processes often involve providing a photoresist layer on a substrate. The photoresist layer portion is exposed to light through a masked light source. The mask includes transparent and opaque regions that form a pattern to be created in the photoresist layer. The photoresist layer area exposed to light is made to be soluble or insoluble in the solvent. If the exposed area is soluble, a positive phase of the mask is created in the photoresist. The photoresist is therefore called a positive protoresist. In contrast, if the non-radiative region does not react with the solvent, a negative phase is produced. Thus, the photoresist at this time is called negative photoresist.
포토레지스트를 광에 노출시킬 때 발생할 수 있는 어려움은 방사파가 포토레지스트 아래의 층으로 포토레지스트를 통해 전파할 수 있고, 그후, 포토레지스트를통해 다시 반사되어 포토레지스트를 통과하는 다른 파동과 상호작용할 수 있다는 점이다. 반사된 파동은 포토레지스트를 통과하는 다른 파동과 보강 간섭이나 상쇄 간섭을 일으킬 수 있어서 포토레지스트 내의 광강도의 주기적 변화를 생성할 수 있다. 이러한 광강도의 변화로 인해 포토레지스트가 그 두께 전반에서 에너지의 균일하지 않은 분포를 수용하게 될 수 있다. 비균일한 분포는 마스크 처리 패턴이 포토레지스트로 옮겨질 때 정확성을 감소시킬 수 있다. 따라서, 포토레지스트층 하부의 층에 의해 반사되는 것을 방사파가 억제할 수 있는 방법을 개발하는 것이 요구된다.Difficulties that may arise when exposing the photoresist to light may cause radiation waves to propagate through the photoresist to a layer below the photoresist, which then reflects back through the photoresist and interacts with other waves passing through the photoresist. Can be. Reflected waves can cause constructive or destructive interference with other waves passing through the photoresist, producing periodic changes in light intensity within the photoresist. This change in light intensity can cause the photoresist to accept a non-uniform distribution of energy throughout its thickness. The non-uniform distribution can reduce the accuracy when the masked pattern is transferred to the photoresist. Therefore, it is desired to develop a method in which radiation waves can suppress reflection by the layer under the photoresist layer.
반사파를 억제하기 위해 사용된 방법은 포토레지스트층 아래 반사방지 물질을 형성하는 것이다. 반사방지 물질은 방사를 흡수하는 물질이어서, 방사의 반사를 억누를 수 있다. 반사방지 물질은 여러 파장의 파동을 효과를 달리하면서 흡수한다. 반사방지 물질로 사용하기에 적합한 물질의 수는 제한된다. 따라서, 흡수되는 파장을 변화시키는 대안의 방법, 그리고 반사 방지 물질에 대해 파동이 흡수될 때의 효과를 달리하는 대안의 방법을 개발하는 것이 바람직하다.The method used to suppress reflected waves is to form an antireflective material under the photoresist layer. The antireflective material is a material that absorbs radiation, thereby suppressing the reflection of the radiation. Antireflective materials absorb waves of varying wavelengths with varying effects. The number of materials suitable for use as antireflective materials is limited. Thus, it would be desirable to develop alternative methods for changing the wavelengths absorbed, and alternative methods for varying the effect of the wave absorption on the antireflective material.
특별한 종류의 반사방지 코팅 물질로는 증착형 반사방지 코팅(DARC)이 있다. DARC의 예로는 SixOyNz가 있고, 이때 x는 40-60%, y는 29-45%, 그리고 z는 10-16%이다. DARC는 예를 들어 Si50O37N13일 수 있다. SiH4와 N2O를 프리커서로 사용하여 4-6.5 Torr의 압력에서 섭씨 400도로 기판에 화학 증기 증착법을 실행함으로서 DARC가 형성될 수 있다. DARC 물질은 증착 중 반응 챔버 내에 플라즈마 존재 여부에 상관없이 증착될 수 있다. DARC 필름을 사용하는 통상적인 목적은 포토레지스트 상부층에 도달하는 반사파를 DARC 필름에서 입사파의 10% 이하로 감소시키는 것이다.A special kind of antireflective coating material is a deposition antireflective coating (DARC). Examples of DARC are Si x O y N z, where x is 40-60%, y is 29-45%, and z is 10-16%. DARC can be for example Si 50 O 37 N 13 . DARC can be formed by performing chemical vapor deposition on a substrate at 400 degrees Celsius at a pressure of 4-6.5 Torr using SiH 4 and N 2 O as a precursor. DARC materials may be deposited with or without plasma present in the reaction chamber during deposition. A common purpose of using DARC films is to reduce the reflected waves reaching the photoresist top layer to less than 10% of the incident waves in the DARC film.
DARC 물질을 이용한 공지 공정은 도 1에서 반도체 웨이퍼(10)를 들어 설명된다. 웨이퍼(10)는 기판(12)을 포함한다. 기판(12)은 배경 p형 도펀트로 약하게 도핑된 단결정 실리콘을 한 예로 포함할 수 있다. 첨부된 청구범위의 해석을 돕기 위해, "반도체 기판"이라는 용어는 반도체 웨이퍼와 같은 벌크 반도체 물질을 포함하는(그러나 이에 한정되지는 않는) 반도체 물질과, 반도체 물질층을 포함하는 모든 구조를 의미한다. "기판"이라는 용어는 앞서 언급한 반도체 기판을 포함하는(그러나 이에 한정되지는 않는) 모든 지지 구조를 의미한다.Known processes using DARC materials are described with the semiconductor wafer 10 in FIG. Wafer 10 includes substrate 12. The substrate 12 may include, for example, single crystal silicon slightly doped with a background p-type dopant. To aid the interpretation of the appended claims, the term "semiconductor substrate" refers to any structure including a semiconductor material, including but not limited to a bulk semiconductor material, such as a semiconductor wafer, and a layer of semiconductor material. . The term "substrate" means all supporting structures, including but not limited to the aforementioned semiconductor substrates.
게이트 유전층(14), 폴리실리콘층(16), 실리사이드층(18)이 기판(12) 위에 형성된다. 게이트 유전층(14)은 예를 들어 이산화규소를 포함할 수 있다. 폴리실리콘층(16)은 가령, 전도가능하게 도핑된 폴리실리콘을 포함할 수 있다. 실리사이드층(18)은 가령, 텅스텐 실리사이드나 티타늄 실리사이드를 포함할 수 있다. 층(14, 16, 18)은 궁극적으로는 트랜지스터 게이트 구조로 패턴 처리될 것이다.Gate dielectric layer 14, polysilicon layer 16, and silicide layer 18 are formed over substrate 12. Gate dielectric layer 14 may comprise silicon dioxide, for example. Polysilicon layer 16 may include, for example, polysilicon that is conductively doped. The silicide layer 18 may include, for example, tungsten silicide or titanium silicide. Layers 14, 16 and 18 will ultimately be patterned into transistor gate structures.
반사방지 코팅층(20)이 실리사이드층(18) 위에 제공되고, 포토레지스트층(22)이 반사방지 코팅층(20) 위에 제공된다. 반사방지 코팅층(20)은 SixOyNz와 같은 무기질층을 포함할 수 있다. 실제로, 층(20)은 본질적으로 무기질일 수 있고, "본질적으로 무기질"이라는 말은 층(20)이 소량의 탄소(1% 이하)를 포함할 수 있다는 것을 의미한다.An antireflective coating layer 20 is provided over the silicide layer 18, and a photoresist layer 22 is provided over the antireflective coating layer 20. The antireflective coating layer 20 may include an inorganic layer, such as Si x O y N z . Indeed, layer 20 may be inorganic in nature, and the term “essentially inorganic” means that layer 20 may contain a small amount of carbon (1% or less).
실리사이드층(18)은 트랜지스터 게이트에 층을 이용하기 전에 실리사이드층의 전도도와 결정 구조를 개선시키기 위해 어닐링 처리된다. 한 예로 실리사이드층(18)의 어닐링 처리는 대기압(1기압)에서 섭씨 850도로 30분간 실시된다.The silicide layer 18 is annealed to improve the conductivity and crystal structure of the silicide layer before using the layer in the transistor gate. As an example, annealing of the silicide layer 18 is performed at atmospheric pressure (1 atmosphere) for 30 minutes at 850 degrees Celsius.
어닐링 처리중 기체 산소로부터 층(18)을 보호하기 위해 어닐링 처리 전에 실리사이드층(18) 위에 DARC 물질(20)이 제공된다. 기체 산소가 어닐링 중에 층(18)과 반응하면, 산소는 층(18)의 일부를 산화시켜서 층(18)의 전도도에 악영향을 끼칠 수 있다. 불행하게도, 어닐링 조건은 DARC 물질(20)의 광학적 성질에 해로운 영향을 미칠 수 있다. 특히, DARC 물질(20)은 굴절률(n)과 소광 계수(에너지 흡수 계수)(k)로 표현할 수 있는 광학적 성질을 가진다. 실리사이드층(18)의 전도도를 개선시키는 어닐링 조건은 층(20)의 "n"과 "k"중 한 개나 두 개 모두를 변화시킬 수 있다. 방사파가 포토레지스트층(22)에 도달하기 전에 반사파를 소광시키도록 적절한 매개변수로 물질의 "n"과 "k"를 조절하도록 물질층(20)의 화학구조가 조심스럽게 선택된다. "n"과 "k"에 대한 어닐링 조건의 효과는 이러한 매개변수를 최적 조절 범위에서 밀어낼 수 있다. 따라서, 물질의 "n"과 "k"가 어닐링 조건에 의해 유도되는 변화에 둔감한 DARC 물질을 형성하는 방법을 개발하는 것이 요구된다.DARC material 20 is provided over the silicide layer 18 prior to the annealing treatment to protect the layer 18 from gaseous oxygen during the annealing treatment. If gaseous oxygen reacts with layer 18 during annealing, oxygen may oxidize a portion of layer 18, adversely affecting the conductivity of layer 18. Unfortunately, the annealing conditions can adversely affect the optical properties of the DARC material 20. In particular, the DARC material 20 has an optical property that can be expressed by the refractive index n and the extinction coefficient (energy absorption coefficient) k. Annealing conditions that improve the conductivity of the silicide layer 18 may change one or both of the “n” and “k” of the layer 20. The chemical structure of the material layer 20 is carefully selected to adjust the "n" and "k" of the material with appropriate parameters to quench the reflected wave before the radiation wave reaches the photoresist layer 22. The effect of the annealing conditions on "n" and "k" can push these parameters out of the optimum adjustment range. Thus, there is a need to develop a method of forming DARC materials that are insensitive to changes caused by annealing conditions in the "n" and "k" of the material.
본 발명은 반사방지 물질층 형성 및 이용법과 트랜지스터 게이트 적층구조 형성법에 관한 것이다.The present invention relates to methods of forming and utilizing antireflective material layers and methods of forming transistor gate stacks.
도 1은 기존 반도체 웨이퍼의 단면도.1 is a cross-sectional view of an existing semiconductor wafer.
도 2는 본 발명의 방법의 예비 단계에서 반도체 웨이퍼의 단면도.2 is a cross-sectional view of a semiconductor wafer in a preliminary step of the method of the present invention.
도 3은 도 2의 단계의 다음 단계의 웨이퍼 단면도.3 is a cross sectional view of the wafer following the steps of FIG. 2;
도 4는 도 3의 단계의 다음 단계의 웨이퍼 단면도.4 is a cross-sectional view of the wafer following the steps of FIG. 3;
도 5는 도 4의 단계의 다음 단계의 웨이퍼 단면도.5 is a cross-sectional view of the wafer following the steps of FIG. 4;
도 6은 본 발명의 방법에 사용될 수 있는 반응 챔버의 단면도.6 is a cross-sectional view of a reaction chamber that may be used in the method of the present invention.
(도면의 부호설명)(Description of symbols in the drawings)
10, 50, 110 ... 반도체 웨이퍼 12, 52 ... 기판10, 50, 110 ... semiconductor wafer 12, 52 ... substrate
14, 54 ... 게이트 유전층 16, 56 ... 폴리실리콘층14, 54 ... gate dielectric layer 16, 56 ... polysilicon layer
18, 58 ... 실리사이드층 20, 60 ... 반사방지 코팅층18, 58 ... silicide layer 20, 60 ... antireflective coating layer
22 ... 포토레지스트층 70 ... 게이트 적층구조22 ... photoresist layer 70 ... gate stacked structure
100 ... 반응기 102 ... 코일100 ... reactor 102 ... coil
104 ... 전원 106 ... 챔버104 ... Power 106 ... Chamber
108 ... 웨이퍼 홀더(척) 112 ... 전원108 ... wafer holder (chuck) 112 ... power supply
한 태양에서, 기판 위에 실리콘, 질소, 산소를 포함하는 고체층을 증착할 때 기체 형태의 실리콘, 질소, 그리고 산소가 고밀도 플라즈마에 노출되는 반도체 공정 방법을 본 발명이 포함한다.In one aspect, the invention includes a semiconductor processing method in which silicon, nitrogen, and oxygen in gaseous form are exposed to a high density plasma when depositing a solid layer comprising silicon, nitrogen, and oxygen on a substrate.
또다른 태양에서, 발명은 포토리소그래피 공정의 반도체 공정 방법을 포함한다. 금속 실리사이드층이 기판 위에 형성된다. 고밀도 플라즈마를 이용하여 반사방지 물질층이 금속 실리사이드층 위에 증착된다.In another aspect, the invention includes a semiconductor processing method of a photolithography process. A metal silicide layer is formed over the substrate. An antireflective material layer is deposited over the metal silicide layer using a high density plasma.
또하나의 태양에서, 발명은 트랜지스터 게이트 적층구조 형성 방법을 포함한다. 폴리실리콘층이 기판 위에 형성된다. 금속 실리사이드층이 폴리실리콘층 위에 형성된다. 고밀도 플라즈마를 이용하여 반사방지 물질층이 금속 실리사이드층 위에 증착된다. 반사방지 물질층 위에 포토레지스트층이 형성된다. 포토레지스트층은 포토리소그래피 방식으로 패턴 처리되어, 포토레지스트층으로부터 패턴처리된 마스크층을 형성한다. 패턴처리된 마스크층으로부터 반사방지 물질층, 금속 실리사이드층, 그리고 폴리실리콘층으로 패턴이 전이되어, 반사방지 물질층, 금속 실리사이드층, 폴리실리콘층을 트랜지스터 게이트 적층구조로 패턴처리한다.In another aspect, the invention includes a method of forming a transistor gate stack. A polysilicon layer is formed over the substrate. A metal silicide layer is formed over the polysilicon layer. An antireflective material layer is deposited over the metal silicide layer using a high density plasma. A photoresist layer is formed over the antireflective material layer. The photoresist layer is patterned by photolithography to form a patterned mask layer from the photoresist layer. The pattern is transferred from the patterned mask layer to the antireflective material layer, the metal silicide layer, and the polysilicon layer to pattern the antireflective material layer, the metal silicide layer, and the polysilicon layer in a transistor gate stack structure.
도 2는 발명의 방법의 예비 단계에서 반도체 웨이퍼(50)의 단면도이다. 웨이퍼(50)는 기판(52), 게이트 유전층(54), 폴리실리콘층(56), 실리사이드층(58)을 포함한다. 기판(52), 게이트 유전층(54), 폴리실리콘층(56), 그리고 실리사이드층(58)은 기판(12), 게이트 유전층(14), 폴리실리콘층(16), 그리고 실리사이드층(18)에 대해 도 1의 공지 구조에서 사용된 물질과 동일한 물질을 포함할 수 있다.2 is a cross sectional view of a semiconductor wafer 50 in a preliminary step of the method of the invention. Wafer 50 includes a substrate 52, a gate dielectric layer 54, a polysilicon layer 56, and a silicide layer 58. The substrate 52, the gate dielectric layer 54, the polysilicon layer 56, and the silicide layer 58 may be formed on the substrate 12, the gate dielectric layer 14, the polysilicon layer 16, and the silicide layer 18. The same material as used in the known structure of FIG. 1 may be included.
실리사이드층(58) 위에 DARC 물질층(60)이 형성된다. 기존 방법에 반해, DARC 물질(60)이 고밀도 플라즈마 증착을 이용하여 형성된다. 이러한 증착은 반응 챔버 내에서 발생할 수 있다. 첨부된 청구범위의 해석을 돕기 위하여, "고밀도 플라즈마"는 1010이온/cm3이상의 밀도를 가지는 플라즈마로 정의된다. 층(60)이 증착되는 웨이퍼(50) 부분은 증착 중에 섭씨 300-800 도로 유지되는 것이 선호되며, 섭씨 600도가 가장 선호된다. 웨이퍼 냉각을 위해 증착 중에 웨이퍼 후면에 헬륨을쏘임으로서 웨이퍼(50) 온도가 제어될 수 있다. 온도가 높을수록 조밀한 층(60)이 형성될 수 있다. 이러한 조밀한 층(60)은 덜 조밀한 층(60)에 비해 어닐링 조건에서 보다 안정할 수 있다. 층(60)을 증착할 때 반응 챔버 내의 선호되는 압력 범위는 1-100 mTorr이다. 고밀도 플라즈마 증착에 사용되는 공급 기체로는 SiH4, N2, O2, 그리고 아르곤이 있다.A DARC material layer 60 is formed over the silicide layer 58. In contrast to existing methods, DARC material 60 is formed using high density plasma deposition. Such deposition can take place in the reaction chamber. To aid the interpretation of the appended claims, “high density plasma” is defined as a plasma having a density of at least 10 10 ions / cm 3 . The portion of wafer 50 where layer 60 is deposited is preferably maintained at 300-800 degrees Celsius during deposition, with 600 degrees Celsius being most preferred. The wafer 50 temperature can be controlled by shooting helium at the wafer backside during deposition for wafer cooling. The higher the temperature, the denser the layer 60 can be formed. This dense layer 60 may be more stable at annealing conditions than the less dense layer 60. The preferred pressure range in the reaction chamber when depositing layer 60 is 1-100 mTorr. Feed gases used for high density plasma deposition include SiH 4 , N 2 , O 2 , and argon.
본 발명의 방법에 사용될 수 있는 반응 챔버가 반응기(100)의 일부로 도 6에 도시된다. 반응기(100)는 전원(104)에 연결된 코일(102)을 포함한다. 코일(102)은 반응 챔버(106)를 둘러싸며, 챔버(106) 내에 플라즈마를 생성하는 구조를 가진다. 웨이퍼 홀더(척)(108)는 전원(112)에 전기적으로 연결된다. 전원(104, 112)은 분리된 전원일 수도 있고, 단일 전원으로부터 발생하는 분리된 공급원일 수도 있다. 전원(104)으로부터의 전력은 한 예로 2000 와트일 수 있고, 13.6 MHz의 주파수를 포함할 수 있다. 전원(112)으로부터 웨이퍼(110)에 가해지는 전력은 200 와트 이하로 바이어스되는 것이 선호되며, 100 와트 바이어스가 가장 선호된다. 실제로, 바이어스 전력은 웨이퍼(110) 자체에서보다는 웨이퍼(110) 홀더인 척(108)에서 측정되는 것이 일반적이다.A reaction chamber that can be used in the method of the present invention is shown in FIG. 6 as part of the reactor 100. Reactor 100 includes a coil 102 connected to a power source 104. The coil 102 surrounds the reaction chamber 106 and has a structure for generating a plasma in the chamber 106. Wafer holder (chuck) 108 is electrically connected to a power source 112. The power supplies 104 and 112 may be separate power supplies or separate sources that originate from a single power supply. The power from power source 104 may be 2000 watts as an example and may include a frequency of 13.6 MHz. The power applied from the power supply 112 to the wafer 110 is preferably biased to 200 watts or less, with a 100 watt bias being most preferred. In practice, the bias power is generally measured at the chuck 108, which is a holder of the wafer 110, rather than at the wafer 110 itself.
공급 기체가 반응 챔버(106)로 흐르는 예는 SiH4100 sccm, N2150 sccm, O2150 sccm, 그리고 아르곤 200 sccm이다. 본 발명의 고압 플라즈마 공정에서 반도체 웨이퍼에 층(60)(도 2)을 증착하는 동안, 증착 및 에칭 공정이 동시에 일어나, 증착-에칭 비를 나타낼 것이다. 증착 속도는 에칭 속도보다 빨라서, 알짜 효과는 물질이 웨이퍼에 증착되는 것이다. 증착 속도는 증착 중에 기판에 바이어스를 제공하지 않음으로서 연산될 수 있고, 에칭 속도는 어떤 증착 프리커서도 반응기(106) 내로 공급되지 않을 때 에칭 속도를 결정함으로서 계산될 수 있다. 기판(110)에 대한 바이어스 전력을 조절함으로서 증착-에칭비의 수정은 증착된 층(60)의 "n"과 "k" 갓에 영향을 미치도록 사용될 수 있다.Examples of a feed gas flowing into the reaction chamber 106 are SiH 4 100 sccm, N 2 150 sccm, O 2 150 sccm, and 200 sccm of argon. During the deposition of layer 60 (FIG. 2) on a semiconductor wafer in the high pressure plasma process of the present invention, the deposition and etching processes will occur simultaneously, indicating a deposition-etch ratio. The deposition rate is faster than the etching rate, so the net effect is that the material is deposited on the wafer. The deposition rate can be calculated by not providing a bias to the substrate during deposition, and the etch rate can be calculated by determining the etch rate when no deposition precursor is fed into the reactor 106. Modification of the deposition-etching ratio by adjusting the bias power for the substrate 110 may be used to affect the "n" and "k" shades of the deposited layer 60.
도 2에서, 실리사이드층(58)은 DARC 물질(60)의 증착 후 어닐링 처리된다. 본 발명의 고압 플라즈마 증착은 실리사이드층(58)의 어닐링 처리중 물질(60)의 광학적 성질(가령 "n"과 "k" 값)의 가변성을 감소시킬 수 있다. 예를 들어, 본 명세서의 "배경기술" 단락에서 논의된 조건을 이용한 어닐링 처리에 의해 유도되는 "n"과 "k" 값의 변화는 10% 이하로 제한될 수 있다.In FIG. 2, silicide layer 58 is annealed after deposition of DARC material 60. The high pressure plasma deposition of the present invention can reduce the variability of the optical properties of the material 60 (eg, "n" and "k" values) during annealing the silicide layer 58. For example, the change in the "n" and "k" values induced by the annealing treatment using the conditions discussed in the "Background" paragraphs herein may be limited to 10% or less.
도 3에서, DARC 물질(60) 위에 포토레지스트층(62)이 형성된다. 층(62) 부분을 제거하고 도 4에 도시되는 구조를 형성하기 위해 마스크 처리된 광원과 용매에 노출시킴으로서 포토레지스트층(62)이 패턴처리된다.In FIG. 3, a photoresist layer 62 is formed over the DARC material 60. The photoresist layer 62 is patterned by removing part of the layer 62 and exposing it to a masked light source and solvent to form the structure shown in FIG.
층(62)으로부터 하부층(54, 56, 58, 60)으로 패턴이 전이되어, 도 5에 도시되는 게이트 적층구조(70)를 형성한다. 게이트 적층구조가 층(60, 58, 56)을 포함하고 층(54)이 패턴처리되지 않는 실시예도 발명에 또한 포함된다. 포토레지스트층(62)으로부터 하부층(54, 56, 58, 60)으로 패턴을 전이하는 방법은 플라즈마 에칭이다. 게이트 적층구조(60)가 형성된 후, 포토레지스트층(62)이 제거될 수 있다. 또한, 게이트 적층구조(70) 주변에 소스 및 드레인 영역이 주입될 수 있고, 게이트 적층구조로부터 트랜지스터 게이트 구조를 형성하기 위해 게이트 적층구조(70)의 측벽을 따라 측벽 스페이서가 형성될 수 있다.The pattern is transferred from the layer 62 to the lower layers 54, 56, 58, and 60 to form the gate stacked structure 70 shown in FIG. Also included in the invention are embodiments in which the gate stack includes layers 60, 58, 56 and layer 54 is not patterned. The method of transferring the pattern from the photoresist layer 62 to the underlying layers 54, 56, 58, 60 is plasma etching. After the gate stack 60 is formed, the photoresist layer 62 may be removed. In addition, source and drain regions may be implanted around the gate stack 70, and sidewall spacers may be formed along sidewalls of the gate stack 70 to form a transistor gate structure from the gate stack.
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1998
- 1998-09-03 US US09/146,841 patent/US6268282B1/en not_active Expired - Lifetime
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1999
- 1999-08-31 JP JP2000569431A patent/JP3542118B2/en not_active Expired - Fee Related
- 1999-08-31 AU AU55907/99A patent/AU5590799A/en not_active Abandoned
- 1999-08-31 KR KR10-2001-7002809A patent/KR100423560B1/en not_active IP Right Cessation
- 1999-08-31 WO PCT/US1999/020030 patent/WO2000014781A1/en active IP Right Grant
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2001
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2004
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WO2000014781A1 (en) | 2000-03-16 |
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JP2002524873A (en) | 2002-08-06 |
US7151054B2 (en) | 2006-12-19 |
US6727173B2 (en) | 2004-04-27 |
US20010044221A1 (en) | 2001-11-22 |
JP3542118B2 (en) | 2004-07-14 |
AU5590799A (en) | 2000-03-27 |
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