KR20010068590A - Wafer level package - Google Patents
Wafer level package Download PDFInfo
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- KR20010068590A KR20010068590A KR1020000000583A KR20000000583A KR20010068590A KR 20010068590 A KR20010068590 A KR 20010068590A KR 1020000000583 A KR1020000000583 A KR 1020000000583A KR 20000000583 A KR20000000583 A KR 20000000583A KR 20010068590 A KR20010068590 A KR 20010068590A
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- South Korea
- Prior art keywords
- metal
- pattern
- level package
- wafer level
- conductive pillar
- Prior art date
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical group [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 abstract description 36
- 235000012431 wafers Nutrition 0.000 description 21
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 238000005336 cracking Methods 0.000 description 1
- 239000013013 elastic material Substances 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 239000000806 elastomer Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 웨이퍼 레벨 패키지에 관한 것으로서, 보다 구체적으로는 웨이퍼 상태에 패키징 공정이 실시되어 구성되는 웨이퍼 레벨 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer level package, and more particularly, to a wafer level package in which a packaging process is performed on a wafer state.
반도체 패키지는 반도체 칩의 본드 패드에 전기적으로 연결된 접속 매개체를 포함한다. 접속 매개체는 통상적으로 금속 와이어에 의해 본드 패드에 연결되고, 전체 결과물이 봉지제로 봉지된다. 한편, 봉지제로부터 노출된 접속 매개체의 볼 랜드에 보드에 실장되는 외부 접속 단자가 접합된다. 현재 반도체 패키지의 외부 접속 단자로는 솔더 볼이 주로 사용된다. 솔더 볼은 기존의 리드 프레임보다 전기 신호 전달 경로가 대폭 단축되는 잇점이 있다.The semiconductor package includes a connection medium electrically connected to the bond pads of the semiconductor chip. The connection medium is typically connected to the bond pads by metal wires, and the entire result is encapsulated with an encapsulant. On the other hand, the external connection terminal mounted on a board is joined to the ball land of the connection medium exposed from the sealing agent. Currently, solder balls are mainly used as external connection terminals of semiconductor packages. Solder balls have the advantage of significantly shorter electrical signal paths than conventional lead frames.
한편, 현재 주류를 이루면서 개발 추세에 있는 패키지는 개개의 반도체 칩에 대해 패키징 공정이 실시되는 형태가 아니라 웨이퍼 레벨에서 모든 패키징 공정이 실시된 후 웨이퍼를 절단하여 개개의 반도체 칩으로 분리하여 구성되는 웨이퍼 레벨 패키지로서, 도 1에 종래의 웨이퍼 레벨 패키지가 단면도로 도시되어 있다.On the other hand, a package that is currently in the mainstream and developing trend is not a packaging process for individual semiconductor chips, but a wafer formed by cutting wafers and separating them into individual semiconductor chips after all packaging processes are performed at the wafer level. As a level package, a conventional wafer level package is shown in cross section in FIG.
도 1에 도시된 바와 같이, 반도체 칩(1)의 표면에 패턴 필름(2)이 접착되어 있다. 패턴 필름(2)은 폴리이미드와 같은 절연층(2b)상에 구리 재질의 금속 패턴(2c)이 형성된 구조로 이루어진다. 즉, 절연층(2b)의 밑면이 접착제(2a)를 매개로 반도체 칩(1) 표면에 접착되어 있고, 금속 패턴(2c)의 표면에는 솔더 레지스트(2d)가 도포되어서, 이 솔더 레지스트(2d)로부터 금속 패턴(2c)이 국부적으로 노출되어 볼 랜드를 형성하도록 되어 있다. 한편, 반도체 칩(1)의 본드 패드(3)는 금속 와이어(4)를 매개로 금속 패턴(2c)상에 전기적으로 연결되어 있고, 이러한 와이어 본딩 영역이 봉지제(5)로 봉지되어 있다. 금속 패턴(2c)의 볼 랜드에는 솔더 볼(6)이 마운트되어 있다.As shown in FIG. 1, the pattern film 2 is adhered to the surface of the semiconductor chip 1. The pattern film 2 has a structure in which a metal pattern 2c of copper material is formed on an insulating layer 2b such as polyimide. That is, the bottom surface of the insulating layer 2b is adhered to the surface of the semiconductor chip 1 via the adhesive 2a, and the solder resist 2d is applied to the surface of the metal pattern 2c, and this solder resist 2d ), The metal pattern 2c is locally exposed to form a ball land. On the other hand, the bond pad 3 of the semiconductor chip 1 is electrically connected to the metal pattern 2c via the metal wire 4, and such a wire bonding area is sealed with the sealing agent 5. The solder balls 6 are mounted on the ball lands of the metal pattern 2c.
한편, 이러한 구성요소들은 웨이퍼에 일괄적으로 구성된 후, 웨이퍼를 스크라이브 라인을 따라 절단하여 개개의 반도체 칩으로 분리하는 것에 의해, 웨이퍼 레벨 패키지가 완성된다.On the other hand, these components are collectively configured on the wafer, and then the wafer level package is completed by cutting the wafer along the scribe line and separating the individual semiconductor chips.
그런데, 외부 접속 단자로 종래에 사용되는 솔더 볼은 명칭대로 볼 형상이다. 이로 인하여, 각 솔더 볼간의 접촉 방지를 위해, 솔더 볼간의 피치에는 제한이 따른다. 그러므로, 점차 고집적화되어 핀의 수가 많아지는 반도체 칩의 개발 추세에 따라, 하나의 패키지에 마운트되는 솔더 볼의 수도 증가되어야 하는데, 이러한 제한 때문에 솔더 볼의 사용에 제약이 따른다.By the way, the solder ball conventionally used as an external connection terminal is a ball shape according to the name. For this reason, in order to prevent the contact between each solder ball, the pitch between solder balls is limited. Therefore, with the development trend of semiconductor chips in which the number of pins is gradually increased and the number of pins increases, the number of solder balls mounted in one package must be increased, which limits the use of solder balls.
이를 해소하기 위해서는, 솔더 볼의 크기를 줄여서 피치를 좁히므로써, 솔더 볼의 수를 증가시키는 방안을 고려해볼 수는 있으나, 솔더 볼의 접합 강도 취약이라는 새로운 문제가 발생된다. 보다 구체적으로, 솔더 볼을 외부 접속 단자로 사용하는 패키지에서는, 솔더 볼이 보드에 마운트된 후의 솔더 볼의 접합 강도가 항상 대두되는 문제이다. 그 이유는, 반도체 칩과 보드간의 열팽창계수 차이가 매우 커서, 열팽창계수 차이로 인한 열적 응력이 솔더 볼에 집중되어, 솔더 볼에 크랙이 발생되기 때문이다.In order to solve this problem, a method of increasing the number of solder balls by narrowing the pitch by reducing the size of the solder balls may be considered. However, a new problem arises in that the solder balls have weak bonding strength. More specifically, in a package using the solder ball as an external connection terminal, the bonding strength of the solder ball after the solder ball is mounted on the board is always a problem. The reason is that the difference in thermal expansion coefficient between the semiconductor chip and the board is very large, and thermal stress due to the difference in thermal expansion coefficient is concentrated in the solder ball, causing cracks in the solder ball.
그래서, 종래에는 솔더 볼의 접합 강도 강화를 위한 여러 가지 방안이 제시되었으나, 현재까지는 큰 실효성을 거두지 못하고 있는 실정이다. 이러한 상황에서, 솔더 볼의 크기를 줄이게 되면, 솔더 볼의 실장 면적도 비례하여 축소되므로, 접합 강도가 취약한 문제가 더 크게 대두된다.Therefore, in the related art, various methods for strengthening the bonding strength of solder balls have been proposed, but have not been able to achieve great effectiveness until now. In such a situation, if the size of the solder ball is reduced, the mounting area of the solder ball is also reduced in proportion, so that the problem of weak bonding strength is raised.
결과적으로, 솔더 볼에 크랙이 발생되는 문제를 해소하기 전에는 솔더 볼의크기를 줄이는 방안은 실효성이 없고, 따라서 솔더 볼의 수에 제한을 받게 된다.As a result, until the problem of cracking in the solder balls is eliminated, the method of reducing the size of the solder balls is not practical, and thus the number of solder balls is limited.
본 발명은 상기된 제약을 해소하기 위해 안출된 것으로서, 외부 접속 단자를 기존의 솔더 볼에서 서로간의 피치가 미세하게 구현되는 다른 수단으로 변경하여, 외부 접속 단자의 수를 고집적화되는 반도체 칩의 개발 추세에 따라 증가시킬 수 있는 웨이퍼 레벨 패키지를 제공하는데 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned constraints, and the trend of developing semiconductor chips in which the number of external connection terminals is highly integrated by changing the external connection terminals to other means in which the pitch between each other is finely realized in the existing solder ball. It is an object to provide a wafer level package that can be increased according to.
도 1은 종래의 웨이퍼 레벨 패키지를 나타낸 단면도.1 is a cross-sectional view showing a conventional wafer level package.
도 2 내지 도 6은 본 발명에 따른 웨이퍼 레벨 패키지를 제조 공정 순서대로 나타낸 단면도.2 to 6 are cross-sectional views of wafer level packages according to the present invention in the order of manufacturing process.
도 7 및 도 8은 본 발명의 주요부인 도전성 필라의 다른 변형예를 나타낸 도면.7 and 8 show another modified example of the conductive pillar, which is an essential part of the present invention.
- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-
10 ; 웨이퍼 11 ; 본드 패드10; Wafer 11; Bond pad
20 ; 패턴 필름 22 ; 절연층20; Pattern film 22; Insulation layer
23 ; 금속 패턴 24 ; 솔더 레지스트23; Metal pattern 24; Solder resist
30 ; 금속 와이어 40 ; 봉지제30; Metal wire 40; Encapsulant
50 ; 도전성 필라 51 ; 금속막50; Conductive pillars 51; Metal film
상기와 같은 목적을 달성하기 위해, 본 발명에 따른 웨이퍼 레벨 패키지는 다음과 같은 구성으로 이루어진다.In order to achieve the above object, the wafer level package according to the present invention has the following configuration.
본드 패드가 배치된 반도체 칩의 표면에 본드 패드가 노출되도록 패턴 필름이 접착된다. 패턴 필름은 절연층상에 금속 패턴이 배열되고, 이 금속 패턴은 솔더 레지스트에 의해 국부적으로 노출된 구조로서, 금속 패턴의 노출 부분이 금속 와이어를 매개로 반도체 칩의 본드 패드에 전기적으로 연결된다. 금속 와이어가 위치한 와이어 본딩 영역이 봉지제로 봉지된다. 금속 패턴의 다른 노출 부분인 볼 랜드에 얇은 줄 형태의 도전성 필라(pillar)가 접합된다. 도전성 필라는 니켈과 같은 금속막으로 도금되는 것이 바람직하다.The pattern film is bonded so that the bond pads are exposed on the surface of the semiconductor chip on which the bond pads are disposed. The pattern film is a metal pattern is arranged on the insulating layer, the metal pattern is a structure that is locally exposed by the solder resist, the exposed portion of the metal pattern is electrically connected to the bond pad of the semiconductor chip via the metal wire. The wire bonding area where the metal wire is located is encapsulated with an encapsulant. A thin line-shaped conductive pillar is bonded to the ball land, another exposed portion of the metal pattern. The conductive pillar is preferably plated with a metal film such as nickel.
상기된 본 발명의 구성에 의하면, 외부 접속 단자로 기존의 솔더 볼 대신에 도전성 필라가 사용되므로써, 얇은 줄 형태인 도전성 필라는 서로간의 피치를 미세하게 좁힐 수가 있으므로, 외부 접속 단자의 수를 고집적화되는 반도체 칩에 따라 증가시킬 수가 있게 된다.According to the above-described configuration of the present invention, since conductive pillars are used instead of the conventional solder balls as the external connection terminals, the conductive pillars in the form of thin lines can be finely narrowed to each other, thereby increasing the number of external connection terminals. It can be increased according to the semiconductor chip.
이하, 본 발명의 바람직한 실시예를 첨부도면에 의거하여 설명한다.Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described based on the accompanying drawings.
도 2 내지 도 6은 본 발명에 따른 웨이퍼 레벨 패키지를 제조 공정 순서대로 나타낸 단면도이고, 도 7 및 도 8은 본 발명의 주요부인 도전성 필라의 다른 변형예를 나타낸 도면이다.2 to 6 are cross-sectional views showing the wafer level package according to the present invention in the order of manufacturing process, and FIGS. 7 and 8 show another modified example of the conductive pillar, which is a main part of the present invention.
먼저, 도 2에 도시된 바와 같이, 웨이퍼(10)에는 복수개의 반도체 칩이 구성되어 있고, 각 반도체 칩의 본드 패드(11)는 웨이퍼(10) 표면에 배치되어 있다. 이러한 상태에서, 패턴 필름(20)을 접착제(21)를 매개로 웨이퍼(10) 표면에 접착한다. 접착제(21)는 응력 흡수 기능을 갖는 엘라스토머와 같은 탄성 재질인 것이 바람직하다.First, as shown in FIG. 2, a plurality of semiconductor chips are formed on the wafer 10, and the bond pads 11 of each semiconductor chip are disposed on the surface of the wafer 10. In this state, the pattern film 20 is adhered to the surface of the wafer 10 via the adhesive 21. The adhesive 21 is preferably an elastic material such as an elastomer having a stress absorbing function.
한편, 패턴 필름(20)에는 개구부가 형성되어서, 이 개구부를 통해 본드 패드(11)가 노출된다. 패턴 필름(20)은 폴리이미드와 같은 절연층(22)상에 접착제(25)를 매개로 금속 패턴(23)이 접착되고, 금속 패턴(23)상에는 솔더 레지스트(24)가 도포되어서, 금속 패턴(23)은 국부적으로 노출된 구조이다.On the other hand, an opening part is formed in the pattern film 20, and the bond pad 11 is exposed through this opening part. In the pattern film 20, the metal pattern 23 is adhered to the insulating layer 22, such as polyimide, via the adhesive 25, and the solder resist 24 is coated on the metal pattern 23. (23) is a locally exposed structure.
이어서, 도 3과 같이, 본드 패드(11)와 개구부 안쪽을 통해 노출된 금속 패턴(23) 부분을 금속 와이어(30)를 매개로 전기적으로 연결시킨다. 이어서, 금속 와이어(30)가 위치한 개구부, 즉 와이어 본딩 영역 전체를 봉지제(40)로 봉지하면, 도 4와 같은 구조가 된다. 이때, 금속 패턴(23)의 다른 노출 부분, 즉 볼 랜드는 봉지제(40)로부터 노출된 상태이다.Subsequently, as illustrated in FIG. 3, the bond pad 11 and the portion of the metal pattern 23 exposed through the inside of the opening are electrically connected through the metal wire 30. Subsequently, when the opening where the metal wire 30 is located, that is, the entire wire bonding region, is sealed with the encapsulant 40, a structure as shown in FIG. 4 is obtained. At this time, another exposed portion of the metal pattern 23, that is, the ball land, is exposed from the encapsulant 40.
그런 다음, 도 5에 도시된 바와 같이, 본 발명에서 제시되는 외부 접속 단자인 도전성 필라(50)를 금속 패턴(23)의 볼 랜드에 접합한다. 도전성 필라(50)는 얇은 줄 형태로서, 기존의 솔더 볼보다 서로간의 피치가 대폭 줄어든다는 잇점이 있다. 한편, 도전성 필라(50)의 재질로는 금이나 알루미늄 또는 구리인 것이 바람직하다. 또한, 도전성 필라(50)의 강도 보강을 위해, 도전성 필라(50)에 도금을 실시하여 금속막(51)으로 도전성 필라(50)를 피복하는 것이 바람직하다. 한편, 금속막(51)의 재질로는 니켈이 바람직하다.Then, as shown in Fig. 5, the conductive pillar 50, which is an external connection terminal presented in the present invention, is bonded to the ball land of the metal pattern 23. The conductive pillar 50 is in the form of a thin line, which has the advantage that the pitch between each other is significantly reduced than the conventional solder ball. On the other hand, the material of the conductive pillar 50 is preferably gold, aluminum or copper. In addition, in order to reinforce the strength of the conductive pillar 50, it is preferable to coat the conductive pillar 50 and coat the conductive pillar 50 with the metal film 51. On the other hand, nickel is preferable as the material of the metal film 51.
마지막으로, 스크라이브 라인을 따라 웨이퍼(10)를 절단하여 개개의 반도체 칩으로 분리하면, 도 6에 도시된 본 발명에 따른 웨이퍼 레벨 패키지가 완성된다. 한편, 도 6에 도시된 도전성 필라(50)는 대략 S자 형상이나 반드시 이러한 형상에 국한되지 않는다. 즉, 도 7 및 도 8에 도시된 바와 같이, 도전성 필라(50)는 I자형이나 L자형일 수도 있다.Finally, cutting the wafer 10 along the scribe line and separating it into individual semiconductor chips, a wafer level package according to the invention shown in FIG. 6 is completed. On the other hand, the conductive pillar 50 shown in FIG. 6 is substantially S-shaped, but is not necessarily limited to such a shape. That is, as illustrated in FIGS. 7 and 8, the conductive pillar 50 may be I-shaped or L-shaped.
한편, 본 발명에서와 같이 외부 접속 단자로서 종래의 솔더 볼 대신에 도전성 필라(50)를 사용하게 되면, 전술된 바와 같이 피치가 좁혀지는 잇점이 있으므로, 외부 접속 단자의 수를 종래보다 대폭 증가시킬 수가 있는데, 종래와 본 발명에 따른 외부 접속 단자의 수를 비교한 예가 하기 표 1에 나타나 있다.On the other hand, when the conductive pillar 50 is used instead of the conventional solder ball as the external connection terminal as in the present invention, the pitch is narrowed as described above, so that the number of external connection terminals can be greatly increased. Although the number of external connection terminals according to the present invention and the prior art is compared, it is shown in Table 1 below.
표 1Table 1
상기 표 1에서와 같이, 솔더 볼의 피치는 0.50㎜이고 필라의 피치는 0.35㎜이므로, 종래의 솔더 볼 수는 256개인데 반해 본 발명의 필라는 484개로서, 대략 2배 정도가 된다.As shown in Table 1, since the pitch of the solder balls is 0.50 mm and the pitch of the pillars is 0.35 mm, the number of conventional solder balls is 256, whereas the number of pillars of the present invention is 484, which is approximately twice that.
이상에서 설명한 바와 같이 본 발명에 의하면, 외부 접속 단자로서 기존의 솔더 볼 대신에 도전성 필라가 사용되므로써, 외부 접속 단자간의 피치를 좁힐 수가 있게 된다. 그러므로, 패키지에 외부 접속 단자의 수를 증가시키는 것이 구현되어, 고집적화되는 반도체 칩의 개발 추세에 본 발명에 따른 패키지가 효용 가치가 매우 높다는 것은 명백하다.As described above, according to the present invention, since the conductive pillar is used instead of the conventional solder ball as the external connection terminal, the pitch between the external connection terminals can be narrowed. Therefore, it is evident that increasing the number of external connection terminals in the package is implemented, so that the package according to the present invention has a very high utility value in the development trend of highly integrated semiconductor chips.
이상에서는 본 발명의 바람직한 실시예에 대하여 도시하고 또한 설명하였으나, 본 발명은 상기한 실시예에 한정되지 않고, 이하 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진자라면 누구든지 다양한 변경 실시가 가능할 것이다.Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the above-described embodiments, and the present invention is not limited to the above-described claims, and the present invention is not limited to the scope of the present invention. Anyone with knowledge will be able to make various changes.
Claims (4)
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| KR1020000000583A KR20010068590A (en) | 2000-01-07 | 2000-01-07 | Wafer level package |
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| KR1020000000583A KR20010068590A (en) | 2000-01-07 | 2000-01-07 | Wafer level package |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100771873B1 (en) * | 2006-06-19 | 2007-11-01 | 삼성전자주식회사 | Semiconductor package and method of mounting the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980055816A (en) * | 1996-12-28 | 1998-09-25 | 문정환 | Manufacturing Method of Chip Size Semiconductor Package |
| KR19990039990A (en) * | 1997-11-15 | 1999-06-05 | 구본준 | Manufacturing method of chip size semiconductor package |
| JPH11186328A (en) * | 1997-12-25 | 1999-07-09 | Sony Corp | Semiconductor device |
| KR20000008346A (en) * | 1998-07-13 | 2000-02-07 | 윤종용 | Flip chip package and method thereof |
| KR100253376B1 (en) * | 1997-12-12 | 2000-04-15 | 김영환 | Chip size semiconductor package and fabrication method thereof |
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2000
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980055816A (en) * | 1996-12-28 | 1998-09-25 | 문정환 | Manufacturing Method of Chip Size Semiconductor Package |
| KR19990039990A (en) * | 1997-11-15 | 1999-06-05 | 구본준 | Manufacturing method of chip size semiconductor package |
| KR100253376B1 (en) * | 1997-12-12 | 2000-04-15 | 김영환 | Chip size semiconductor package and fabrication method thereof |
| JPH11186328A (en) * | 1997-12-25 | 1999-07-09 | Sony Corp | Semiconductor device |
| KR20000008346A (en) * | 1998-07-13 | 2000-02-07 | 윤종용 | Flip chip package and method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100771873B1 (en) * | 2006-06-19 | 2007-11-01 | 삼성전자주식회사 | Semiconductor package and method of mounting the same |
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