KR100349362B1 - Wafer level package and method of fabricating the same - Google Patents
Wafer level package and method of fabricating the same Download PDFInfo
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- KR100349362B1 KR100349362B1 KR1020000037132A KR20000037132A KR100349362B1 KR 100349362 B1 KR100349362 B1 KR 100349362B1 KR 1020000037132 A KR1020000037132 A KR 1020000037132A KR 20000037132 A KR20000037132 A KR 20000037132A KR 100349362 B1 KR100349362 B1 KR 100349362B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
본 발명은 웨이퍼 레벨 패키지 및 그의 제조 방법을 개시한다. 개시된 본 발명은, 반도체 칩의 본드 패드에 금속 와이어의 일단이 본딩되고, 그의 타단은 고리 형상으로 연장되어 본드 패드가 배치된 면을 향한다. 반도체 칩의 본드 패드 주위 영역에 봉지제가 도포되어, 금속 와이어의 양단이 봉지제에 내장되고 고리부만이 봉지제로부터 노출된다. 봉지제에 솔더 볼이 마운트되어, 금속 와이어의 고리부가 솔더 볼에 내장된다.The present invention discloses a wafer level package and its manufacturing method. In the disclosed invention, one end of a metal wire is bonded to a bond pad of a semiconductor chip, and the other end thereof extends in a ring shape to face the surface where the bond pad is disposed. An encapsulant is applied to the area around the bond pad of the semiconductor chip so that both ends of the metal wire are embedded in the encapsulant and only the ring portion is exposed from the encapsulant. The solder ball is mounted on the encapsulant so that the hook portion of the metal wire is embedded in the solder ball.
Description
본 발명은 웨이퍼 레벨 패키지 및 그의 제조 방법에 관한 것으로서, 보다 구체적으로는 웨이퍼 상태에서 각종 패키징 공정이 실시되는 웨이퍼 레벨 패키지 및이를 제조하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer level package and a method of manufacturing the same, and more particularly, to a wafer level package and a method of manufacturing the same, in which various packaging processes are performed in a wafer state.
기존의 일반적인 패키지는 웨이퍼를 먼저 스크라이브 라인을 따라 절단하여 개개의 반도체 칩으로 분리한 후, 개개의 반도체 칩별로 여러 가지 패키징 공정을 실시하는 것에 의해 제조되었다.Existing general packages were manufactured by first cutting a wafer along a scribe line, separating the wafer into individual semiconductor chips, and then performing various packaging processes for each semiconductor chip.
그러나, 상기된 기존의 패키지는 개개의 반도체 칩별로 많은 단위 공정이 실시되어야 하기 때문에, 하나의 웨이퍼에서 제조되는 반도체 칩들을 고려하게 되면, 공정수가 너무 많다는 문제점을 안고 있다.However, since the conventional package described above requires many unit processes to be performed for each semiconductor chip, considering the semiconductor chips manufactured from one wafer, there is a problem that the number of processes is too large.
그래서, 최근에는 웨이퍼를 먼저 절단하지 않고 웨이퍼 상태에서 상기된 패키징 공정을 우선적으로 실시한 후, 최종적으로 스크라이브 라인을 따라 절단하여 패키지를 제조하는 방안이 제시되었다. 이러한 방법으로 제조된 패키지를 웨이퍼 레벨 패키지라 하는데, 이러한 웨이퍼 레벨 패키지를 제조하는 종래 방법을 도 1 내지 도 5를 참고로 하여 설명하면 다음과 같다.Therefore, in recent years, a method of manufacturing a package by first performing the above-described packaging process in a wafer state without cutting the wafer first and finally cutting along the scribe line has been proposed. A package manufactured by this method is called a wafer level package. A conventional method of manufacturing such a wafer level package will be described below with reference to FIGS. 1 to 5.
먼저, 도 1에 도시된 바와 같이, 금속 트레이스를 갖는 회로 기판(3)상에 복수개의 반도체 칩(1)을 접착한다. 그런 다음, 각 반도체 칩(10)의 본드 패드와 회로 기판(3)의 표면을 통해 노출된 금속 트레이스 부분을 금속 와이어(2)로 전기적으로 연결시킨다.First, as shown in FIG. 1, a plurality of semiconductor chips 1 are bonded onto a circuit board 3 having a metal trace. Then, the bond pad of each semiconductor chip 10 and the exposed metal trace portion through the surface of the circuit board 3 are electrically connected to the metal wire 2.
이어서, 도 2에 도시된 바와 같이, 회로 기판(3)의 상부 영역을 봉지제(4)로 봉지하여, 와이어 본딩 영역을 외부 충격으로부터 보호한다. 이어서, 도 3에 도시된 바와 같이, 회로 기판(3)의 밑면을 통해 노출된 금속 트레이스 부분, 즉 볼 랜드(6)에 솔더 볼(5)을 마운트한다.Then, as shown in FIG. 2, the upper region of the circuit board 3 is sealed with the encapsulant 4 to protect the wire bonding region from external impact. Subsequently, as shown in FIG. 3, the solder balls 5 are mounted on the metal trace portions exposed through the bottom surface of the circuit board 3, that is, the ball lands 6.
마지막으로, 도 4에 도시된 바와 같이 스크라이브 레인을 따라 봉지제(4) 부분을 절단하여 개개의 반도체 칩(1)으로 분리하면, 도 5에 도시된 웨이퍼 레벨 패키지가 완성된다.Finally, as shown in FIG. 4, the portion of the encapsulant 4 is cut along the scribe lane and separated into individual semiconductor chips 1, thereby completing the wafer level package shown in FIG.
그런데, 종래의 웨이퍼 레벨 패키지는 별도의 회로 기판이 사용되므로, 우선 제조 비용이 상승하고 공정이 복잡해지는 문제점이 있다.However, since the conventional wafer level package uses a separate circuit board, there is a problem that the manufacturing cost increases first and the process becomes complicated.
또한, 회로 기판의 상부 영역이 봉지제로 봉지되므로, 이 봉지제로 인해 패키지의 크기가 너무 커진다는 단점도 있다.In addition, since the upper region of the circuit board is encapsulated with an encapsulant, the encapsulant also has a disadvantage in that the size of the package becomes too large.
특히, 웨이퍼 레벨 패키지에서 가장 문제시되는 솔더 볼의 접합 강도가 여전히 취약하다. 그 이유는 솔더 볼이 평면 구조인 볼 랜드와 접촉하기 때문에, 접촉 면적이 너무 좁은 것에 기인하다.In particular, the bond strength of the solder balls, which is the most problematic in wafer level packages, is still weak. The reason is that the solder ball is in contact with the ball land having a planar structure, and the contact area is too narrow.
따라서, 본 발명은 종래의 웨이퍼 레벨 패키지가 안고 있는 문제점을 해소하기 위해 안출된 것으로서, 별도의 기판 사용을 배제하고, 크기를 반도체 칩 크기 정도로 구현할 수 있으며, 아울러 솔더 볼의 접합 강도도 강화시킬 수 있는 웨이퍼 레벨 패키지 및 그의 제조 방법을 제공하는데 목적이 있다.Accordingly, the present invention has been made to solve the problems of the conventional wafer-level package, eliminates the use of a separate substrate, can be implemented as the size of a semiconductor chip, and can also enhance the bonding strength of the solder ball. It is an object of the present invention to provide a wafer level package and a manufacturing method thereof.
도 1 내지 도 5는 종래의 웨이퍼 레벨 패키지를 제조 공정 순서대로 나타낸 단면도.1 to 5 are cross-sectional views showing conventional wafer level packages in the order of manufacturing process.
도 6 내지 도 11은 본 발명에 따른 웨이퍼 레벨 패키지를 제조 공정 순서대로 나타낸 단면도.6-11 are cross-sectional views of wafer level packages in accordance with the present invention in the order of manufacturing process.
- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-
10 ; 웨이퍼 11 ; 본드 패드10; Wafer 11; Bond pad
12 ; 더미 패드 13 ; 스크라이브 레인12; Dummy pad 13; Scribe lane
20 ; 지지판 30 ; 금속 와이어20; Support plate 30; Metal wire
31 ; 금속막 40 ; 봉지제31; Metal film 40; Encapsulant
50 ; 솔더 볼50; Solder ball
상기와 같은 목적을 달성하기 위하여, 본 발명에 따른 웨이퍼 레벨 패키지는 다음과 같은 구성으로 이루어진다.In order to achieve the above object, the wafer level package according to the present invention has the following configuration.
반도체 칩의 본드 패드에 금속 와이어의 일단이 본딩되고, 그의 타단은 고리 형상으로 연장되어 본드 패드가 배치된 면을 향한다. 반도체 칩의 본드 패드 주위영역에 봉지제가 도포되어, 금속 와이어의 양단이 봉지제에 내장되고 고리부만이 봉지제로부터 노출된다. 봉지제에 솔더 볼이 마운트되어, 금속 와이어의 고리부가 솔더 볼에 내장된다.One end of the metal wire is bonded to the bond pad of the semiconductor chip, and the other end thereof extends in a ring shape to face the surface where the bond pad is disposed. An encapsulant is applied to the area around the bond pad of the semiconductor chip so that both ends of the metal wire are embedded in the encapsulant and only the ring portion is exposed from the encapsulant. The solder ball is mounted on the encapsulant so that the hook portion of the metal wire is embedded in the solder ball.
상기된 구성으로 이루어진 웨이퍼 레벨 패키지를 제조하는 방법은 다음과 같은 단계로 이루어진다.The method of manufacturing a wafer level package having the above-described configuration consists of the following steps.
복수개의 반도체 칩이 구성된 웨이퍼를 지지판상에 접착한다. 반도체 칩의 본드 패드들은 반도체 칩의 외곽에 배치되어 있다. 웨이퍼에 형성된 스크라이브 레인상에 더미 패드를 형성한다. 더미 패드와 본드 패드를 금속 와이어로 연결한다. 금속 와이어의 강도 보강을 위해 금속막을 금속 와이어에 도금한다. 금속 와이어의 고리 형상인 중간부만이 노출되도록, 더미 패드와 본드 패드를 덮는 봉지제를 웨이퍼 표면에 국부적으로 형성한다. 스크라이브 레인을 따라 웨이퍼를 절단하여 개개의 반도체 칩으로 분리한 후, 봉지제에 솔더 볼을 마운트하여, 솔더 볼내에 금속 와이어의 고리부가 내장되도록 한다.A wafer composed of a plurality of semiconductor chips is bonded onto a support plate. Bond pads of the semiconductor chip are disposed outside the semiconductor chip. A dummy pad is formed on the scribe lane formed on the wafer. Connect the dummy pad and the bond pad with a metal wire. The metal film is plated on the metal wire to reinforce the strength of the metal wire. An encapsulant covering the dummy pad and the bond pad is locally formed on the wafer surface so that only the annular intermediate portion of the metal wire is exposed. The wafer is cut along the scribe lane and separated into individual semiconductor chips, and then solder balls are mounted in the encapsulant so that the ring portions of the metal wires are embedded in the solder balls.
상기된 본 발명의 구성에 의하면, 금속 와이어의 고리부만이 봉지제로부터 노출되어, 이 고리부가 솔더 볼에 내장되므로써, 별도의 회로 기판 사용이 배제되고, 특히 솔더 볼에 금속 와이어의 고리부가 내장되어 솔더 볼의 지지 강도가 대폭 강화된다.According to the above-described configuration of the present invention, only the hook portion of the metal wire is exposed from the encapsulant, and since the hook portion is embedded in the solder ball, the use of a separate circuit board is eliminated, and in particular, the hook portion of the metal wire is embedded in the solder ball. As a result, the support strength of the solder ball is greatly enhanced.
이하, 본 발명의 바람직한 실시예를 첨부도면에 의거하여 설명한다.Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described based on the accompanying drawings.
도 6 내지 도 11은 본 발명에 따른 웨이퍼 레벨 패키지를 제조 공정 순서대로 나타낸 단면도이다.6 through 11 are cross-sectional views illustrating wafer level packages according to the present invention in the order of manufacturing process.
먼저, 도 6에 도시된 바와 같이, 웨이퍼(10)에는 복수개의 반도체 칩이 구성되어 있고, 각 반도체 칩의 본드 패드(11)는 반도체 칩의 외곽에 배치되어 있다. 이러한 웨이퍼(10)를 지지판(20)상에 접착한 후, 각 반도체 칩을 구획하는 웨이퍼(10)의 스크라이브 레인(13)상에 더미 패드(12)를 형성한다. 그런 다음, 금속 와이어(30)를 사용해서 더미 패드(12)와 본드 패드(11)를 전기적으로 연결시킨다.First, as shown in FIG. 6, a plurality of semiconductor chips are formed on the wafer 10, and the bond pads 11 of each semiconductor chip are arranged outside the semiconductor chip. After the wafer 10 is adhered to the support plate 20, a dummy pad 12 is formed on the scribe lane 13 of the wafer 10 partitioning each semiconductor chip. Then, the metal pad 30 is used to electrically connect the dummy pad 12 and the bond pad 11.
이어서, 도 7과 같이 금속 와이어(30)의 강도 보강을 위해, 금속막(31)을 금속 와이어에 도금한다. 금속막(31)의 재질로는 구리/니켈 합금인 것이 바람직하다.Subsequently, the metal film 31 is plated on the metal wire to reinforce the strength of the metal wire 30 as shown in FIG. 7. The material of the metal film 31 is preferably copper / nickel alloy.
그런 다음, 본드 패드(11)와 더미 패드(12)를 덮어서 노출시키지 않는 봉지제(40)를 웨이퍼(10) 표면에 국부적으로 형성하는데, 특히 금속막(31)이 도금된 금속 와이어의 중간부, 즉 고리 형상을 갖는 부분만이 노출될 정도로 얇게 형성한다.Then, an encapsulant 40 is formed locally on the surface of the wafer 10, which covers the bond pad 11 and the dummy pad 12 so as not to be exposed. In particular, an intermediate portion of the metal wire plated with the metal film 31 is formed. That is, it is formed so thin that only the portion having an annular shape is exposed.
이어서, 도 9에 도시된 바와 같이, 블레이드를 사용해서 웨이퍼(10)를 스크라이브 레인(13)을 따라 절단한 후 지지판(20)을 웨이퍼(10)로부터 분리하면, 도 10에 도시된 바와 같이 웨이퍼(10)가 개개의 반도체 칩으로 분리된다. 도 10에 도시된 패키지는 금속막(31)이 도금된 금속 와이어의 고리부만이 봉지제(40)로부터 노출된 구조를 갖고 있다.Subsequently, as shown in FIG. 9, when the wafer 10 is cut along the scribe lane 13 using a blade, and then the support plate 20 is separated from the wafer 10, the wafer as shown in FIG. 10. 10 is separated into individual semiconductor chips. The package shown in FIG. 10 has a structure in which only the ring portion of the metal wire plated with the metal film 31 is exposed from the encapsulant 40.
따라서, 솔더 볼(50)을 봉지제(40)상에 마운트하면, 금속 와이어의 고리부가 솔더 볼(50)에 내장되므로, 솔더 볼(50)을 지지하는 강도가 대폭 강화된다. 이러한 솔더 볼(50)을 도 11에 도시된 바와 같이, 보드(60)에 실장하면, 솔더 볼(50)에 크랙이 발생되는 현상이 대폭 억제된다. 특히, 솔더 볼(50)과 금속 와이어는 종래와같이 면대면이 접촉하는 방식이 아니라, 와이어가 솔더 볼(50)에 내장되는 방식이므로, 접합력이 종래보다 강화될 수가 있다.Therefore, when the solder ball 50 is mounted on the sealing agent 40, since the ring part of the metal wire is embedded in the solder ball 50, the strength which supports the solder ball 50 is greatly strengthened. As shown in FIG. 11, when the solder ball 50 is mounted on the board 60, the phenomenon in which the crack occurs in the solder ball 50 is greatly suppressed. In particular, the solder ball 50 and the metal wire are not a method in which the face-to-face contact as in the prior art, but a method in which the wire is embedded in the solder ball 50, and thus, the bonding force may be enhanced.
이상에서 설명한 바와 같이 본 발명에 의하면, 금속 와이어가 솔더 볼에 내장되므로써, 솔더 볼의 접합 강도가 대폭 강화되어 솔더 볼에 크랙이 발생되는 현상이 억제된다.As described above, according to the present invention, since the metal wire is embedded in the solder ball, the bonding strength of the solder ball is greatly enhanced, and the phenomenon in which the crack occurs in the solder ball is suppressed.
또한, 종래와 같이 별도의 회로 기판 사용이 배제되므로, 제조 비용이 절감되고 공정수도 줄어드는 잇점이 있다.In addition, since the use of a separate circuit board is eliminated as in the prior art, manufacturing cost is reduced and the number of processes is also reduced.
특히, 패키지의 크기가 반도체 칩 크기 정도로 작게 구현될 수가 있다.In particular, the size of the package can be implemented as small as the size of a semiconductor chip.
이상에서는 본 발명의 바람직한 실시예에 대하여 도시하고 또한 설명하였으나, 본 발명은 상기한 실시예에 한정되지 않고, 이하 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진자라면 누구든지 다양한 변경 실시가 가능할 것이다.Although the preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the above-described embodiments, and the present invention is not limited to the above-described claims, and the present invention is not limited to the scope of the present invention. Anyone with knowledge will be able to make various changes.
Claims (7)
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