KR20010066161A - Apparatus for dual link - Google Patents

Abstract

PURPOSE: An apparatus for diagnosing duplicated links is provided to simply confirm the abnormality of duplicated links in active and standby states. CONSTITUTION: An A-link abnormality detection apparatus is comprised of an abnormal mode setup circuit(120), a bit pattern generation circuit(130), a comparison circuit(140), and an interrupt generation circuit(150). The abnormal mode setup circuit(120) contains a mode register(121) and a timer(123). The timer(122) provides a cycle signal to the mode register(121). The mode register(121) provides an A-loop signal to a loop circuit when an interrupt bit and a selective bit are enabled. The bit pattern generation circuit(130) is composed of a bit pattern generator(131), a shift register(132) and a multiplexer(MUX11). The bit pattern generator(131) receives and stores a bit pattern provided from a CPU and provides it to the shift register(132). The shift register(132) provides the bit pattern to the multiplexer(MUX11) sequentially, corresponding to a transmitting clock(TxC). The multiplexer(MUX11) selectively outputs either the bit pattern of the shift register(132) or output data(TxD(A)) according to the control of the CPU. The comparison circuit(140) is composed of a multiplexer(MUX12), a shift register(141) and a comparator(142). The multiplexer(MUX12) selects the data provided from a link or the data provided from the multiplexer(MUX11) and provides the selected data to the shift register(141). The shift register(141) synchronizes the data of the multiplexer(MUX12) with a receiving clock(RxC) and supplies the data to the comparator(142). The comparator(142) compares the data of the shift register(141) and the data of the bit pattern generator(131) and provides a normal(or abnormal) indication signal to the interrupt generation circuit(150). The interrupt generation circuit(150) is comprised of a status register(151) and an interrupt request part(152). The status register(151) stores the normal(or abnormal) indication signal and provides the stored signal to the interrupt request part(152) and the CPU. The interrupt request part(152) supplies an interrupt signal to the CPU if the cycle signal from the timer(122) and the normal(or abnormal) indication signal from the status register(151) are supplied.

Description

Redundant Link Diagnostic Device {APPARATUS FOR DUAL LINK}

The present invention relates to an electronic switch, and more particularly, to an apparatus capable of diagnosing an abnormal link in an active / standby state in a redundant link.

The electronic switchgear is configured in a distributed control form to perform a switching function, and performs tasks while communicating with each other between processor systems performing a unique function. Accordingly, there is a high speed real-time hardware module inside the switch that allows messages to be delivered to a corresponding address for interprocessor communication, and the processors are matched with the module to perform interprocessor communication.

The internal structure of these exchanges is redundant with each processor and matching circuit for reliability. 1 illustrates a configuration in which a redundant processor block is matched for interprocessor communication.

As shown, two output lines Tx (A) and Tx (B) and two input lines Rx (A) and Rx (B) are connected to one processor block. These lines Tx (A), Tx (B), (Rx (A), Rx (B)) are connected to the serial input / output circuit 1 via the buffers B1-B4, and the serial input / output circuit 1 Are connected to the central processing unit 2 and the memory 3. The transmission data from the central processing unit 2 is output to the output lines Tx (A) and Tx (B) via the buffers B1 and B2 via the serial input / output circuit 1 and the input lines Rx (A ), The data from Rx (B) is provided to the serial input / output circuit 1 via the buffers B3 and B4 and the multiplexer MUX1 and to the memory 3 via the serial input / output circuit 1. That is, data output from the processor block is output in two lines Tx (A) and Tx (B), and the processor block inputs data through two lines Rx (A) and Rx (B). .

2 illustrates a state in which the above-described processor block is duplexed and connected to the routing module 10, that is, a module for mediating communication. As shown, a plurality of matching circuits M1 -Mn are connected to the routing module 10, and redundant matching processor blocks P11 and P12 are connected to the matching circuits M1 -Mn. The processor blocks P11 and P12 have the same configuration as the processor block of FIG. 1 and are connected to the matching circuits M1-Mn. Hereinafter, the relationship between the processor blocks P11 and P12 connected to the matching circuit M1 will be described. However, the matching circuits M2-Mn also have the same relationship as the processor block (not shown). One of ordinary skill will readily know.

As shown, the matching circuit M1 includes two matching parts 21 and 22, and the matching parts 21 and 22 are cross-connected with the processor blocks P11 and P12. Here, the link AA means that the lines Tx (A) and Rx (A) are combined, and the link BA means that the lines Tx (B) and Rx (B) are combined. do. In other words, the processor block P11 is connected to the matching unit 21 or 22 through the link AA / or BA to communicate with the routing module 10, but is in communication with the link AA / or BA during communication. If an abnormality occurs, communication with the routing module 10 can be continued by switching the communication link to (BA) / or (AA).

In the same manner, the processor block P12 is connected to the matching units 21 and 22 through a link AB / or BB to communicate with the routing module 10. Here, the link AB means that the lines Tx (A) and Rx (A) are combined, and the link BB means that the lines Tx (B) and Rx (B) are combined. The processor block P12 routes the communication link to (BB) / or (AB) when an error occurs in the link (AB) / or (BB) during communication via the link (AB) / or (BB). Communication with module 10 may continue.

Here, since the processor blocks P11 and P12 are redundantly configured through the matching units 21 and 22, it can be seen that the processor blocks P11 and P12 are capable of mutually redundant switching. That is, the processor blocks P111 and P12 may be selectively driven in active / standby mode. Therefore, the links AA, AB, BA, and BB connected to the processor blocks P11 and P12 are in the active state among the processor blocks P11 and P12 and in the active state among the active processor blocks. Data communication is performed only on a link connected to the processor block (hereinafter referred to as an activation link), and data communication is not performed through the remaining links except the activation link. Since data communication is performed only through the activated link, the processor blocks P11 and P12 may determine whether the activated link is normally operated. That is, it is possible to determine whether the link is normally operated by using an error of data received through the activated link. In the event that an active link (eg AA) is in abnormal operation, the active processor block (eg P11) activates the inactive link BA of its own links and the data through the activated link BA. Communication continues, and in this case, when the link BA is abnormally operated, the processor block P12 in the standby state is switched to the active state to communicate with the routing module 10 through another link (for example, BA). Will continue.

As can be seen from the above description, in a conventional redundant link, an active state, that is, an active state link, may determine whether the link is abnormal as an error of data being communicated, but the inactive link may determine whether the link is abnormal. There is no way to judge. Therefore, as a result of activating another link due to an abnormal link during communication through an active link, if another link malfunctions, the other link must be activated again. Therefore, the link switching operation and the active / standby switching operation of the processor module are continuously performed. There is a problem that it may occur, and this may cause the whole system to be down.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide an apparatus capable of simply checking whether an active / standby link is abnormal in links of a redundant configuration.

In order to achieve the above object, the present invention provides a redundant link diagnosis apparatus comprising a first processor and a second processor block, which are redundantly configured through a routing module and first and second links, and having a central processing unit communicating with the routing module. A method comprising: connecting between a routing module and a first and a second link to match data transmission and reception between the routing module and the first and second processor blocks, and through the first and second links in accordance with a loop signal. A matching circuit having a loop circuit for returning a signal provided from the processor block to the first and second processor blocks; A first link abnormality detecting device for monitoring an abnormality of a first link and a second link abnormality detecting device for monitoring an abnormality of a second link are respectively configured in the first and second processor blocks. The link abnormality detection apparatus provides a transmission / reception path of data between the central processing unit and the first and second links under the control of the central processing unit, and generates a predetermined bit pattern under the control of the central processing unit to generate the first and second links. And provide the loop signal to the loop circuit and compare the feedback bit pattern with the generated bit pattern to detect an abnormality of the first and second links and provide it to the central processing unit.

1 is a block diagram of a conventional processor block having a redundant link,

2 is a diagram illustrating a state in which a processor block is duplicated in a routing module;

3 is a schematic block diagram of a redundant link diagnosis apparatus according to the present invention;

4 is a conceptual diagram of a loop circuit configured in the redundant link diagnosis apparatus according to the present invention;

5 is a detailed block diagram of a link failure detection apparatus in a redundant link diagnostic apparatus according to the present invention;

FIG. 6 is a diagram showing an example of bit contents stored in a mode register in a redundant link diagnosis apparatus according to the present invention; FIG.

<Description of the symbols for the main parts of the drawings>

120: abnormal mode setting circuit 121: mode register

122: timer 130: bit pattern generation circuit

131: bit pattern generator 132: shift register

140: comparison circuit 141: shift register

142: comparator 150: interrupt generation circuit

151: status register 152: interrupt request unit

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a schematic block diagram of a processor block 100 in accordance with the present invention. As shown in the figure, the processor block 100 of the present invention includes a central processing unit 101, a serial input / output circuit 102, a memory 103, and buffers B1-B4 as in the prior art. Between the circuit 102 and the buffers B1-B4, the link failure detection device 104 of the present invention is configured. The link failure detection device 104 is composed of an A link failure detection device 105 and a B link failure detection device 106 as shown.

The A / B link fault detection apparatuses 105 and 106 receive an address, data and a control signal from the central processing unit 101 and operate in the fault detection mode / normal mode as described later. In the normal mode, the A / B link abnormality detection device 105, 106 normally provides data from the central processing unit 101 to the buffers B1, B2, and buffers B3, B4. Data stored in the serial input / output circuit 102, but in the abnormality detection mode, the A / B link abnormality detection devices 105 and 106 generate and output predetermined bit pattern information and A / B loop signals. do. The bit pattern information is fed back through the matching unit (any one of M1-Mn in FIG. 2) and provided to the A / B link abnormality detecting apparatuses 105 and 106 again, and the A / B link abnormality detecting apparatus 105 is provided. ) And 106 may compare the feedback bit pattern with the transmitted bit pattern and provide the central processing unit 101 with an abnormal state of the link if they are different from each other. Here, as described above, the link abnormality detecting apparatuses 105 and 106 are configured for each of the links A and B, and the A link abnormality detecting apparatus 105 includes data about the link A (TxD (A)). , RxD (A)) transmits and receives, and generates and compares bit pattern information, and selectively outputs only the A loop signal. It will be readily understood from the following description that the B link abnormality detection device 106 provides a link. Transmitting and receiving data (TxD (B), RxD (B)) and generating and comparing bit pattern information for (B), and selectively outputting only the B loop signal will be easily understood from the following description.

The A / B link abnormality detection apparatuses 105 and 106 perform generation and comparison of the bit pattern information with a predetermined period according to the control from the central processing unit 101, and when the predetermined period is reached, that is, when the bit pattern information occurs In the following, a predetermined interrupt signal is provided to the CPU 101 so that the CPU 101 temporarily suspends the data transmission, that is, the data transmission to the routing module.

In the above description, it has been described that the abnormality detecting device 104 can detect whether the link A or B is abnormal in the abnormal detection mode as a bit pattern, but the abnormality detection mode is the link A and B as described above. It can also be operated in the link abnormality detection mode for detecting the abnormality of the board) and the in-board abnormality detection mode in which the abnormality of the board of the abnormality detection device 104 can be determined. .

The A / B loop signal is provided to the matching unit 200 (corresponding to M1-Mn in FIG. 3) as shown in FIG. 4, and the loop circuit 211 is configured as shown in the matching unit 200. . The loop circuit 211 serves to return data inputted through the lines TA and TB back to the output lines RA and RB as shown by a dotted line. When the A loop signal is provided, the A line is provided. Only the data of TTA (TxD (A)) is fed back (RxD (A)), and if the B loop signal is provided, the data of the B line (TB) (TxD (B)) is fed back (RxD (B)). Consists of.

When the A / B loop signal is not provided, the loop circuit 211 receives the data provided through the lines TA and TB and provides the received data to the routing module through the first-in first-out buffer 212 for transmission. Data of the routing module provided through the selection buffer 213 is received and provided to the abnormality detection device 104 through the lines RA and RB.

FIG. 5 shows a detailed block diagram of the A link failure detection device 105 among the above-described A / B link failure detection devices 105 and 106. As illustrated, the A-link abnormality detecting device 105 includes an abnormal mode setting circuit 120, a bit pattern generating circuit 130, a comparing circuit 140, and an interrupt generating circuit 150. The central processing unit 101 provides the link abnormality detecting device 105 with an address, data, and a control signal through the control bus as shown in FIG. 3 to control the operation of the A link abnormality detecting device 105. . Here, the address signal is for designating the components in the link abnormality detecting apparatus 105, and the data means the data necessary for the operation of the bit pattern or the link abnormality detecting apparatus 105 described above, and the control signal is the link abnormality detecting. It will be readily apparent from the following description that the purpose is to control the storage / reading of data in components within the device 105.

The abnormal mode setting circuit 120 in the link abnormality detecting apparatus 105 is composed of a mode register 121 and a timer 123, and the mode register 121 is a link for returning a bit pattern as shown in FIG. (A) bit (b1) for selection, bit (b2) for selecting link (B), bit (b3) for selecting board 105, bit (b4) for selecting board 106, bit (b5) for timer, and Interrupt bits b6 are configured, and these bits b1-b6 are selectively enabled by data of the central processing unit 101. That is, bit b1 enabled means that link A is selected, bit b2 enabled means that link B is selected, and bit b3 enabled is the board 105. That is, the A-link anomaly detection device is selected, and that bit b4 is enabled means that the board 106, that is, the B-link anomaly detection device, is selected. In addition, enabling bit b5 means enabling the timer 122, and enabling bit b6 means performing an abnormal detection mode.

In addition, a period signal is provided to the mode register 121 from the timer 122, and the mode register 121 is A when the interrupt bit b6 is enabled and the bit b1 is enabled. The loop signal is provided to the loop circuit 211 of FIG.

The timer 122 operates when the timer bit b5 of the mode register 121 is enabled, and its count value is provided by the central processing unit 101. The timer 122 provides the period register 121 and the interrupt request unit 152 of the interrupt generating circuit 150 when the internal clock is counted up to the count value of the central processing unit 101, indicating that the cycle has ended. .

Bit pattern generator circuit 130 is composed of a bit pattern generator 131, a shift register 132 and a multiplexer (MUX11), the bit pattern generator 131 stores a bit pattern from the central processing unit 101, This is provided to the shift register 132.

The shift register 132 sequentially provides the bit pattern to the multiplexer MUX11 in response to the transmission clock TxC, and outputs the data TxD (A) of the serial input / output circuit 102 to the other end of the multiplexer MUX11. ) Is provided. The multiplexer MUX11 selects and outputs one of these signals, that is, the bit pattern of the shift register 132 or the output data TxD (A) under the control from the central processing unit 101. Output data from the multiplexer MUX11 is provided to the link TA and comparison circuit 140.

The comparison circuit 140 is composed of a multiplexer MUX12, a shift register 141, and a comparator 142. The multiplexer MUX12 centrally processes data provided from the link RA or data provided from the multiplexer MUX11. Selected under control of the device 101 and provided to the shift register 141. The shift register 141 provides the data from the multiplexer MUX12 to the comparator 142 in synchronization with the reception clock RxC. The comparator 142 is provided with data from the shift register 141 and the bit pattern generator 131, and the comparator 142 compares the data from these two blocks to indicate whether they are the same, i.e., an abnormal / normal signal. To the interrupt generation circuit 150.

The interrupt generating circuit 150 includes a status register 151 and an interrupt requesting unit 152. The status register 151 stores an abnormal / normal signal of the comparator 142, and stores the stored signal in the interrupt requesting unit ( 152 and the central processing unit 101. The interrupt request unit 152 provides the interrupt signal to the central processing unit 101 when the periodic signal and the abnormal / normal status signal are provided from the timer 122.

Hereinafter, the operation of the present invention having the above-described configuration will be described in detail.

First, in the normal mode, that is, the data TxD (A) of the central processing unit 101 is transmitted to the routing module, and the data RxD (A) from the routing module is received and stored in the memory 101. The case of a mode is demonstrated.

In the normal mode, the central processing unit 101 controls the multiplexer MUX11 to provide the data TxD (A) to the loop circuit 211. At this time, since the A-link abnormality detection device 105 is in a disabled state, the A-loop signal is not provided to the loop circuit 211, so that the loop circuit 211 buffers the data TxD provided through the link TA. 212). In addition, data RxD (A) from the routing module provided through the buffer 213 is provided to the serial input / output circuit 102 through the line 143 of the link failure detection device 105.

Next, in the case of the abnormality detection mode, the abnormality detection mode can be divided into the link abnormality detection mode and the on-board abnormality detection mode as described above, and in the case of the link abnormality detection mode, the central processing unit 102 is a mode register ( The link A selection bit b1, the timer bit b5, and the interrupt bit b6 of the 121 are enabled, and a period of time required for the timer 122, that is, a period for performing the abnormal detection mode is set. The bit pattern generator 131 provides and stores a predetermined bit pattern for a test.

As the bit b5 of the mode register 121 is enabled by the above-described process, the timer 122 starts driving, and when the predetermined time set by the central processing unit 101 elapses, the cycle signal is sent to the status register 151. And the interrupt request unit 152. The interrupt request unit 152 provides the interrupt signal to the central processing unit 101 in response to the periodic signal to cause the central processing unit 101 to temporarily stop the transmission of the data TxD (A). In addition, the central processing unit 101 controls the multiplexer MUX11 to provide the output of the shift register 132 to the loop circuit 211 in response to the interrupt signal, and causes the multiplexer MUX12 to perform the loop circuit 211. Control is provided to the shift register 141.

In addition, in response to the periodic signal of the timer 122, the mode register 121 provides the A loop signal to the loop circuit 211 according to the enable state of the bit b1, so that the loop circuit 211 is disconnected from the link TA. The provided signal is fed back to the link RA to be provided to the link failure detection device 105 again.

In this case, the bit pattern generator 131 is provided with a predetermined bit pattern from the central processing unit 101, and the bit pattern generator 131 provides the provided bit pattern to the shift register 132. Since the shift register 132 provides this bit pattern to the multiplexer MUX11 in synchronization with the clock TxC, the bit pattern is provided to the multiplexer MUX12 again through the loop circuit 211. The multiplexer MUX12 sequentially provides the bit pattern to the comparator 142 under the control of the central processing unit 101. The other end of the comparator 142 is provided with a bit pattern of the bit pattern generator 131, and the comparator 142 compares the bit pattern of the shift register 141 with the bit pattern of the bit pattern generator 131 to determine whether the bit pattern is abnormal / The normal status signal is stored in the status register 151. That is, when the two compared patterns are different from each other, the abnormal signal is provided to the status register 151. However, when the two patterns are the same, the normal signal is provided to the status register 151.

The abnormal / normal status signal of the status register 151 is provided to the interrupt request unit 152, and the interrupt request unit 152 provides the interrupt signal back to the central processing unit 101 when the abnormal signal is provided. That is, the interrupt request unit 152 provides the interrupt signal to the central processing unit 101 when the periodic signal is provided from the timer 122 and when the abnormal signal is provided from the status register 151.

When such an interrupt signal is generated, the central processing unit 10 reads the information in the status register 151 to determine whether the link is in an abnormal state or an interrupt state due to a timer cycle signal. That is, when the interrupt signal is provided, the central processing unit 101 reads the information in the status register 151, and if the abnormal signal of the link is stored, the central processing unit 101 may know that an abnormality has occurred in the test result of the link. In the case where the normal signal is stored in 161, it is regarded as the interrupt state caused by the periodic signal of the timer 122, and the input of the multiplexer MUX11 is selected as the signal of the shift register 132.

As can be seen from the above description, in the link abnormality detection mode, the bit pattern from the bit pattern generator 131 is fed back through the loop circuit 211, and the returned bit pattern is the original bit pattern, that is, the bit pattern generator. It is possible to easily detect whether a link is abnormal by determining whether it matches the bit pattern of 131.

Next, referring to the on-board abnormality detection mode, the central processing unit 101 enables the board 105 selection bit b3, the timer bit b5, and the interrupt bit b6 in the mode register 121. In addition, a time required for the timer 122, that is, a cycle time to check whether there is an abnormality, is provided, and the bit pattern generator 131 provides and stores a predetermined bit pattern for a test.

As the bit b5 of the mode register 121 is enabled by the above-described process, the timer 122 starts driving, and when a predetermined time elapses, the cycle signal is sent to the status register 151 and the interrupt request unit 152. To provide. The interrupt request unit 152 provides the interrupt signal to the central processing unit 101 in response to the periodic signal so that the central processing unit 101 starts the on-board abnormality detection mode to temporarily transmit the data TxD (A). Stop. Further, the central processing unit 101 controls the multiplexer MUX11 to provide the output of the shift register 132 to the loop circuit 211 in response to the interrupt signal, and causes the multiplexer MUX12 to control the multiplexer MUX11. Control to provide data to the shift register 141.

Accordingly, the bit pattern of the shift register 141 is compared with the bit pattern of the bit pattern generator 131 through the comparator 142, and an abnormal / normal signal is provided to the status register 151. Since the abnormal / normal status signal of the status register 151 is provided to the interrupt request unit 152 as in the link fault detection mode, the interrupt request unit 152 sends an interrupt signal to the central processing unit 101. The central processing unit 101 can read the information in the status register 151 according to the interrupt signal to determine whether there is an abnormal state in the board.

As can be seen from the above description, the on-board abnormality detection mode operates in the same manner as the link abnormality mode, except that the multiplexer MUX12 provides the bit pattern of the multiplexer MUX11 to the comparator 142.

As described above, in the present invention, by configuring a link abnormality detecting apparatus capable of inspecting a link abnormality in the redundant processor blocks communicating with the routing module, it is possible to simply check whether the active and standby links are abnormal, and in particular, the link abnormality detecting apparatus. There is an effect that can be easily checked for abnormalities.

Claims (7)

10. A redundant link diagnostic apparatus comprising first and second processor blocks redundantly configured through a routing module and first and second links and having a central processing unit communicating with the routing module. Connected between the routing module and the first and second links to match data transmission and reception between the routing module and the first and second processor blocks, the first through the first and second links in accordance with a loop signal; And a matching circuit having a loop circuit for feedbacking a signal provided from a second processor block to the first and second processor blocks; A first link failure detection device configured to monitor an abnormality of the first link and a second link failure detection device configured to monitor an abnormality of the second link are respectively configured in the first and second processor blocks. The first and second link abnormality detection apparatuses provide a passage for transmitting and receiving data between the central processing unit and the first and second links according to the control of the central processing unit, and the predetermined bit pattern according to the control of the central processing unit. Generates and provides the first and second links, provides the loop signal to the loop circuit, compares the feedbacked bit pattern with the generated bit pattern, and detects whether the first and second links are abnormal. Redundant link diagnostic device configured to provide to the central processing unit. The method of claim 1, The first and second link failure detection device, The bit pattern is generated according to the control of the central processing unit, and the generated bit pattern is feedback in the first and second link abnormality detection devices, and the feedback bit pattern is compared with the generated bit pattern. And a redundant link diagnosis device configured to detect an abnormality of the first and second link failure detection devices and provide the same to the central processing unit. The method of claim 2, The first and second link failure detection device, The abnormal mode setting circuit for selectively outputting the loop signal by setting a link abnormality detection mode and an on-board abnormality detection mode every predetermined period according to the control of the central processing unit; A bit pattern generation circuit receiving the bit pattern from the central processing unit and sequentially generating the bit pattern, and outputting the bit pattern and data of the processor block through the first / second link; The data provided through the first / second link is provided to the first / second processor block, and the bit pattern of the bit pattern generation circuit is compared with the data provided through the first / second link. A comparison circuit for outputting a normal status signal; And an interrupt generating circuit for providing an interrupt signal to the central processing unit according to the abnormal / normal signal to cause the central processing unit to check the abnormal / normal signal. The circuit of claim 3, wherein the abnormal mode setting circuit comprises: A mode register for inputting and storing information of a link abnormality detection mode, an on-board abnormality detection mode, and a timer enable mode from the central processing unit; And a timer for driving according to the timer enable information of the mode register and counting the time value from the central processing unit to output the periodic signal. The circuit of claim 4, wherein the bit pattern generation circuit comprises: A bit pattern generator for continuously generating and outputting a bit pattern from the central processing unit; A first shift register configured to input and sequentially output the bit pattern of the bit pattern generator; A redundancy link diagnostic apparatus having a first multiplexer which supplies data of the processor block or bit patterns of the first shift register to the first / second link to the loop circuit under control of the central processing unit . The method of claim 5, wherein the comparison circuit, A second multiplexer for selectively outputting data of the loop circuit or an output of the first multiplexer received through the first / second link under the control of the central processing unit; A second shift register for sequentially outputting the output of the multiplexer; And a comparator for comparing an output of the bit pattern generator and the output of the second shift register to provide an abnormal / normal signal. The circuit of claim 6, wherein the interrupt generation circuit comprises: A status register for storing an abnormal / normal signal from the comparator; An interrupt request unit for providing an interrupt signal to the central processing unit according to an abnormality / normal status signal in the status register and a periodic signal of the timer; And the central processing unit is configured to detect an abnormality in a link / board by an abnormality / normality signal of the status register according to the interrupt signal, and to selectively pause transmission of output data.