KR20010065299A - Method of manufacturing a capacitor in a semiconductor device - Google Patents
Method of manufacturing a capacitor in a semiconductor device Download PDFInfo
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- KR20010065299A KR20010065299A KR1019990065172A KR19990065172A KR20010065299A KR 20010065299 A KR20010065299 A KR 20010065299A KR 1019990065172 A KR1019990065172 A KR 1019990065172A KR 19990065172 A KR19990065172 A KR 19990065172A KR 20010065299 A KR20010065299 A KR 20010065299A
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- capacitor
- film
- lower electrode
- manufacturing
- semiconductor device
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- 239000003990 capacitor Substances 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 27
- 238000004140 cleaning Methods 0.000 claims abstract description 21
- 150000004767 nitrides Chemical class 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 6
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 16
- 238000004381 surface treatment Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000005121 nitriding Methods 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 239000007788 liquid Substances 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 2
- 229910052593 corundum Inorganic materials 0.000 abstract 2
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000012495 reaction gas Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 241000252506 Characiformes Species 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Materials Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 특히 유전체막으로 알루미늄 옥사이드(Al2O3)를 사용하는 캐패시터에서 알루미늄 옥사이드를 증착하기 전에 하부전극을 세정하는 방법을 개선하여 누설 전류를 감소시킬 수 있는 반도체 소자의 캐패시터 제조방법에 관한것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and in particular, to improve a method of cleaning a lower electrode before depositing aluminum oxide in a capacitor using aluminum oxide (Al 2 O 3 ) as a dielectric film to reduce leakage current. The present invention relates to a method for manufacturing a capacitor of a semiconductor device.
일반적으로, 반도체 소자가 고집적화 및 소형화되어감에 따라 캐패시터가 차지하는 면적 또한 줄어들고 있는 추세이다. 캐패시터의 면적이 줄어들고 있음에도 불구하고 소자의 동작에 필요한 캐패시터의 정전 용량은 확보되어야 한다. 정전용량을 확보하기 위해 하부 전극을 3차원 구조로 형성하여 유효 표면적을 증대시키고 있으나, 이 방법 역시 한계에 도달하여 256M DRAM 급 이상의 고집적 반도체 소자에는 적용할 수 없는 실정이다. 정전용량을 확보하기 위한 다른 방법은 높은 유전율을 갖는 유전체를 사용하여 캐패시터를 제조하는 것이다.In general, as semiconductor devices are highly integrated and miniaturized, the area occupied by capacitors is also decreasing. Although the area of the capacitor is decreasing, the capacitance of the capacitor required for the operation of the device must be secured. In order to secure the capacitance, the lower electrode is formed in a three-dimensional structure to increase the effective surface area, but this method also reaches a limit and cannot be applied to a highly integrated semiconductor device of 256M DRAM or more. Another way to ensure capacitance is to manufacture a capacitor using a dielectric having a high dielectric constant.
최근, 캐패시터의 하부 전극 및 상부 전극을 폴리실리콘을 사용하면서 캐패시터 형성 후 800℃ 이상의 열공정에서도 캐패시터의 특성이 열화되지 않는 장점이 있고, 유전상수값이 8 내지 15 정도로 높은 Al2O3를 이용하여 캐패시터를 형성하는 방법이 제시되고 있다.Recently, the lower electrode and the upper electrode of the capacitor using the polysilicon has a merit that the characteristics of the capacitor does not deteriorate even in the thermal process of 800 ℃ or more after the formation of the capacitor, the dielectric constant value of about 8 to 15 using Al 2 O 3 To form a capacitor is proposed.
기존의 Al2O3캐패시터 제조방법은 기판상에 하부 전극을 형성한 후 자연산화막을 제거하기 위하여 HF 세정액을 이용하여 제거하고, 800 내지 850℃ 의 온도에서 급속 질화 열처리(RTN)로 하부전극 상부면에 질화막을 형성한 후 Al2O3유전체막을 형성하고, Al2O3유전체막 상에 상부전극을 형성하여 캐패시터를 완성한다.In the conventional Al 2 O 3 capacitor manufacturing method, the lower electrode is formed on a substrate and then removed using an HF cleaning solution to remove the natural oxide layer, and the upper electrode is lowered by rapid nitriding heat treatment (RTN) at a temperature of 800 to 850 ° C. After the nitride film is formed on the surface, an Al 2 O 3 dielectric film is formed, and an upper electrode is formed on the Al 2 O 3 dielectric film to complete the capacitor.
상기에서, 종래 하부 전극에 형성되는 자연산화막을 HF 세정액을 이용하여 제거하면 누설전류 특성이 열악해지는 문제점있다.In the above, when the natural oxide film formed on the conventional lower electrode is removed using the HF cleaning solution, the leakage current characteristics are poor.
따라서, 본 발명은 캐패시터의 누설전류를 감소시킬 수 있는 새로운 세정방법으로 누설전류 특성을 향상시킬 수 있는 반도체 소자의 캐패시터 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device capable of improving leakage current characteristics as a new cleaning method capable of reducing leakage current of a capacitor.
상기한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 캐패시터 제조방법은 하부 전극이 형성된 반도체 기판이 제공되는 단계; 표면 처리를 통해 상기 하부전극 상부면에 산화막을 형성시키는 단계; 상기 산화막 상부면에 질화막을 형성시키는 단계; 및 상기 질화막을 포함한 전체 상부면에 유전체막인 Al2O3막을 증착한 후 상부전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method including: providing a semiconductor substrate on which a lower electrode is formed; Forming an oxide film on an upper surface of the lower electrode through surface treatment; Forming a nitride film on the upper surface of the oxide film; And forming an upper electrode after depositing an Al 2 O 3 film, which is a dielectric film, on the entire upper surface including the nitride film.
도 1a 내지 도 1e는 본 발명에 따른 반도체 소자의 캐패시터 제조방법을 설명하기 위한 소자의 단면도.1A to 1E are cross-sectional views of a device for explaining a method of manufacturing a capacitor of a semiconductor device according to the present invention.
도 2는 본 발명에 따른 세정방법을 실시한 후의 전기적 특성을 나타낸 그래프로.Figure 2 is a graph showing the electrical properties after the cleaning method according to the present invention.
〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>
1 : 반도체 기판 2 : 접합부1 semiconductor substrate 2 junction
3 : 절연막 4 : 콘택 홀3: insulating film 4: contact hole
5 : 하부전극 6 : 산화막5: lower electrode 6: oxide film
7 : 질화막 8 : Al2O3막7: nitride film 8: Al 2 O 3 film
9 : 상부전극9: upper electrode
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1e는 본 발명에 따른 반도체 소자의 캐패시터 제조방법을 설명하기 위한 소자의 단면도이다.1A to 1E are cross-sectional views of devices for explaining a capacitor manufacturing method of a semiconductor device according to the present invention.
도 1a를 참조하면, 반도체 기판(1) 상에 접합부(2) 및 절연막(3)을 순차적으로 형성한 후 접합부(2)가 노출되도록 콘택 홀(4)을 형성한다.Referring to FIG. 1A, after the junction part 2 and the insulating film 3 are sequentially formed on the semiconductor substrate 1, the contact hole 4 is formed to expose the junction part 2.
도 1b를 참조하면, 콘택 홀(4)을 포함한 전체 상부면에 접합부(2)와 연결되는 하부 전극(5)을 형성한 후, HF + SC1 세정액을 이용한 세정공정으로 하부전극(5) 표면에 얇은 산화막(6)을 형성시킨다.Referring to FIG. 1B, after forming the lower electrode 5 connected to the junction part 2 on the entire upper surface including the contact hole 4, the lower electrode 5 is formed on the surface of the lower electrode 5 by a cleaning process using HF + SC1 cleaning solution. A thin oxide film 6 is formed.
상기에서, 하부 전극(5)는 도프트 폴리실리콘으로 형성하며, 도프트 폴리실리콘 하부 전극(5)을 HF+ SC1 세정액으로 세정할 경우 하부 전극(5) 표면에 SiON의 산화막(6)이 형성된다. SiON은 도프트 폴리실리콘에 대해 일함수(Work potentail)가 높은 물질로 알려져 있다. SC1 세정액은 H2O : H2O2; NH4OH = 5 : 1 : 1 비율로 이루어 진다. 이와같이, 본 발명은 표면처리를 통해 얇은 두께의 산화막(6)을 형성하므로 하부 전극(5)과의 일함수 차이를 크게하여 누설전류 특성을 향상시킨다. 표면처리는 HF + SC1 세정공정 대신에 HF + 피란하(Piranha) 세정공정을 이용할 수 있고, 또는 RTO, RTN2O 및 RTON 등과 같은 RTP 기술을 이용하여 산화막(6)을 형성할 수 있다.In the above, the lower electrode 5 is formed of doped polysilicon, and when the doped polysilicon lower electrode 5 is cleaned with HF + SC1 cleaning solution, an oxide film 6 of SiON is formed on the lower electrode 5 surface. . SiON is known to have a high work potentail for doped polysilicon. SC1 cleaning liquid H 2 O: H 2 O 2 ; NH 4 OH = 5: 1: 1 ratio. As described above, the present invention forms a thin oxide film 6 through surface treatment, thereby increasing the difference in work function from the lower electrode 5, thereby improving leakage current characteristics. The surface treatment may use the HF + Piranha cleaning process instead of the HF + SC1 cleaning process, or the oxide film 6 may be formed using RTP techniques such as RTO, RTN 2 O and RTON.
도 1c는 산화막(6) 상부면에 질화막(7)을 형성시킨 상태의 단면도이다.FIG. 1C is a cross-sectional view of the nitride film 7 formed on the upper surface of the oxide film 6.
상기에서, 질화막(7)은 750 내지 850℃ 온도 및 NH3가스 분위기에서 급속 질화 열처리 공정으로 10 내지 20Å 두께로 형성된 Si3N4막으로 이루어진다. 질화막(7)은 후속 산소 분위기의 고온 열공정에서의 산화 저항성을 증가시키기 위해 형성한다.In the above, the nitride film 7 is made of a Si 3 N 4 film formed to a thickness of 10 to 20 kPa by a rapid nitriding heat treatment process at a temperature of 750 to 850 ℃ and NH 3 gas atmosphere. The nitride film 7 is formed to increase the oxidation resistance in the high temperature thermal process in the subsequent oxygen atmosphere.
도 1d는 전체 상부면에 유전체막인 Al2O3막(8)을 증착한 후 플라즈마공정 및 고온 열처리공정을 실시한 상태의 단면도이다.1D is a cross-sectional view of a state in which a plasma process and a high temperature heat treatment process are performed after depositing an Al 2 O 3 film 8 as a dielectric film on the entire upper surface.
상기에서, 유전체막인 Al2O3막(8)은 200 내지 450℃ 온도와 50 내지 300 mTorr 압력에서 Al 반응가스 및 O2반응가스를 번갈아 가면서 기판 표면에 노출시키는 단원자 증착법을 이용하여 40 내지 100Å 두께로 형성하다. 이때, 알루미늄(Al) 반응가스로 TMA를 사용하며, 산소(O2) 반응가스로 H2O를 사용한다. 플라즈마 공정은 Al2O3막(8) 증착시 발생한 탄소기를 제거하기 위하여 N2O 플라즈마를 이용하고, 고온 열처리공정은 Al2O3막(8)을 결정화 시켜 치밀한 막질을 얻을 수 있도록 750 내지 850℃ 온도에서 N2가스를 이용한다.In the above, the Al 2 O 3 film 8, which is a dielectric film, is formed using a monoatomic deposition method in which the Al reaction gas and the O 2 reaction gas are alternately exposed to the surface of the substrate at a temperature of 200 to 450 ° C. and a pressure of 50 to 300 mTorr. To 100 μm thick. In this case, TMA is used as an aluminum (Al) reaction gas, and H 2 O is used as an oxygen (O 2 ) reaction gas. The plasma process uses N 2 O plasma to remove the carbon group generated during the deposition of the Al 2 O 3 film (8), and the high temperature heat treatment process 750 to obtain a dense film quality by crystallizing the Al 2 O 3 film (8). N 2 gas is used at a temperature of 850 ° C.
도 1e는 유전체막인 Al2O3막(8) 상부면에 상부전극(9)을 증착한 상태의 단면도이다.FIG. 1E is a cross-sectional view of the upper electrode 9 deposited on the upper surface of the Al 2 O 3 film 8 as a dielectric film.
상기에서, 상부전극(9)은 TiN 또는 폴리실리콘/TiN으로 형성한다.In the above, the upper electrode 9 is formed of TiN or polysilicon / TiN.
도 2는 기존의 HF 전세정과 본 발명의 HF + SC1 전세정에 따른 Al2O3캐패시터의 전기적 특성을 나타낸 그래프로서, 본 발명의 HF + SC1 전세정의 경우 기존의 HF 전세정 보다 누설전류가 저하됨을 알수 있다.Figure 2 is a graph showing the electrical characteristics of the conventional HF pre-cleaning and Al 2 O 3 capacitor according to the HF + SC1 pre-cleaning of the present invention, the leakage current is lower than the conventional HF pre-cleaning of the HF + SC1 pre-cleaning of the present invention You can see.
상기한 바와같이, 본 발명은 Al2O3를 유전체막으로 이용하는 반도체 소자의 캐패시터 형성시 하부 전극 형성 후 세정공정으로 하부전극과의 일함수 차이가 큰 산화막을 형성함으로써, Al2O3캐패시터의 누설전류 특성을 향상시킬 수 있어 소자의 전기적 특성이 향상되는 효과가 있다.As described above, the present invention forms an oxide film having a large work function difference from the lower electrode in the cleaning process after forming the lower electrode when forming the capacitor of the semiconductor device using Al 2 O 3 as a dielectric film, thereby forming an Al 2 O 3 capacitor. Since leakage current characteristics can be improved, the electrical characteristics of the device can be improved.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990065172A KR20010065299A (en) | 1999-12-29 | 1999-12-29 | Method of manufacturing a capacitor in a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990065172A KR20010065299A (en) | 1999-12-29 | 1999-12-29 | Method of manufacturing a capacitor in a semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR20010065299A true KR20010065299A (en) | 2001-07-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990065172A KR20010065299A (en) | 1999-12-29 | 1999-12-29 | Method of manufacturing a capacitor in a semiconductor device |
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| Country | Link |
|---|---|
| KR (1) | KR20010065299A (en) |
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1999
- 1999-12-29 KR KR1019990065172A patent/KR20010065299A/en not_active Application Discontinuation
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