KR20010064041A - Delay line circuit of FIR filter - Google Patents

Abstract

PURPOSE: A delay line circuit is provided, minimizes the size of a delay circuit even if the number of taps at an FIR filter. CONSTITUTION: A delay line circuit is composed of a some of register(REG_1 - REG_15) and a multiplexor(22). Each of the resister of first to fifteenth(REG_1 - REG_15) stores and outputs data inputted for one cycle. Each of the resister of first to fifteenth(REG_1 - REG_15) is connected in series. The data inputted to the first resister(REG_1) is selection data(SD) outputted from the multiplexor(22). The multiplexor(22) inputs data of the fourteenth register(REG_14) connected with a filter input data(D) through feedback loop. The multiplexor(22) selects a data between the filter input data(D) and the fourteenth register(REG_14) and outputs the data to selection data(SD). The data of the register of the first to the fourteenth(REG_1 - REG_14) is shifted from the second register to the fifteenth register(REG_2 - REG_15) at each time of cycles. And, the data of the fifteenth register(REG_15) gets to be output-data(OUT) to be multiplied with filter factor.

Description

Delay line circuit of FIR filter

The present invention relates to a filter, and more particularly to a delay line circuit for storing filter input data in a finite impulse response filter (FIR filer).

Finite impulse response filters (hereinafter referred to as FIR filters) are always stable, generate linear phase output data, and are easy to implement. Due to these advantages, FIR filters are widely used in various fields of signal processing. The FIR filter is generally expressed as Equation 1 below.

Here, y [n] denotes the current filter output data, C _i denotes the filter coefficient, and d [ni] denotes the filter input data input i time ago.

Therefore, the FIR filter uses the current filter input data and the N-1 past filter input data to generate current filter output data. Therefore, a total of N filter input data are used to generate one filter output data. In general, N is called the tap number of the FIR filter. Since the FIR filter with N taps uses N-1 historical filter input data, a delay line or circular buffer structure is required to store this data.

The implementation of the delay line circuit of the conventional FIR filter is divided into a method using a register and a method using a memory. The delay line circuit using the memory consists of an N depth memory and an address control stage. The filter input data is stored and retrieved using the memory access operation. However, since the delay line circuit using the memory is disadvantageous compared to the delay line circuit using the register in terms of size and operation speed, it is usually implemented by using a register.

1 is a diagram illustrating a delay line circuit using an existing register. Referring to FIG. 1, a delay line circuit using an existing register includes N serially connected registers REG_1 to REG_N and a multiplexer 12. The filter input data D is shifted and inputted every cycle in the registers REG_1 to REG_N. The multiplexer 12 receives data of each register REG_1 to REG_N, and sequentially outputs output data OUT. Therefore, the multiplexer 12 is an Nx1 multiplexer which selects and outputs one of N pieces of data.

Therefore, in the delay line circuit using the conventional register, as the number of taps N of the FIR filter increases, the size of the multiplexer increases exponentially. Therefore, there is a problem that the size of the FIR filter having the existing delay line circuit is greatly increased.

The technical problem to be achieved by the present invention is to provide a delay line circuit in which the increase in the size of the delay line circuit is minimized even if the number of taps of the FIR filter increases.

1 is a diagram showing a delay line circuit of a finite impulse response filter according to the prior art.

2 is a diagram illustrating a delay line circuit of a finite impulse response filter according to an exemplary embodiment of the present invention.

The present invention for achieving the above technical problem relates to a finite impulse response filter having a tap number N. The delay line circuit of the FIR filter according to a preferred embodiment of the present invention is a first to Nth registers for storing and outputting input data for a predetermined time, wherein the data input to the first register is predetermined selection data, and the i th (integers of i = 2 to N) Data input to the registers include the first to Nth registers which are output data of the i-th register; And a selector for selecting one of the output data and the filter input data of the N-th register and outputting the selected data.

Preferably, the selector is a multiplexer.

Even if the number of taps of the FIR filter is increased by the delay line circuit of the present invention, the increase in the size of the delay line circuit is minimized.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present specification, for the convenience of description, data performing the same role through each drawing is denoted by the same reference numeral.

2 is a diagram illustrating a delay line circuit of an FIR filter according to an exemplary embodiment of the present invention. Referring to this, the delay line circuit according to the preferred embodiment includes a plurality of registers REG_1 to REG_15 and a multiplexer 22. The delay line circuit in this embodiment is assumed to be a delay line circuit of a 15-tap FIR filter for convenience of explanation. Therefore, the delay line circuit of this embodiment is provided with fifteen registers. The fifteen registers are described as first to fifteenth registers REG_1 to REG_15.

The first to fifteenth registers REG_1 to REG_15 store and output the input data for one cycle. The first to fifteenth registers REG_1 to REG_15 are connected in series. Therefore, the data input to the i th register REG_i is the data of the i th register REG_i-1. Where i is an integer from 2 to 15. The data input to the first register REG_1 is the selection data SD which is output data of the multiplexer 22.

The multiplexer 22 receives the filter input data D and data of a fourteenth register REG_14 connected through a feedback loop. The multiplexer 22 selects one of the filter input data D and the data of the fourteenth register REG_14 and outputs the selected data SD. Therefore, the multiplexer 22 is a 2x1 multiplexer which selects and outputs one of two pieces of data. The multiplexer 22 outputs the filter input data D as the selection data SD for every 15th cycle, and outputs the data of the fourteenth register as the selection data SD in the remaining cycles. Therefore, the filter input data D is input to the first register REG_1 every 15th cycle.

The data of the first to fourteenth registers REG_1 to REG_14 are shifted to the second to fifteenth registers REG_2 to REG_15 that are the next registers every cycle. The data of the fifteenth register REG_15 becomes output data OUT to be multiplied by the filter coefficient. The output data OUT is input to an operator (not shown) and multiplied by the filter coefficients. The multiplied values are added by the number of taps to generate filter output data.

Table 1 below shows each data at every cycle in the delay line circuit of FIG.

REG_1 REG_2 REG_3 REG_4 ... REG_12 REG_13 REG_14 REG_15 OUT C y [n] D13 D12 D11 D10 ... D2 D1 D0 0 0 - D14 D13 D12 D11 ... D3 D2 D1 D0 D0 C0 y [14] D1 D14 D13 D12 ... D4 D3 D2 D1 D1 C1 D2 D1 D14 D13 ... D5 D4 D3 D2 D2 C2 ... ... ... ... D14 D13 D12 D11 ... D3 D2 D1 D14 D14 C14 D15 D14 D13 D12 ... D4 D3 D2 D1 D1 C0 y [15] D2 D15 D14 D13 ... D5 D4 D3 D2 D2 C1 D3 D2 D15 D14 ... D6 D5 D4 D3 D3 C2 ... ... D15 D14 D13 D12 ... D4 D3 D2 D15 D15 C14 D16 D15 D14 D13 ... D5 D4 D3 D2 D2 C0 y [16] D3 D16 D15 D14 ... D6 D5 D4 D3 D3 C1 D4 D3 D16 D15 ... D7 D6 D5 D4 D4 C2 ... ... D16 D15 D14 D13 ... D5 D4 D3 D16 D16 C14

Referring to Table 1, the overall operation of the delay line circuit of FIG. 2 is described as follows. For convenience of explanation, it is assumed that the filter input data D is expressed in Dn and input in series. The filter coefficients are expressed in Ci. The filter output data is represented by y [n]. Where n is an integer greater than or equal to 0 and i is an integer from 0 to 14.

First, it is assumed that the first to fourteenth registers REG_1 to REG_14 are initialized with filter input data D13 to D0, respectively. And, it is assumed that the fifteenth register is initialized to '0'. That is, 14 filter input data D are already input. Therefore, when the following filter input data D14, D15 ... are input in series, the filter output data y [14], y [15] ... is generated.

In the first cycle, the data D13 to D0 stored in the first to fourteenth registers REG_1 to REG_14 are shifted to the next second to fifteenth registers REG_2 to REG_15, respectively. The filter input data D14 and the data D0 of the fourteenth register are input to the multiplexer 22. At this time, the multiplexer 22 outputs filter input data D14 as selection data SD. Therefore, filter input data D14 is input to the first register REG_1. The data D0 of the fifteenth register REG_15 becomes the output data OUT. Therefore, the output data D0 is multiplied by the filter coefficient C0 in an operator (not shown).

In a second cycle, the multiplexer 22 outputs data D1 of the fourteenth register REG_14 as selection data SD. Accordingly, D1 is input to the first register REG_1, and data D14 to D1 stored in all registers REG_1 to REG_14 are shifted and input to the remaining registers REG_2 to REG_15. The data D1 of the fifteenth register REG_15 is output data OUT and is multiplied by the filter coefficient C1 in an operator (not shown).

From the third cycle to the fifteenth cycle, the multiplexer 22 outputs the data of the fourteenth register REG_14 as the selection data OUT. Each time, the data stored in the register is shifted by one register. The output data D2, D3, ..., D14 are input from the fifteenth register REG_15 to an operator (not shown) and multiplied by the filter coefficients C2, C3, ..., C14, respectively. The multiplied data are added together and ultimately output to the filter output data y [14].

In the 16th cycle, the multiplexer 22 outputs new filter input data D15 as selection data SD. Therefore, new filter input data D15 is input to the first register REG_1, and input data stored in all registers is shifted and input to the remaining registers. The data D1 of the fifteenth register REG_15 is multiplied by the filter coefficient C0. In the next 14th cycle (17th to 30th), the output data D2, D3, ..., D15 are multiplied by the respective filter coefficients C1, C2, ..., C14. The multiplied data are added together and ultimately output to the filter output data y [15].

Thus, filter output data y [n] expressed by the following expression (2) is obtained.

y [14] = D0 * C0 + D1 * C1 + ... + D14 * C14

y [15] = D1 * C0 + D2 * C1 + ... + D15 * C14

You can still get the filter output data in the same way.

As described above, in the delay line circuit of the present invention, a selector for selecting one of two input signals is used regardless of the number of taps of the FIR filter. Therefore, even if the number of taps is increased, the size of the delay line circuit is not increased, and the increase in the size of the FIR filter can also be minimized.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Although the number of taps of the FIR filter is increased by the delay line circuit of the present invention, the increase in the size of the delay line circuit can be minimized.

Claims (2)

In a finite impulse response filter with N taps, A first to N-th register for storing and outputting input data for a predetermined time, wherein the data input to the first register is predetermined selection data and is input to the i th (integer with i = 2 to N) register The first to Nth registers may be data that is output data of the i-th register; And And a selector for selecting any one of the output data and the input data of the N-th register and outputting the selected data as the selection data. The method of claim 1, wherein the selector A delay line circuit of a finite impulse response filter, characterized in that it is a multiplexer.