KR100260747B1 - Finite impulse response filter and filtering method thereof - Google Patents

Abstract

PURPOSE: A finite impulse response filter and a finite-impulse-response filtering method are provided which has a memory with a reduced capacity, decreases the size of hardware, and easily adjusts a clock rate controlling the filter to control the capacity of a ROM. CONSTITUTION: A finite impulse response filter generates an address for accessing a memory using two delay lines when data over-sampled m times during one symbol section is inputted. Each of the delay lines is divided into two parts to generate two memory addresses. Each of the generated address is sent to a storage divided into at least two or four. Accordingly, filter output values corresponding to the generated memory addresses are selected from a plurality of filter output values stored in the storage to be outputted. In case where the memory addresses are generated using the two delay lines, the capacity of required memory can be reduced.

Description

Finite field impulse response filter and filtering method

The present invention relates to a digital filter, and more particularly, to a finite field impulse response filter and a filtering method thereof.

A typical filter used in a digital signal processing system is a finite impulse response (FIR) filter. FIR filters are currently being used in most digital signal processing systems because of their superior performance compared to analog filters and infinite impulse response filters. The FIR filter is classified into a tapped delay line type FIR filter and a look-up table type FIR filter according to the configuration.

FIG. 1 is a diagram illustrating a configuration of a FIR filter according to a tapped delay line method, and filtering is performed by performing a convolution. Referring to FIG. 1, when one input data is applied to the shift register 102, the applied filter input data is N input data together with N-1 input data previously inputted to the shift register 102. Form a line. The multipliers 104, 106, 108, ... 110 multiply the N input data and the N filter coefficients stored in the storage unit 112, respectively. The adder 114 then adds the results output from the respective multipliers 104, 106, 108, ..., 110 and outputs them as filter output data.

The FIR filter according to the tapped delay line method is currently most widely used. However, when the above-described filtering type is implemented in a parallel processing method, N multipliers and N-1 adders are required, which increases the hardware size. On the other hand, even when the above-described filtering type is implemented in a serial processing method, there is a disadvantage in that a high speed hardware implementation method is required because N multiplications and N-1 additions must be performed during a time when one input data is applied.

FIG. 2 is a diagram illustrating a configuration of a FIR filter based on a lookup table method. Referring to FIG. 2, a filter output value corresponding to N input combinations is calculated and stored in the ROM 206 in advance. At this time, if one data is applied to the shift register 202, the current filter input data forms N input data lines together with the N-1 input data previously input to the shift register 202. The address generator 204 then generates N input data as an address, and the filter output value stored in the ROM 206 corresponding to the generated address is output as the filter output data.

This type of filtering has the advantage that it is not necessary to use a multiplier when implementing the filter, and a high speed hardware implementation method is required. However, as the number of taps of the filter increases, the capacity of the ROM has to be increased accordingly.

Meanwhile, the applicant of the present application has already implemented a technique for solving the above disadvantages, that is, an FIR filter having a reduced capacity memory (ROM). The FIR filter implemented in this way was first filed on June 29, 1995, and then filed in priority application on June 12, 1996, under Korean Patent Application No. 96-21065 entitled "Limited Impulse Response Filter and Its Filtering Method." It is disclosed in detail. The FIR filter disclosed in the patent is an example of a combination of a tapped delay line method and a look-up table method, and reduces the existing ROM capacity from 2 ^L to m × 2 ^{L / 2} or 2 ^{L / 2 + 1} .

Accordingly, it is an object of the present invention to provide a FIR filter and a filtering method for reducing the size of hardware.

Another object of the present invention is to provide a FIR filter having a reduced capacity memory and a filtering method thereof.

It is still another object of the present invention to provide a FIR filter and a filtering method capable of adjusting the capacity of a ROM according to various applications by freely adjusting a clock rate controlling a filter.

The present invention for achieving the above object proposes a FIR filter and a filtering method that is implemented by using a combination of the tapped delay line method and the lookup table method. The FIR filter according to the present invention generates an address for accessing the memory using two delay lines when m times oversampled data is input during one symbol period. At this time, each delay line is divided into two parts to generate two memory addresses. The generated addresses are provided to at least two or four divided storage means, so that filter output values corresponding to the generated memory addresses are selected and output from among a plurality of filter output values stored in these storage means. . According to the present invention, it is possible to further reduce the capacity of a memory required when generating a memory address using two delay lines.

In the FIR filter according to the first aspect of the present invention, a series of L / 2 delay elements are connected and each delay element sequentially delays and outputs input data according to a predetermined symbol rate. And a series of L / 2 delay elements that are symmetrical with respect to each delay element of the first delay unit, and each delay element sequentially delays the delay output from the first delay unit according to the symbol rate. The first delay bank and the second delay bank including a plurality of ROMs storing filter output values according to a predetermined number of taps, and the last two bit delay outputs of the first delay unit. A third ROM bank comprising ROMs storing filter output values corresponding to an address that can be addressed, and corresponding to an address that can be determined by the first two bit delay outputs of the second delay unit. Each ROM of the first ROM bank using a fourth ROM bank including ROMs storing filter output values, and delay outputs of the remaining (L / 2-2) bits except the last 2-bit delay output of the first delay unit. A first address generation unit for generating a first address for addressing any one of the filter output values stored in the second output, and the remaining (L / 2-2) bits except the first two-bit delay output of the second delay unit. A second address generator for generating a second address for addressing any one of the filter output values stored in each of the ROMs of the second bank using the delayed outputs of the first and second banks; A first multiplexer and a third multiplexer for multiplexing and outputting the filter output value output from the third ROM bank according to the oversampling rate / 2 times the clock of the symbol rate; A second multiplexer and a fourth multiplexer configured to sequentially multiplex and output a filter output value output from the second and fourth ROM banks in a reverse order to the multiplexing order by the first and third multiplexers; A first filter output value processing unit for directly outputting or outputting the filter output values outputted from the multiplexer and the third multiplexer by performing two's complement processing; and directly outputting or complementing two filter output values output from the second multiplexer and the fourth multiplexer. And a second filter output value processing unit for processing and outputting, and an adder for adding the filter output values output from the first filter output value processing unit and the second filter output value processing unit and outputting them as filter output data.

According to a second aspect of the present invention, a FIR filter includes a first delay unit configured to connect a series of L / 2 delay elements, and each delay element sequentially delays and outputs data according to a predetermined symbol rate; It consists of a series of L / 2 delay elements in a symmetric relationship with respect to each delay element of the first delay unit, each delay element sequentially delays and outputs the delay output from the first delay unit in accordance with the symbol rate A counter for counting a second delay unit, a clock twice the symbol rate and outputting a first output signal representing the counting result and a second output signal representing the inverse counting result, and a last two bit delay of the first delay unit; A first multiplexer for multiplexing the output and the first 2-bit delayed output of the second delay unit according to a clock four times the symbol rate, and each of the outputs of the first multiplexer A ROM bank comprising ROMs storing filter output values corresponding to addresses determined by the second bank; a second multiplexer configured to multiplex and output a filter output value output from the ROM bank according to a clock four times the symbol rate; A third multiplexer for multiplexing the first delay output of the first delay section and the last delay output of the second delay section according to a clock four times the symbol rate, and outputting the first delay section as a control signal, and the first output signal and the second output signal. By multiplexing according to a clock value four times the symbol rate, this multiplexing result is generated as a 2-bit address most significant bit value, and the delay outputs of the remaining (L / 2-3) bits excluding the first delay output of the first delay unit and these The delayed outputs of the second delay unit, which are symmetrical with respect to the outputs, are each remote according to a clock four times the symbol rate. A plurality of multiplexers which are output by flexing and outputting exclusive outputs of the multiplexers except for the multiplexer generating the most significant bit value of the address among the multiplexers and the control signal, and outputting these outputs to the most significant bit value of the address. A plurality of exclusive logical sum circuits outputting the bit values of the (L / 2-3) bits connected to each other; a filter output value according to a predetermined number of taps; and a most significant bit value generated by the initial multiplexer of the multiplexers. A lookup table for outputting a filter output value accessed by an address of a (L / 2-1) bit determined by the remaining (L / 2-3) bit values generated by the plurality of exclusive OR circuits, and the lookup Complement two of the filter output values output from the table and the second multiplexer according to the control signal. A filter output value processing unit for processing and outputting or outputting directly, a register for temporarily storing the output of the filter output value processing unit, a filter output value temporarily stored by the register and a filter output value processed by the filter output value processing unit, and adding the filter At least an adder for outputting as output data.

According to a third aspect of the present invention, a FIR filter includes: a first delay unit configured to connect a series of L / 2 delay elements, each delay element sequentially delaying and outputting data according to a predetermined symbol rate; It consists of a series of L / 2 delay elements in a symmetric relationship with respect to each delay element of the first delay unit, each delay element sequentially delays and outputs the delay output from the first delay unit in accordance with the symbol rate A counter for counting a second delay unit, a clock twice the symbol rate and outputting a first output signal representing the counting result and a second output signal representing the inverse counting result, and a last two bit delay of the first delay unit; A first multiplexer for multiplexing the output and the first 2-bit delayed output of the second delay unit according to a clock four times the symbol rate, and each of the outputs of the first multiplexer A first ROM bank composed of ROMs storing filter output values corresponding to an address determined by the second multiplex, and a second multiplexed filter output value output from the first ROM bank according to a clock four times the symbol rate. A multiplexer, a third multiplexer for multiplexing the first output signal and the second output signal according to a clock four times the symbol rate, an initial delayed output of the first delay unit and a final delayed output of the second delay unit; Is multiplexed according to a clock of 4 times the symbol rate and output as a control signal, delay outputs of (L / 2-3) bits other than the initial delay output of the first delay unit, and these outputs. Multiple multiplexing the delayed outputs of the second delay unit symmetrical relative to each other according to a clock four times the symbol rate A lexer, a plurality of exclusive logical sum circuits for outputting each output and the control signal of the plurality of multiplexers and the control signals and outputting these outputs as addresses, and a plurality of ROMs each storing filter output values according to a predetermined number of taps. A second ROM bank for outputting a filter output value accessed by an address generated by the plurality of exclusive OR circuits, and multiplexing the filter output values output from the respective ROMs of the second ROM bank according to the output of the third multiplexer. A filter output value processing unit for outputting or directly outputting a fifth multiplexer outputting the second multiplexer, filter output values output from the second multiplexer and the fifth multiplexer according to the control signal, or directly outputting the result; To registers to be temporarily stored It is made to temporarily contain the stored filter output value and the adder which adds the output value of the filter processing by the filter processing section outputs the output value as a filter output data at least.

1 is a block diagram of a finite field impulse response filter according to a tapped delay line method.

2 is a block diagram of a finite field impulse response filter according to a lookup table method;

3 is a diagram illustrating a configuration of a modulator of a binary data transmission system to which a finite field impulse response filter according to the present invention can be applied.

4 is a diagram illustrating a form of data input to a filter illustrated in FIG. 3.

5 is a block diagram of a finite field impulse response filter according to a first embodiment of the present invention;

6 is a block diagram of a finite field impulse response filter according to a second embodiment of the present invention;

7 is a block diagram of a finite field impulse response filter according to a third embodiment of the present invention;

FIG. 8 is a detailed configuration diagram of a first signal processor and a second signal processor illustrated in FIG. 5.

FIG. 9 is a detailed configuration diagram of the first signal processing unit shown in FIG. 6.

FIG. 10 is a detailed configuration diagram of the first signal processing unit shown in FIG. 7.

11 is a view showing the operation timing of the finite field impulse response filter according to the first embodiment of the present invention.

12 is a view showing operation timing of a finite field impulse response filter according to a second embodiment of the present invention.

13 is a view showing the operation timing of the finite field impulse response filter according to the third embodiment of the present invention;

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are used as much as possible even if displayed on different drawings. In addition, in the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to the intention or custom of the user or chip designer, and the definitions should be made based on the contents throughout the present specification. In the following, L represents the filter length, m represents the oversampling rate, N represents the number of filter taps, and n represents the number of bits of data output from the ROM. FI represents the input data of the filter, FO represents the output data of the filter. The first clock CLK1 represents a clock of symbol rate, the second clock CLK2 represents a clock twice the symbol rate, and the third clock CLK3 represents a clock four times the symbol rate. The control signal CONT3 is a signal according to the counting result of the second clock CLK2, and the control signal CONT4 represents a reverse order of the result of counting the second clock CLK2. The control signal CONT3 is a signal inverted. The control signal CONT10 represents the initial delay output value of the first delay unit 502 composed of L / 2 delay elements, and the control signal CONT20 represents the final delay of the second delay unit 504 composed of L / 2 delay elements. Indicates the output value. The control signals CONT30 and CONT40 are signals indicating the multiplexing result when the first delayed output value of the first delay unit 502 and the final output value of the second delay unit 504 are multiplexed according to the third clock CLK.

First, before describing the FIR filter according to the present invention, a modulator of a binary data transmission system to which the present invention can be applied will be described.

3 shows a configuration of a modulator of a binary data transmission system, wherein the modulator includes low pass filters 306 and 308. The low pass filters 306 and 308 usually use sections having a length of L as the filter length, and the sections are oversampled by m times to be implemented by a digital filter having N (L × m) filter taps. Can be. The present invention can be applied not only to the implementation of the low pass filters 306 and 308 included in the modulator of the binary data transmission system, but also to the implementation of all filters that accept data in the form of pulses mapped to ± 1 impulses. have. In FIG. 3, the signal mapping unit 304 provides a filter input form mapped to an impulse of ± 1.

On the other hand, when the digital filter is designed to have a linear phase characteristic, the filter coefficient values are usually designed to have symmetry. The symmetry of the filter coefficients means that, for example, when the filter coefficient values are 5, C-2, C-1, C0, C1, and C2, the values of C-2 and C2 are the same, and C-1 and C1 It means the same value. It should be noted that the filter coefficient values according to the present invention are also designed to have the same symmetry.

FIG. 4 is a diagram showing the type of input data applied to the low pass filters 306 and 308, in which m-fold oversampled signals are input during one symbol period. That is, the first sample of one symbol section has the actual value "± 1" mapped by the signal mapping unit 304, and the remaining m-1 samples have the form of "0". Since the input data of this type is applied to the low pass filters 306 and 308, one filter output value is obtained after L multiplications and L-1 additions are performed during one oversampling time in the low pass filters 306 and 308. During the symbol interval, m filter outputs are obtained after the multiplication by mL and the addition of m (L-1) are performed. If the FIR filter performing the above operation is to be implemented according to the lookup table method as shown in FIG. 2, the required ROM will have a capacity of ^2L .

The m filter output values output during the one symbol section in the low pass filter 306 are multiplied by the carrier wave oscillated in the local oscillator 310 and the multiplier 312, and the one symbol section in the low pass filter 308. M filter output values, which are output during the multiplication process, are oscillated by the local oscillator 310 and then multiplied by the carrier 316 multiplied by a phase shifter π / 2 by the phase shifter 314. The result of multiplication by the multiplier 312 and the multiplier 316 is added by the adder 318 and then output as a transmission signal.

Next, the configuration and operation of the FIR filter according to the present invention will be described in detail for each embodiment.

First embodiment

5 is a view showing the configuration of the FIR filter according to the first embodiment of the present invention, Figure 8 is a view showing a specific configuration of the first signal processing unit 506 and the second signal processing unit 508 shown in FIG. 11 is a view showing the operation timing of the FIR filter according to the first embodiment.

Referring to FIG. 5, the FIR filter of the present invention includes L / 2 delay elements, and a delay unit for delaying and outputting the impulse data FI input according to the symbol rate CLK1 by L / 2 steps. 502 and 504, the first signal processor 506 and the second signal processor 508 constituting a memory address using the delay output values from the delay units 502 and 504, and a plurality of filter output values. The memory addresses determined by the delay output values [x (n) to x (nL / 2 + 3), x (nL / 2 + 2) to x (n-L + 1)] by the delay units 502 and 504. Rombanks 510 and 512 outputting the corresponding filter output values, Rombanks 524 and 526 used to further reduce the capacity of the Rombanks 510 and 512, and Filter output values output from the respective Rombanks 510, 512, 524 and 526. An adder 522 that adds and outputs the filtered value.

First, the present invention divides a delay line for storing data (0 or 1 corresponding to ± 1) into every first symbol section into a first delay unit 502 and a second delay unit 504, thereby combining the number of memory addresses. To reduce from 2 ^L to (2 ^{L / 2} +2 ^{L / 2} ). Such a method is a technique disclosed under Korean Patent Application No. 96-21065, titled "Limited Impulse Response Filter and its Filtering Method," filed previously by the present applicant as described in the prior art. However, in the present invention, the least significant two bits of each delay unit 502 and 504 {x (nL / 2 + 2), x (nL / 2 + 1); x (n-L + 2), x (n-L + 1) } The memory address combinations are reduced from 2 ^{L / 2} back to (2 ^{L / 2-4} +2 ² ), and finally the memory address combinations inputted into the rombank from the delay section. by using the symmetry of reducing the memory in combination of 2 ^{L / 2-4} to 2 ^{L / 2-3.} Therefore, the total amount of ROM required in the present invention is (2 ^{L / 2-3} +2 ² ), which is a considerable amount of ROM compared with 2 ^{L × m} , which is the total amount of ROM required in a conventional ROM lookup table filter. It can be seen that a reduction in capacity has been brought about.

The characteristics of the present invention, that is, the FIR filtering method according to the present invention for reducing the ROM capacity will be described in more detail. Once input, the data is maintained for one symbol period as an address required to calculate m filter output values. That is, each of the delay units 502 and 504 forming the delay line is operated by the symbol clock CLK1, and the outputs of the first and second ROM banks 510 and 512 are m / 2 times the symbol rate. It is controlled by the multiplexers 514, 516, 528 and 530 which operate according to the output values CONT3 and CONT4 of the Modulo-3 counter 524 which is operated by a clock, i.e., the clock twice the symbol rate CLK2. Each output of the multiplexers 514, 516, 528, 530 according to the control is applied to the adder 522, is added, and then output. At this time, m filter values are output during one symbol period.

Meanwhile, the process of obtaining the m filter output values while maintaining the input data for one symbol period obtains the same result as performing the m convolution while shifting the data input to the delay units 502 and 504 for one symbol period m times. That is, the position of the L filter coefficient values that are multiplied by the actual data when m filter output values are calculated is fixed in correspondence to the number of m. These operations are summarized as shown in Tables 1, 2, and 3 below.

division Filter coefficient values corresponding to the first delay unit 502 Filter coefficient values corresponding to the second delay unit 504 n = 0n = 1 · n = m-2n = m-1 h [0], h [n + m],... … … , h [n + (L / 2-1) m] h [1], h [n + m + 1],... H [n + (L / 2-1) m] ... h [m-2], h [n + 2m-2],... , h [n + (L / 2-1) m] h [m-1], h [n + 2m-1],... , h [n + (L / 2-1) m] h [n + (L / 2-1) m],... , h [n + 2m-1], h [m-1] h [n + (L / 2-1) m],... h [n + 2m-2], h [m-2] .h [n + (L / 2-1) m]; … , h [n + m + 1], h [1] h [n + (L / 2-1) m],... … H [n + m], h [0]

division Filter coefficient values corresponding to the first rom bank 510 Filter coefficient values corresponding to the second ROM bank 512 n = 0n = 1 · n = m-2n = m-1 h [0], h [n + m],... … … , h [n + (L / 2-3) m] h [1], h [n + m + 1],... H [n + (L / 2-3) m] ... h [m-2], h [n + 2m-2],... , h [n + (L / 2-3) m] h [m-1], h [n + 2m-1],... , h [n + (L / 2-3) m] h [n + (L / 2-3) m],... , h [n + 2m-1], h [m-1] h [n + (L / 2-3) m],... h [n + 2m-2], h [m-2] .h [n + (L / 2-3) m]; … , h [n + m + 1], h [1] h [n + (L / 2-3) m],... … H [n + m], h [0]

division Filter coefficient values corresponding to the third ROM bank 524 Filter Coefficients Corresponding to Fourth Lom Bank 526 n = 0n = 1 · n = m-2n = m-1 h [n + (L / 2-2)], h [n + (L / 2-1) m] h [n + (L / 2-2)], h [n + (L / 2-1) m] h [n + (L / 2-2)], h [n + (L / 2-1) m] h [n + (L / 2-2)], h [n + (L / 2-1) m] h [n + (L / 2-2)], h [n + (L / 2-1) m] h [n + (L / 2-2)], h [n + (L / 2-1) m] h [n + (L / 2-2)], h [n + (L / 2-1) m] h [n + (L / 2-2)], h [n + (L / 2-1) m]

Referring to Table 1, the array of filter coefficient values by which the non-zero filter input values of the delay unit 504 are multiplied when m = 0 is the filter coefficient value of the delay unit 502 when m = m-1. It can be seen that the positional arrangement of the filter coefficient values of the delay unit 504 in the reverse order with respect to the arrangement of the sigma units is equal to the positional arrangement of the filter coefficient values of the delay unit 502 when m = m-2. have. m = 2,... The same rule applies when, m = m-1. Therefore, the output values of the second and second ROM banks 512 and 526 output by the address generated by the delay unit 504 are stored in the first and second ROM banks 510 and 524, respectively. This means that it can be obtained as a set of values. Therefore, in FIG. 5, all the filter output values desired by using only one of the memory banks of the first and second banks 510 and 524, the second and second banks 512 and 526, respectively. The conclusion that it can be obtained and the possible implementation such as this will be described in detail in FIG. 6 and FIG.

The FIR filter according to the present invention operates on the basic principle described above. In the FIR filter according to the first embodiment of the present invention, as shown in FIG. / 2 + 1)] [x (n-L + 2), x (n-L + 1)] were used as memory addresses of the third and second ROM banks 524 and 526, respectively. The L / 2-2 bits are used to generate the memory addresses of the first and second ROM banks 510 and 512 through the first signal processor 506 and the second signal processor 508, respectively. In this case, the total capacity of the first ROM bank 510 and the second ROM bank 512 is to be respectively 2 ^{L / 2-2} but is actually one-half the use of 2 ^{L / 2-3} reduced. This operation is possible by configuring the first signal processing unit 506 and the second signal processing unit 508 as a plurality of exclusive logic circuits as shown in FIG.

Referring to FIG. 6, the first signal processing unit 506 and the second signal processing unit 508 perform a pass or complementary operation of 1 according to the control signals CONT10 and CONT20, respectively. That is, the first signal processing unit 506 using the initial delay output x (n) of the delay unit 502 as the control signal CONT10 sets the control signal CONT10 as a common input for each exclusive logic circuit. When the value of the address determined by the delay unit 502 is another input of the exclusive logic circuits, the control signal indicates an address larger than ^{2L / 2-3} (when the “high” level is indicated). Perform one's complement operation on the values of the address. In addition, the second signal processing unit 508 having the final delay output [x (n-L + 1)] of the delay unit 504 as the control signal CONT20 uses the common control circuit CONT20 as the control signal CONT20. When the control signal CONT20 indicates an address larger than 2 ^{L / 2-1} by using the input and the values of the addresses determined by the delay unit 504 as other inputs of the exclusive OR circuits ("high" level) In the case of representing a), a complementary operation of 1 for the values of the determined address is performed.

In this case, since the actual values multiplied by the filter coefficient values are ± 1, considering that the binary data values of L / 2-2 bits constituting the binary address are symmetric about 2 ^{L / 2-3} values, 2 ^{L /} It can be seen that the memory stored values designated by addresses of ^2-3 or more can be obtained by calculating the two's complement of the memory stored values designated by addresses less than 2 ^{L / 2-3} . Therefore, the memory capacity can be reduced once again.

The complementary operation of 2 is processed by the third signal processing unit 518 and the fourth signal processing unit 520, and the third signal processing unit 518 and the fourth signal processing unit 520 respectively control signals CONT10 and CONT20. According to the two's complementary operation. That is, the third signal processing unit 518 having the initial delay output value [x (n)] of the delay unit 502 as the control signal CONT1 has an address in which the control signal CONT1 is larger than ^{2L / 2-3.} The memory output value from the first ROM bank 510 selected by the first multiplexer 514 at the time of indicating the "high" level is complemented by two. The fourth signal processing unit 520 having the final delay output value [x (n-L + 1)] of the delay unit 504 as the control signal CONT20 has the control signal CONT2 of 2 ^{L / 2-3.} When indicating a larger address, the memory output value from the second ROM bank 512 selected by the second multiplexer 516 is processed by two's complement. In addition to the above operation, the third signal processor 518 and the fourth signal processor 520 may be selected by the third multiplexer 528 and the fourth multiplexer 530, respectively. ) Outputs the sums of the output values by the first multiplexer 514 and the second multiplexer 516 and then outputs the sum of the output values.

The 48-tap FIR filter L = 12, m = 4 will be described as an example to more easily understand how the filtering of the present invention described above works in conjunction with the configuration of FIG. 5. In the case of a 48-tap FIR filter, the position of the filter coefficient values multiplied by the input data is fixed for each value of m. This is shown in <Table 4>, and <Table 5> and <Table 6> are reconstructed according to the operation configuration of the present invention configured to the <Table 4> as shown in FIG.

Filter coefficient values corresponding to the first delay unit 502 Filter coefficient values corresponding to the second delay unit 504 m = 0 (0) h [0], h [4], h [8], h [12], h [16], h [20] (3) 'h [23], h [19], h [15], h [11], h [7], h [3] m = 1 H [1], h [5], h [9], h [13], h [17], h [21] (2) 'h [22], h [18], h [14], h [10], h [6], h [2] m = 2 (2) h [2], h [6], h [10], h [14], h [18], h [22] (1) 'h [21], h [17], h [13], h [9], h [5], h [1] m = 3 H [3], h [7], h [11], h [15], h [19], h [23] (0) 'h [20], h [16], h [12], h [8], h [4], h [0]

Filter coefficient values corresponding to the first rom bank 510 Filter coefficient values corresponding to the second ROM bank 512 m = 0 (0) h [0], h [4], h [8], h [12] (3) 'h [15], h [11], h [7], h [3] m = 1 (1) h [1], h [5], h [9], h [13] (2) 'h [14], h [10], h [6], h [2] m = 2 (2) h [2], h [6], h [10], h [14] (1) 'h [13], h [9], h [5], h [1] m = 3 (3) h [3], h [7], h [11], h [15] (0) 'h [12], h [8], h [4], h [0]

Filter coefficient values corresponding to the thirteenth rombank 524 Filter Coefficients Corresponding to Fourth Lom Bank 526 m = 0 (0) h [16], h [20] (3) 'h [23], h [19] m = 1 (1) h [17], h [21] (2) 'h [22], h [18] m = 2 (2) h [18], h [22] (1) 'h [21], h [17] m = 3 (3) h [19], h [23] (0) 'h [20], h [16]

Table 5 shows the positions of the filter coefficient values used when the least two bits of the delay units 502 and 504 are excluded. Table 6 shows the filters corresponding to the least significant two bits among the ROM addresses. To count values. Here, the least significant two bits are x (nL / 2 + 2), x (nL / 2 + 1), which are the last 2-bit delay outputs from the first delay unit 502, and from the second delay unit 504. The first two bits of delay output are x (nL / 2) and x (nL / 2-1).

The basic concept of the present invention and how the data of the 6-bit (L / 2 = 12/2 = 6) delay units 502 and 504 are classified and used as a memory address of a ROM bank are shown in Table 7 below. As it is. Table 7 shows an example of a 48-tap FIR filter.

Delay part data (6 bits) 1, 2 rombank address (actual use) Delay part data (high 4 bits) 3rd and 4th bank bank address (lower 2 bits) Delay part data (6 bits) 1, 2 rombank address (not used) Delay part data (high 4 bits) 3rd and 4th bank bank address (lower 2 bits) 0 (000000) # 0 (0000) 0000 00 32 (100000) # 8 (1000) 1000 00 1 (000001) 0000 01 33 (100001) 1000 01 2 (000010) 0000 10 34 (100010) 1000 10 3 (000011) 0000 11 35 (100011) 1000 11 4 (000100) # 1 (0001) 0001 00 36 (100100) # 9 (1001) 1001 00 5 (000101) 0001 01 37 (100101) 1001 01 6 (000110) 0001 10 38 (100110) 1001 10 7 (000111) 0001 11 39 (100111) 1001 11 8 (001000) # 2 (0010) 0010 00 40 (101000) # 10 (1010) 1010 00 9 (001001) 0010 01 41 (101001) 1010 01 10 (001010) 0010 10 42 (101010) 1010 10 11 (001011) 0010 11 43 (101011) 1010 11 12 (001100) # 3 (0011) 0011 00 44 (101100) # 11 (1011) 1011 00 13 (001101) 0011 01 45 (101101) 1011 01 14 (001110) 0011 10 46 (101110) 1011 10 15 (001111) 0011 11 47 (101111) 1011 11 16 (010000) # 4 (0100) 0100 00 48 (110000) # 12 (1100) 1100 00 17 (010001) 0100 01 49 (110001) 1100 01 18 (010010) 0100 10 50 (110010) 1100 10 19 (010011) 0100 11 51 (110011) 1100 11 20 (010100) # 5 (0101) 0101 00 52 (110100) # 13 (1101) 1101 00 21 (010101) 0101 01 53 (110101) 1101 01 22 (010110) 0101 10 54 (110110) 1101 10 23 (010111) 0101 11 55 (110111) 1101 11 24 (011000) # 6 (0110) 0110 00 56 (111000) # 14 (1110) 1110 00 25 (011001) 0110 01 57 (111001) 1110 01 26 (011010) 0110 10 58 (111010) 1110 10 27 (011011) 0110 11 59 (111011) 1110 11 28 (011100) # 7 (0111) 0111 00 60 (111100) # 15 (1111) 1111 00 29 (011101) 0111 01 61 (111101) 1111 01 30 (011110) 0111 10 62 (111110) 1111 10 31 (011111) 0111 11 63 (111111) 1111 11

As shown in Table 7, 64 six-bit delay data is divided into upper 4 bits and lower 2 bits, respectively. Comparing the upper 4 bits of the 64 6-bit data except the lower 2 bits, the data is grouped into 16 (# 0 to # 15) 4-bit data. The values of the grouped data are input to the first signal processing unit 506 and the second signal processing unit 508 and passed through an exclusive logical sum circuit by the respective control signals CONT10 and CONT20, and finally 3 bits (000 to 111). Generated as a ROM address of. That is, the ROM bank stored value between 1000 and 1111 has only the ROM banks 510 and 512 stored values between 000 and 111, and can be generated by the signal processing units 506, 508, 518 and 520 and the control signals CONT10 and CONT20. In addition, because the lower 2 bits of the 64 bits of each delay part change most frequently, but only 4 combinations are used, this property makes 64 6 bits of data into 16 4 bits of data. It can be implemented with only three 3-bit ROM capacities. These lower two bits are used as addresses of the third and second ROM banks 524 and 526.

The operation principle of the present invention will now be described using the following equation. The operation at this time is m = 0 and has been described using an example where it is applied to the first delay unit 502.

Filter output (111111) = -h [0] -h [4] -h [8] -h [12] -h [16] -h [20]

=-{h [0] + h [4] + h [8] + h [12]} + {-h [16] -h [20]}

=-{First rombank output [address]} + {third rombank output [address]}

=-{First rombank output [000]} + {third rombank output [11]}

= Output of the third signal processor 518

Filter output (001010) = h [0] + h [4] -h [8] + h [12] -h [16] + h [20]

= {h [0] + h [4] -h [8] + h [12]} + {-h [16] + h [20]}

= {First rombank output [address]} + {third rombank output [address]}

= {First rombank output [010]} + {third rombank output [10]}

= Output of the third signal processor 518

As shown in Equations 1 and 2 above, 64 memory address combinations for each value of m are 8 (2 ^{L / 2-3} = 2 ^6-3 = 2 ³ ). It can be seen that it can be configured as ROMs 510 and 512 having 4 capacities and ROMs 524 and 526 having 4 (2 ² ) capacities. Thus, a total of 12 ROM capacities can replace 64 ROM capacities.

Tables 8 and 9 below show the stored values of the first and second ROM banks 510 and 512 and the third ROM bank 524 when m = 0 in the 48-tap FIR filter, respectively. And a stored value of the fourth ROM bank 526.

Address Stored value Address Stored value 000 h [0] + h [4] + h [8] + h [12] 100 h [0] -h [4] + h [8] + h [12] 001 h [0] + h [4] + h [8] -h [12] 101 h [0] -h [4] + h [8] -h [12] 010 h [0] + h [4] -h [8] + h [12] 110 h [0] -h [4] -h [8] + h [12] 011 h [0] + h [4] -h [8] -h [12] 111 h [0] -h [4] -h [8] -h [12]

Address (2 bits) Stored value 00 h [16] + h [20] 01 h [16] -h [20] 10 -h [16] + h [20] 11 -h [16] -h [20]

In summary, the FIR filter according to the first embodiment of the present invention generates a memory address through two delay lines when two times oversampled signals are input during one symbol period, and stores two memory addresses. A filter output value corresponding to the generated memory address is selected and output from among the filter output values already stored in the means. As a result, the memory capacity required for implementing the filter having the filter length L, the number of taps N, and the oversampling ratio m was reduced from 2 ^{L × m} to (2 ^{L / 2-3} + 2 ² ) × m.

As illustrated in FIG. 5, the FIR filter described so far is implemented at a speed of twice the clock rate CLK2 of the symbol rate CLK1. Thus, in the case of the FIR filter implemented as described above, the required memory capacity is significantly reduced. The method is described. On the other hand, even when the FIR filter is implemented using a clock speed four times higher than the symbol rate, it is necessary to consider the FIR filter and the filtering method that can reduce the required memory capacity. 6 and 7 show the configuration of the FIR filter implemented according to this principle. That is, FIGS. 6 and 7 show the configuration of the FIR filters using the clock four times the symbol rate CLK3. The FIR filters shown in FIG. 5 show the memory capacity required for implementing the FIR filter in FIG. It provides a method that can be significantly reduced than the illustrated FIR filter. It should be noted that since the basic principle of the FIR filter shown in FIGS. 6 and 7 is the same as the FIR filter shown in FIG.

Second embodiment

FIG. 6 is a diagram illustrating a configuration of an FIR filter according to a second embodiment of the present invention. FIG. 9 is a diagram illustrating a detailed configuration of the first signal processing unit 608 shown in FIG. 6, and FIG. FIG. 3 illustrates an operation timing of an FIR filter according to an embodiment. FIG.

Unlike the FIR filter illustrated in FIG. 5, the FIR filter illustrated in FIG. 6 uses a clock CLK3 that is four times the symbol rate CLK1, and uses the clock CLK3 to supply an address to each ROM bank. I'm using a method of multiplexing them. In addition, the configuration of the lookup table 610 as a memory having a concatenated address without using a separate ROM bank as used in FIG. 5 eliminates the need for the multiplexers 514 and 516 required in FIG. Accordingly, the overall hardware size can be reduced.

Referring to FIG. 9, the first of FIG. 5 is used except for multiplexing the addresses using the clock CLK3 four times the symbol rate and using the output of the external modulo-3 counter 606 to generate the addresses. It can be seen that the structure of the signal processor 506 and the second signal processor 508 has the same structure. In addition, the second signal processor 612 of FIG. 6 is also implemented to perform the same functions as the third signal processor 518 and the fourth signal processor 520 of FIG. 5. Meanwhile, in the second embodiment of the present invention, in order to replace the third and second ROM banks 524 and 526 of FIG. 5 with only one ROM bank 618, a multiplexer (MUX2) 622 ). The multiplexer (MUX2) 622 selects output data of the ROM bank 618 according to the quadruple clock CLK3.

)를 출력한다.In FIG. 6, the first delay unit 602 is formed by connecting a series of L / 2 delay elements x (n) to x (nL / 2 + 1), and each delay element symbolizes the input data. Output is delayed sequentially according to (CLK1). The second delay unit 604 is composed of a series of L / 2 delay elements that are symmetrical with respect to each delay element of the first delay unit 602, and each delay element is determined according to the symbol rate CLK1. The delayed output from the first delay unit 602 is sequentially delayed and output. The counter 606 counts the clock CLK2 twice the symbol rate, and outputs the first output signal OUT indicating the counting result and the second output signal indicating the inverse counting result.

)

The first multiplexer (MUX1) 620 is a final 2-bit delay output [x (nL / 2 + 2), x (nL / 2 + 1)] of the first delay unit 602 and the second delay unit ( The first two bit delay outputs x (nL / 2) and x (nL / 2-1) of 604 are multiplexed and output according to the clock CLK3 of the symbol rate. The ROMBank 618 is composed of ROMs (ROMs # 0 to # 3), each of which stores filter output values corresponding to an address that can be determined by the output of the first multiplexer (MUX1) 620. At this time, each of the ROMs of the ROM bank 618 has a capacity of 2 ² . The second multiplexer (MUX2) 622 multiplexes the filter output value output from the ROM bank 618 according to the clock CLK3 of 4 times the symbol rate.

)를 상기 심볼레이트의 4배 클럭(CLK3)에 따라 멀티플렉싱하여 이 멀티플렉싱 결과를 2비트의 어드레스의 최상위 비트값(MSB)으로 생성한다. 그리고 나머지의 멀티플렉서들은 제1지연부(602)의 최초 지연출력을 제외한 나머지 (L/2-3)비트의 지연출력들[x(n-1)∼x(n-L/2+3)]과 이들 출력들에 대해 대칭관계에 있는 제2지연부(604)의 지연출력들[x(n-L+2)∼x(n-L/2+2)]을 상기 심볼레이트의 4배 클럭(CLK3)에 따라 각각 멀티플렉싱하여 출력한다. 상기 다수의 멀티플렉서의 후단에는 다수의 배타적 논리합회로가 연결되는데, 이 다수의 배타적 논리합회로는 다수의 멀티플렉서중에서 최상위 비트값(MSB)을 생성하는 멀티플렉서를 제외한 나머지 멀티플렉서들의 각 출력과 제어신호(CONT30)를 배타적 논리합연산하여 이들 출력을 어드레스의 최상위 비트값에 연결되는 (L/2-3)비트의 각 비트값으로 출력한다. 결과적으로 제1신호처리부(608)는 2비트의 최상위 비트값(MSB)과 (L/2-3)비트값을 제공받아 (L/2-1)비트의 어드레스를 생성하는 동작을 수행하는 것이다.In Fig. 9, the 2: 1 MUX recalls the initial delay output [x (n)] of the first delay unit 602 and the final delay output [x (n-L + 1)] of the second delay unit 604. Multiplexing is performed according to the clock CLK3 of the symbol rate, and the result of the multiplexing is output as a control signal CONT30. In addition, a plurality of multiplexers are shown in FIG. 9, wherein the initial multiplexer includes a first output signal OUT and a second output signal (

) Is multiplexed according to the clock CLK3 of the symbol rate to generate the result of the multiplexing as the most significant bit value MSB of the 2-bit address. The remaining multiplexers are delayed outputs [x (n-1) to x (nL / 2 + 3)] of the remaining (L / 2-3) bits except for the initial delay output of the first delay unit 602. The delayed outputs x (n-L + 2) to x (nL / 2 + 2) of the second delay unit 604, which are symmetrical with respect to the outputs, are applied to the clock CLK3 four times the symbol rate. Therefore, it is output by multiplexing each. A plurality of exclusive logical sum circuits are connected to a rear end of the multiplexers. The plurality of exclusive logical sum circuits each output and control signal CONT30 of the multiplexers except for the multiplexer generating the most significant bit value MSB among the multiplexers. Is the exclusive OR operation and outputs these outputs as respective bit values of (L / 2-3) bits connected to the most significant bit value of the address. As a result, the first signal processor 608 receives the most significant bit value MSB and the (L / 2-3) bit value of 2 bits to generate an address of the (L / 2-1) bit. .

In FIG. 6, the lookup table 610 has a capacity of 2 ^{(L / 2-1)} and stores filter output values according to the number of taps N, and is generated by the first signal processing unit 608 (L / The filter output value accessed by the address of the bit 2-1) is output. The second signal processor 612 selectively performs two's complement processing on the filter output values output from the lookup table 610 according to the control signal CONT30. When the control signal CONT30 is at the "high" level, the second signal processing unit 612 performs the complementary processing of the filter output value output from the lookup table 610 to 2, and outputs the control signal CONT30 at "low". In the case of the level, the filter output value output from the lookup table 610 is directly output. In addition, the second signal processor 612 outputs a sum of the filter output value processed after being output from the lookup table 610 and the filter output value applied from the second multiplexer (MUX2) 622. The output from the second signal processor 612 is applied to the register 614 to be temporarily stored. The adder 616 adds the filter output value temporarily stored by the register 614 and the filter output value processed by the second signal processing unit 612 to output the filter output data FO.

As described above, the FIR filter according to the second embodiment of the present invention requires only a lookup table having a capacity of 2 ^{L / 2-1 and} a ^{Rombank having} a capacity of 2 ² . Controlled by the double clock CLK3. Therefore, it can be seen that the required memory capacity is reduced by half compared to the memory capacity required by the FIR filter shown in FIG. 5. In addition, in the case of the FIR filter illustrated in FIG. 5, multiplexers 514, 516, 528, and 530 are required, but such multiplexers are not required. As a result, the FIR filter according to the second embodiment of the present invention provides the same filtering effect while having a simplified memory and a simplified configuration compared to the FIR filter according to the first embodiment of the present invention.

Third embodiment

7 is a view showing the configuration of the FIR filter according to a third embodiment of the present invention, FIG. 10 is a view showing the specific configuration of the first signal processing unit 708 shown in FIG. 7, and FIG. 13 is the third FIG. 3 illustrates an operation timing of an FIR filter according to an embodiment. FIG.

FIG. 7 shows a structure similar to that of the FIR filter shown in FIG. 5. The FIR filter according to the third embodiment of the present invention uses two ROM banks 722 and 712 and two multiplexers 726 and 714, and inputs the ROM bank 712 using a clock four times the symbol rate CLK3. Multiplexing the output values of the first signal processor 708 and the modulo-3 counter 706 to generate the addresses. That is, the FIR filter according to the third embodiment of the present invention is implemented to have a memory capacity as shown in FIG. 6 while having a structure similar to that of the FIR filter shown in FIG. 5. Also, as in FIG. 6, output data values of the rombank 722 are selected by the second multiplexer 726 controlled by the quadruple clock CLK3. The input addresses of the rombank 722 are the lower two bits [x (nL / 2 + 2), x (nL / 2 + 1)] [x (nL / 2), x (of each delay unit 702,704. nL / 2-1)], and these addresses are also multiplexed by a 2: 1 multiplexer 724 controlled by a clock CLK3 four times the symbol rate.

)를 출력한다.In FIG. 7, the first delay unit 702 is formed by connecting a series of L / 2 delay elements [x (n) to x (nL / 2 + 1)] and each delay element symbolizes input data. Output is delayed sequentially according to (CLK1). The second delay unit 704 is a series of L / 2 delay elements [x (nL / 2) to x (n-L + 1)] which are symmetrical with respect to each delay element of the first delay unit 702. Each delay element sequentially delays and outputs the delay output from the first delay unit 702 according to the symbol rate CLK1. The counter 706 counts the clock CLK2 twice the symbol rate, and outputs the first output signal OUT indicating the counting result and the second output signal indicating the reverse counting result.

)

The first multiplexer (MUX1) 620 is a final 2-bit delay output [x (nL / 2 + 2), x (nL / 2 + 1)] of the first delay unit 602 and the second delay unit ( The first two bit delay outputs x (nL / 2) and x (nL / 2-1) of 604 are multiplexed and output according to the clock CLK3 of the symbol rate. The rombank 722 is composed of ROMs # 0 to # 3, each of which stores filter output values corresponding to an address that can be determined by an output of the first multiplexer (MUX1) 620. At this time, each of the ROMs of the ROM bank 722 has a capacity of 2 ² . The second multiplexer (MUX2) 622 multiplexes the filter output value output from the ROM bank 722 according to the clock CLK3 of 4 times the symbol rate.

In FIG. 10, the 2: 1 MUX recalls the initial delay output [x (n)] of the first delay unit 702 and the final delay output [x (n−L + 1)] of the second delay unit 704. Multiplexing is performed according to the clock CLK3 of the symbol rate and the result of the multiplexing is output as a control signal CONT40. In addition, a plurality of multiplexers are shown in FIG. 10, each of which has (L / 2-3) bits of delay outputs [x (n-1) to x except for an initial delay output of the first delay unit 702. (nL / 2 + 3)] and delay outputs [x (n-L + 2) to x (nL / 2-2)] of the second delay unit 604 which are symmetrical with respect to these outputs. The signals are multiplexed and output according to the clock CLK3 four times the symbol rate. A plurality of exclusive logic sum circuits are connected to the rear ends of the multiplexers, and the plurality of exclusive logic sum circuits perform an exclusive logic operation on each output of the multiplexers and the control signal CONT40 and output these outputs (L / 2-3). Output as a bit address. As a result, the first signal processor 708 generates an address of (L / 2-3) bits.

)를 상기 심볼레이트의 4배 클럭(CLK3)에 따라 멀티플렉싱하여 출력한다. 제2롬뱅크(712)는 각각이 소정 탭수(N)에 따른 필터출력값들을 저장하고 있는 다수의 롬들(ROM #0∼#3)로 이루어지며, 도 10에 도시된 다수의 배타적 논리합회로에 의해 생성되는 (L/2-3)비트의 어드레스에 의해 억세스되는 필터출력값을 출력한다. 상기 제2롬뱅크(712)의 각 롬들은 2^(L/2-3)의 용량을 갖는다. 멀티플렉서(MUX4)(714)는 제2롬뱅크(712)의 각 롬들로부터 출력되는 필터출력값들을 제3멀티플렉서(710)의 출력에 따라 멀티플렉싱하여 출력한다. 제2신호처리부(716)는 멀티플렉서(MUX4)(714)로부터 출력되는 필터출력값들을 제어신호(CONT40)에 따라 2의 보수화처리하여 출력하거나 직접 출력한다. 상기 제2신호처리부(716)는 제어신호(CONT40)가 "하이"레벨인 경우에는 멀티플렉서(MUX4)(714)로부터 출력되는 필터출력값을 2의 보수화처리하여 출력하고, 상기 제어신호(CONT40)가 "로우"레벨인 경우에는 멀티플렉서(MUX4)(714)로부터 출력되는 필터출력값을 직접 출력하게 된다. 이렇게 처리된 필터출력값은 제2멀티플렉서(MUX)(726)로부터의 필터출력값과 합해진 후 레지스터(718) 및 가산기(720)로 인가된다. 상기 제2신호처리부(716)로부터의 출력은 레지스터(718)로 인가되어 일시적으로 저장되게 된다. 그리고 가산기(720)는 상기 레지스터(718)에 의해 일시적으로 저장된 필터출력값과 제2신호처리부(716)에 의해 처리된 필터출력값을 가산하여 필터 출력데이터(FO)로서 출력한다.In FIG. 7, the third multiplexer (MUX3) 710 includes a first output signal OUT and a second output signal (

) Is multiplexed and output according to the clock CLK3 of the symbol rate. The second ROM bank 712 is composed of a plurality of ROMs ROM # 0 to # 3, each of which stores filter output values according to a predetermined number of taps N, and is formed by a plurality of exclusive logical sum circuits shown in FIG. Outputs the filter output value accessed by the address of the generated (L / 2-3) bits. Each ROM of the second ROM bank 712 has a capacity of 2 ^{(L / 2-3)} . The multiplexer (MUX4) 714 multiplexes the filter output values output from the respective ROMs of the second ROM bank 712 according to the output of the third multiplexer 710. The second signal processing unit 716 outputs the filter output values output from the multiplexer (MUX4) 714 by complementary processing of 2 according to the control signal CONT40 or directly outputs them. When the control signal CONT40 is at the "high" level, the second signal processor 716 complements and outputs the filter output value output from the multiplexer (MUX4) 714 to 2, and the control signal CONT40 is output. In the "low" level, the filter output value output from the multiplexer (MUX4) 714 is output directly. The filter output value thus processed is combined with the filter output value from the second multiplexer (MUX) 726 and then applied to the register 718 and the adder 720. The output from the second signal processor 716 is applied to the register 718 to be temporarily stored. The adder 720 adds the filter output value temporarily stored by the register 718 and the filter output value processed by the second signal processor 716 to output the filter output data FO.

As described above, the FIR filter according to the second embodiment of the present invention requires only a Lombank having a capacity of 2 ^{L / 2-3 and} a ^{Lombank having} a capacity of 2 ² . Controlled by the double clock CLK3. Therefore, the capacity of the required memory can be reduced by half compared to the capacity of the memory required by the FIR filter shown in FIG. In addition, in the case of the FIR filter illustrated in FIG. 5, multiplexers 514, 516, 528, and 530 are required, but such multiplexers are not required. As a result, the FIR filter according to the third embodiment of the present invention provides the same filtering effect while having a reduced memory and a simplified configuration as compared to the FIR filter according to the first embodiment of the present invention.

As described above, according to the present invention, when the FIR filter is implemented using a mixed tap delay line method and a lookup table method, two delay lines each for accessing filter output values stored in two or four storage means are provided. Allows you to create memory addresses. Accordingly, the memory capacity required can be further reduced, and the number of components required for implementing the FIR filter can be further reduced.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

Claims (36)

In the finite field impulse response filter, A series of L / 2 delay elements connected to each other, each delay element having a first delay unit for sequentially delaying and outputting input data according to a predetermined symbol rate; It consists of a series of L / 2 delay elements in a symmetric relationship with respect to each delay element of the first delay unit, each delay element sequentially delays and outputs the delay output from the first delay unit in accordance with the symbol rate With the second delay, A first and second ROM banks each including a plurality of ROMs storing filter output values according to a predetermined number of taps; A third ROM bank comprising ROMs storing filter output values corresponding to an address that can be determined by the last two bit delay outputs of the first delay unit; A fourth ROM bank comprising ROMs storing filter output values corresponding to an address that can be determined by first two bit delay outputs of the second delay unit; Addressing any one of the filter output values stored in each of the ROMs of the first ROM bank using delay outputs of the remaining (L / 2-2) bits except the last two-bit delay output of the first delay unit. A first address generator for generating a first address for the first address; Addressing any one of the filter output values stored in each of the ROMs of the second ROM bank using delay outputs of the remaining (L / 2-2) bits except the first two-bit delay output of the second delay unit. A second address generation unit generating a second address for A first multiplexer and a third multiplexer for sequentially multiplexing the filter output values output from the first and third ROM banks according to an oversampling rate / 2 times the clock of the symbol rate; A second multiplexer and a fourth multiplexer for multiplexing and outputting filter output values output from the second and fourth ROM banks in a reverse order to the multiplexing order by the first and third multiplexers; A first filter output value processing unit for directly outputting the filter output values output from the first multiplexer and the third multiplexer or by performing two's complement processing; A second filter output value processor for directly outputting or outputting two's complement by outputting filter output values output from the second multiplexer and the fourth multiplexer; And an adder configured to add filter output values output from the first filter output value processor and the second filter output value processor to output as filter output data. The finite field impulse response filter according to claim 1, wherein each of the ROMs of the first and second ROM banks has a capacity of 2 ^{(L / 2-3)} . 3. The finite field impulse response filter of claim 2, wherein each of the third and second ROM banks has a capacity of 2 ² . The method of claim 1, wherein the first address generating unit inputs the delayed outputs of the remaining (L / 2-2) bits except the last two-bit delayed output of the first delay unit, and inputs the inputted (L / 2-2). According to the most significant bit value among the bit delay outputs, delay outputs of the remaining (L / 2-3) bits are directly generated as the first address or a complement of 1 to generate the processed result as the first address. Finite field impulse response filter, characterized in that. The 1st address generating unit according to claim 4, wherein the first address generation unit performs a 1's complement processing on the delayed outputs of the (L / 2-3) bits when the most significant bit value is greater than 2 ^{(L / 2-3)} . And a finite field impulse response filter characterized in that the result of the processing is generated as the first address. 5. The method of claim 4, wherein the first address generator is configured as a common input using the most significant bit value among the remaining (L / 2-2) bit delay outputs excluding the last 2 bit delay outputs of the first delay unit. A finite field impulse response filter comprising a plurality of exclusive logical sum circuits having different inputs of bit values of a delay stage, and generating the operation result of the plurality of exclusive logical sum circuits as the first address. 2. The second address generator of claim 1, wherein the second address generation unit inputs the delayed outputs of the remaining (L / 2-2) bits except for the first two-bit delayed outputs of the second delay unit. To generate the delayed outputs of the remaining (L / 2-3) bits directly as the second address or to perform one's complement processing according to the least significant bit value of the delayed outputs of the) bits to generate the processed result as the second address. Finite field impulse response filter, characterized in that. 8. The method of claim 7, wherein the second address generator is one's complement processing for the delayed outputs of the (L / 2-3) bits when the value of the least significant bit is greater than two ^{(L / 2-3).} A finite field impulse response filter, characterized in that the result of the processing is generated as the second address. 8. The method of claim 7, wherein the second address generator is configured to set the least significant bit value among the delay outputs of the remaining (L / 2-2) bits except the first two bit delay outputs of the second delay unit as one common input. A finite field impulse response filter comprising a plurality of exclusive logical sum circuits having different inputs of bit values in a delay stage, and generating a result of operation by the plurality of exclusive logical sum circuits as the second address. The third multiplexer according to claim 4, wherein the first filter output value processing unit performs two's complement processing on the filter output value from the first multiplexer when the most significant bit value is greater than two ^{(L / 2-3).} A finite field impulse response filter characterized in that it is output together with the filter output value from the. The fourth multiplexer according to claim 4, wherein the second filter output value processing unit performs two's complement processing on the filter output value from the second multiplexer when the least significant bit value is greater than two ^{(L / 2-3).} A finite field impulse response filter characterized in that it is output together with the filter output value from the. 12. The method according to any one of claims 1 to 11, wherein the clock is inputted and counted twice the symbol rate, and the count result is generated as a clock corresponding to an oversampling rate / 2 times the symbol rate. And a counter for applying one clock to the third multiplexer and the third multiplexer, and applying a clock to the third and fourth multiplexers according to the inverse count result. In the finite field impulse response filter, A series of L / 2 delay elements connected to each other, each delay element having a first delay unit for sequentially delaying and outputting input data according to a predetermined symbol rate; It consists of a series of L / 2 delay elements in a symmetric relationship with respect to each delay element of the first delay unit, each delay element sequentially delays and outputs the delay output from the first delay unit in accordance with the symbol rate With the second delay, A counter for counting a clock twice the symbol rate and outputting a first output signal representing the counting result and a second output signal representing the inverse counting result; A first multiplexer for multiplexing the final 2-bit delay output of the first delay unit and the first 2-bit delay output of the second delay unit according to a clock four times the symbol rate; A ROM bank each comprising ROMs storing filter output values corresponding to an address that can be determined by an output of the first multiplexer; A second multiplexer for multiplexing the filter output value output from the ROM bank according to a clock four times the symbol rate; A third multiplexer for multiplexing the first delayed output of the first delayed portion and the final delayed output of the second delayed portion according to a clock four times the symbol rate, and outputting the resulted signal as a control signal; The first output signal and the second output signal are multiplexed according to a clock four times the symbol rate to generate the multiplexing result as an address most significant bit value of two bits, except for the first delay output of the first delay unit (L). A plurality of multiplexers for multiplexing the delayed outputs of the &lt; RTI ID = 0.0 &gt; 2-3) bits &lt; / RTI &gt; (L / 2-3) exclusively performing an OR logic operation on each of the outputs of the multiplexers except for the multiplexer generating the most significant bit value of the address and the control signal and connecting these outputs to the most significant bit value of the address among the multiplexers. A plurality of exclusive OR circuits outputting the respective bit values of the bit, The filter output values are stored according to a predetermined number of taps, and are determined by the most significant bit value generated by the initial multiplexer of the multiplexer and the remaining (L / 2-3) bit values generated by the multiple exclusive OR circuits. A lookup table for outputting the filter output value accessed by the address of the (L / 2-1) bits; A filter output value processor for outputting the filter output values output from the lookup table and the second multiplexer by two's complementary processing or directly outputting the filter output values according to the control signal; A register for temporarily storing the output of the filter output value processor; And an adder which adds a filter output value temporarily stored by the register and a filter output value processed by the filter output value processing unit and outputs the filter output data as filter output data. 14. The finite field impulse response filter according to claim 13, wherein the lookup table has a capacity of 2 ^{(L / 2-1)} . 14. The finite field impulse response filter as claimed in claim 13, wherein each of the ROMs of the Rombank has a capacity of 2 ² . The filter output value processing unit of claim 13, wherein the filter output value processing unit outputs the filter output value output from the lookup table by two's complement when the control signal is at the "high" level, and when the control signal is at the "low" level. And a filter output value directly output from the lookup table. In the finite field impulse response filter, A series of L / 2 delay elements connected to each other, each delay element having a first delay unit for sequentially delaying and outputting input data according to a predetermined symbol rate; It consists of a series of L / 2 delay elements in a symmetric relationship with respect to each delay element of the first delay unit, each delay element sequentially delays and outputs the delay output from the first delay unit in accordance with the symbol rate With the second delay, A counter for counting a clock twice the symbol rate and outputting a first output signal representing the counting result and a second output signal representing the inverse counting result; A first multiplexer for multiplexing the final 2-bit delay output of the first delay unit and the first 2-bit delay output of the second delay unit according to a clock four times the symbol rate; A first ROM bank each of ROMs storing filter output values corresponding to an address that can be determined by an output of the first multiplexer; A second multiplexer for multiplexing the filter output value output from the first ROM bank according to a clock four times the symbol rate; A third multiplexer for multiplexing the first output signal and the second output signal according to a clock four times the symbol rate; A fourth multiplexer for multiplexing the first delayed output of the first delayed portion and the final delayed output of the second delayed portion according to a clock four times the symbol rate, and outputting the resultant as a control signal; The delayed outputs of the remaining (L / 2-3) bits except the first delayed output of the first delayed portion and the delayed outputs of the second delayed symmetrical with respect to these outputs according to a clock four times the symbol rate. Multiplexers that multiplex each output and A plurality of exclusive OR circuits for exclusively ORing the respective outputs of the plurality of multiplexers and the control signal and outputting these outputs as addresses; A second ROM bank each having a plurality of ROMs storing filter output values according to a predetermined number of taps and outputting a filter output value accessed by an address generated by the plurality of exclusive OR circuits; A fifth multiplexer configured to multiplex and output filter output values output from each ROM of the second ROM bank according to an output of the third multiplexer; A filter output value processing unit for outputting or directly outputting the filter output values output from the second multiplexer and the fifth multiplexer by two's complement processing according to the control signal; A register for temporarily storing the output of the filter output value processor; And an adder which adds a filter output value temporarily stored by the register and a filter output value processed by the filter output value processing unit and outputs the filter output data as filter output data. 18. The finite field impulse response filter of claim 17, wherein each of the ROMs of the first bank has a capacity of 2 ² . 18. The finite field impulse response filter according to claim 17, wherein each of the second ROM banks has a capacity of 2 ^{(L / 2-3)} . 18. The filter output value of claim 17, wherein the plurality of exclusive logical sum circuits comprise (L / 2-3) exclusive logical sum circuits, and the output of each exclusive logical sum circuit is stored in each of the ROMs of the second bank. A finite field impulse response filter, characterized in that it is generated and output as an address of (L / 2-3) bits for accessing. The filter output value processing unit according to claim 17, wherein the filter output value processing unit outputs the filter output value output from the lookup table by two's complement when the control signal is at the "high" level, and when the control signal is at the "low" level. And a filter output value directly output from the lookup table. A first delay bank comprising a plurality of ROMs storing a filter output value according to a predetermined number of taps, and a first delay for sequentially outputting the input data in an impulse form by delaying L / 2 steps according to a predetermined symbol rate. In the filtering method of the finite field impulse response filter comprising at least a second delay unit for delaying and outputting the final delay output from the first delay unit by L / 2 steps sequentially, The (L / 2-3) bit delay output values after the first delay output value by the first delay unit are directly or 1's complemented by the first delay output value by the first delay unit to generate them as a first address. (A) accessing a filter output value corresponding to the generated first address among the filter output values stored in the first ROM bank, and The (L / 2-3) bit delay output values after the first 2 bit delay output value of the second delay unit are directly or 1's complemented according to the final delay output value by the second delay unit to generate them as a second address. (B) accessing a filter output value corresponding to the generated second address among the filter output values stored in the second ROM bank, and (C) generating a final 2-bit delay output value by the first delay unit as a third address to access the filter output value stored in the second ROM bank; (D) generating a first 2-bit delay output value by the second delay unit as a fourth address to access a filter output value stored in the fourth ROM bank; (E) multiplexing the filter output values accessed in steps (a) and (c) according to the oversampling rate / 2 times the clock of the symbol rate; (F) multiplexing and outputting the filter output values accessed in steps (b) and (d) in a reverse order to the multiplexing order in step (e); (G) outputting the filter output values output in step (e) directly or by two's complement processing according to the initial delay output value by the first delay unit; (H) outputting the filter output values output in step (f) directly or by complementing two according to the final delay output value by the second delay unit; And (i) adding the filter output values output in steps (g) and (h) and outputting the addition result as filter output data. 23. The method of claim 22, wherein each of the ROMs of the first and second ROM banks has a capacity of 2 ^{(L / 2-3)} , and the first address and the first address of (L / 2-3) bits. And a filter output value accessed by two addresses. 23. The method of claim 22, wherein each of the ROMs of the third and fourth ROM banks has a capacity of 2 ² , and outputs a filter output value accessed by the third and fourth addresses of two bits. Characterized by a filtering method. 25. The method according to claim 23 or 24, wherein in the step (a), when the initial delay output value by the first delay unit is at the "high" level, after the initial delay output value by the first delay unit (L / 2-3) Complement the bit delay output values to 1 to generate it as the first address, and if the initial delay output value by the first delay unit is "low" level, the initial delay output value by the first delay unit. And subsequently generating (L / 2-3) bit delayed output values as the first address. 25. The method according to claim 23 or 24, wherein in the step (b), when the final delay output value by the second delay unit is at the "high" level, after the first 2 bit delay output value of the second delay unit (L / 2-3) Complement the bit delay output values to 1 to generate it as the second address, and when the final delay output value by the second delay unit is at the "low" level, the first 2 bit delay output value of the second delay unit is generated. And subsequently generating (L / 2-3) bit delayed output values as the second address. 26. The method of claim 25, wherein when the initial delay output value by the first delay unit is "high" level, the filter output values output in step (e) are processed by two's complement, and when the "low" level is directly applied. Filtering method characterized in that the output. 27. The method of claim 26, wherein when the final delay output value by the second delay unit is at the "high" level, the filter output values output in the step (f) are processed by the complementary processing of "2" and are at the "low" level. Filtering method characterized in that the output directly. A lookup table and a rombank storing filter output values according to a predetermined number of taps, and L / 2 delay elements, and a first step of delaying and outputting an impulse-type input data L / 2 steps sequentially according to a predetermined symbol rate. A second delay element comprising L / 2 delay elements corresponding to the delay elements of the first delay unit and sequentially delaying the final delay output from the first delay unit by L / 2 steps In the filtering method of a finite field impulse response filter including at least a part, (A) multiplexing the first delayed output value by the first delay unit and the final delayed output value by the second delay unit according to four times the symbol rate; (B) counting a clock twice the symbol rate according to a predetermined oversampling rate and outputting a first output signal representing the counting result and a second output signal representing the reverse order of the counting result; (C) multiplexing the first output signal and the second output signal according to a clock four times the symbol rate to generate the multiplexing result as a most significant bit value of a two-bit first address; (L / 2-3) bit delay output values after the first delay output value by the first delay unit and (L / 2-3 after the first two bit delay output values of the second delay unit corresponding to each of the delay output values. (D) multiplexing bit delay output values according to a clock four times the symbol rate and generating the multiplexing result as the remaining bit values of the first address; (E) accessing a filter output value corresponding to the first address of the (L / 2-1) bits generated in steps (c) and (d) among the filter output values stored in the lookup table and, (F) generating a multiplexing result as a second address by multiplexing the final 2-bit delay output value by the first delay unit and the first 2-bit delay output value by the second delay unit according to the quadruple clock of the symbol rate; , (G) accessing a filter output value corresponding to the second address among the filter output values stored in the ROM bank, (H) multiplexing and outputting the filter output value accessed in step (g) according to a clock four times the symbol rate; The filter output values output in step (h) may be directly output according to the signal generated in step (a) or after the complementary processing of 2 and output in combination with the filter output values output in step (e). Process, (J) temporarily storing the filter output values output in step (i); And (k) adding the filter output values output in step (i) and the filter output values temporarily stored in step (j) and outputting the addition result as filter output data. 30. The method of claim 29, wherein the lookup table has a capacity of 2 ^{(L / 2-1)} . 30. The method of claim 29, wherein each of the ROMs of the Rombank has a capacity of 2 ² . 30. The method of claim 29, wherein when the signal generated in the step (a) is the "high" level, the filter output values output in the step (h) are processed by two's complement, and when the "low" level, Filtering method characterized in that to directly output the filter output values output in step (h). The first and second ROM banks, each of which includes a plurality of ROMs storing filter output values according to a predetermined number of taps, and L / 2 delay elements, sequentially input L-type input data according to a predetermined symbol rate. The first delay unit outputs by delaying the second stage and L / 2 delay elements corresponding to the delay elements of the first delay unit, and sequentially L / As the final delay output from the first delay unit. In the filtering method of the finite field impulse response filter comprising at least a second delay portion for outputting by delaying two steps, (A) counting a clock twice the symbol rate according to a predetermined oversampling rate and outputting a first output signal indicating a counting result and a second output signal indicating a reverse order of the counting result; (B) multiplexing the first output signal and the second output signal according to a clock four times the symbol rate, and (C) multiplexing the first delayed output value by the first delay unit and the final delayed output value by the second delay unit according to a clock four times the symbol rate, and outputting the multiplexing result as a control signal; A delay output value of (L / 2-3) bits after the first delay output value by the first delay unit and a corresponding (L / 2-3) bit after a delay output value of the first two bits by the second delay unit corresponding thereto. (D) multiplexing and delaying the delayed output values of the delayed output values according to a clock four times the symbol rate, and The delayed output value of the last two bits by the first delay unit and the corresponding first two bits of the delayed output value by the second delay unit are multiplexed according to a clock four times the symbol rate, and the multiplexing result is used as the first address. (E) process of producing, (F) generating an exclusive logical sum of the respective values output from the step (d) and the control signal and generating the second address as a second address; (G) accessing and outputting a filter output value corresponding to the generated first address among filter output values stored in each ROM of the first ROM bank; (H) accessing and outputting a filter output value corresponding to the generated second address among filter output values stored in each ROM of the second ROM bank; (I) multiplexing and outputting the filter output value output in step (h) according to the signal output in step (b); (J) outputting the filter output value output in step (i) directly or by performing two's complement processing according to the control signal and adding the filter output value output in step (g); (K) temporarily storing the filter output value output in step (j); And (l) adding the filter output value output in step (j) and the filter output value temporarily stored in step (k) and outputting the addition result as filter output data. 34. The method of claim 33, wherein each of the first ROM banks has a capacity of 2 ² . 34. The method of claim 33, wherein each of the second ROM banks has a capacity of 2 ^{(L / 2-3)} . 34. The method of claim 33, wherein when the control signal is at the "high" level, the filter output value output at step (i) is processed by two's complement, and at the "low" level, the output is performed at step (i). Filtering method characterized in that the output directly outputted filter output value.

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