KR100260746B1 - Finite impulse response filter - Google Patents

Abstract

PURPOSE: A finite impulse response filter is provided which has a memory with a reduced capacity, decreases the size of hardware, and easily adjusts a clock rate controlling the filter to control the capacity of a ROM. CONSTITUTION: A finite impulse response filter generates an address for accessing a memory using two delay lines when data over-sampled m times during one symbol section is inputted. Each of the delay lines is divided into two parts to generate two memory addresses. Each of the generated address is sent to a storage or a storage divided into two. Accordingly, filter output values corresponding to the generated memory addresses are selected from a plurality of filter output values stored in the storage to be outputted. In case where the memory addresses are generated using the two delay lines, the capacity of required memory can be reduced.

Description

Finite field impulse response filter

The present invention relates to a digital filter, and more particularly, to a finite field impulse response filter in which a tapped delay line method and a lookup table method are mixed.

A typical filter used in a digital signal processing system is a finite impulse response (FIR) filter. FIR filters are currently being used in most digital signal processing systems because of their superior performance compared to analog filters and infinite impulse response filters. The FIR filter is classified into a tapped delay line type FIR filter and a look-up table type FIR filter according to the configuration.

FIG. 1 is a diagram illustrating a configuration of a FIR filter according to a tapped delay line method, and filtering is performed by performing a convolution. Referring to FIG. 1, when one input data is applied to the shift register 102, the applied filter input data is N input data together with N-1 input data previously inputted to the shift register 102. Form a line. The multipliers 104, 106, 108, ... 110 multiply the N input data and the N filter coefficients stored in the storage unit 112, respectively. The adder 114 then adds the results output from the respective multipliers 104, 106, 108, ..., 110 and outputs them as filter output data.

The FIR filter according to the tapped delay line method is currently most widely used. However, when the above-described filtering type is implemented in a parallel processing method, N multipliers and N-1 adders are required, which increases the hardware size. On the other hand, even when the above-described filtering type is implemented in a serial processing method, there is a disadvantage in that a high speed hardware implementation method is required because N multiplications and N-1 additions must be performed during a time when one input data is applied.

FIG. 2 is a diagram illustrating a configuration of a FIR filter based on a lookup table method. Referring to FIG. 2, a filter output value corresponding to N input combinations is calculated and stored in the ROM 206 in advance. At this time, if one data is applied to the shift register 202, the current filter input data forms N input data lines together with the N-1 input data previously input to the shift register 202. The address generator 204 then generates N input data as an address, and the filter output value stored in the ROM 206 corresponding to the generated address is output as the filter output data.

This type of filtering has the advantage that it is not necessary to use a multiplier when implementing the filter, and a high speed hardware implementation method is required. However, as the number of taps of the filter increases, the capacity of the ROM has to be increased accordingly.

Meanwhile, the applicant of the present application has already implemented a technique for solving the above disadvantages, that is, an FIR filter having a reduced capacity memory (ROM). The FIR filter implemented in this way was first filed on June 29, 1995, and then filed in priority application on June 12, 1996, under Korean Patent Application No. 96-21065 entitled "Limited Impulse Response Filter and Its Filtering Method." It is disclosed in detail. The FIR filter disclosed in the patent is an example of a combination of a tapped delay line method and a look-up table method, and reduces the existing ROM capacity from 2 ^L to m × 2 ^{L / 2} or 2 ^{L / 2 + 1} .

It is therefore an object of the present invention to provide a FIR filter that further reduces the size of the hardware.

Another object of the present invention is to provide a FIR filter having a memory of a reduced capacity.

Another object of the present invention is to provide a FIR filter that can adjust the capacity of a ROM according to various applications by freely adjusting the clock rate controlling the filter.

The present invention for achieving the above object proposes a FIR filter and a filtering method that is implemented by using a combination of the tapped delay line method and the lookup table method. The FIR filter according to the present invention generates an address for accessing the memory using two delay lines when m times oversampled data is input during one symbol period. At this time, each delay line is divided into two parts to generate two memory addresses. The generated addresses are provided to the storage means divided into one or two, respectively, so that the filter output values corresponding to the generated memory addresses are selected and output from the plurality of filter output values stored in these storage means. According to the present invention, it is possible to further reduce the capacity of a memory required when generating a memory address using two delay lines.

The FIR filter according to the first aspect of the present invention; A series of L / 2 (L is filter length) delay elements connected to each other, each delay element including a first delay unit for sequentially delaying and outputting input data according to a predetermined symbol rate; It consists of a series of L / 2 delay elements in a symmetric relationship with respect to each delay element of the first delay unit, each delay element is sequentially output delayed delay output from the first delay unit in accordance with the symbol rate A second delay unit; A first and second ROM banks each comprising a plurality of ROMs storing filter output values according to a predetermined tap number N; Are stored in each ROM of the first ROM bank by using the delay outputs of the remaining (L / 2-2) bits except for the first delay element of the first delay unit and the 2-bit delay output output through the next delay element. A first address generator for generating a first address for addressing any one of the filter output values; Are stored in each ROM of the second ROM bank using delay outputs of the remaining (L / 2-2) bits except the 2-bit delay outputs output through the last delay element and the previous delay element of the second delay unit. A second address generator for generating a second address for addressing any one of the filter output values; A first multiplexer for sequentially multiplexing the filter output value output from the first ROM bank according to an oversampling rate / 2 times the clock of the symbol rate; A second multiplexer for multiplexing and outputting the filter output value output from the second ROM bank in a reverse order to the multiplexing order by the first multiplexer; The filter outputs the filter output values directly outputted from the first multiplexer or the two's complement processing according to the values of the 2-bit delay outputs output through the first delay element and the next delay element of the first delay unit. A first filter output value processing unit for directly outputting an output value or adding and outputting a first preset value to the filter output value; The filter outputs the filter output values directly output from the second multiplexer or outputs by complementing two according to the values of the 2-bit delay outputs output through the last delay element and the previous delay element of the second delay unit. A second filter output value processing unit for directly outputting an output value or adding and outputting a second preset value to the filter output value; And an adder for adding the filter output values output from the first filter output value processor and the second filter output value processor to output as filter output data.

According to a second aspect of the present invention, a FIR filter includes: a series of L / 2 (L is filter length) delay elements connected to each other, and each delay element sequentially delays input data according to a predetermined symbol rate and outputs the delay elements. A first delay unit to perform; It consists of a series of L / 2 delay elements in a symmetric relationship with respect to each delay element of the first delay unit, each delay element is sequentially output delayed delay output from the first delay unit in accordance with the symbol rate A second delay unit; A counter for counting a clock twice the symbol rate and outputting a first output signal representing the counting result and a second output signal representing the inverse counting result; A look-up table storing filter output values according to a predetermined number of taps (N); Delay outputs of the remaining (L / 2-2) bits except the first delay element of the first delay unit and the 2-bit delay output output through the next delay element, the last delay element of the second delay unit, and the previous delay element Delay outputs of the remaining (L / 2-2) bits other than the 2-bit delay output output through the second delay output and the second delay output through the first delay element and the next delay element of the first delay unit; L / 2 for addressing the filter output value stored in the lookup table by combining a delay output of 2 bits output through the last delay element and the previous delay element of the delay unit with the first output signal and the second output signal. An address generator for generating a bit address; According to the bit values of the 2-bit delay output output through the first delay element and the next delay element of the first delay unit and the 2-bit delay output output through the last delay element and the previous delay element of the second delay unit; A filter output value processing unit for directly outputting or outputting the filter output values addressed and output from the lookup table, and outputting the outputted filter output value directly or adding the preset value to the filter output value; A register for temporarily storing the output of said filter output value processor; And an adder which adds the filter output value temporarily stored by the register and the filter output value processed by the filter output value processing unit and outputs the filter output data as filter output data.

According to a third aspect of the present invention, a FIR filter includes: a series of L / 2 (L is filter length) delay elements connected to each other, and each delay element sequentially delays input data according to a predetermined symbol rate and outputs the delay elements. A first delay unit to perform; It consists of a series of L / 2 delay elements in a symmetric relationship with respect to each delay element of the first delay unit, each delay element is sequentially output delayed delay output from the first delay unit in accordance with the symbol rate A second delay unit; A counter for counting a clock twice the symbol rate and outputting a first output signal representing the counting result and a second output signal representing the inverse counting result; A first multiplexer for multiplexing the first output signal and the second output signal according to a clock four times the symbol rate; A first ROM bank comprising a plurality of ROMs storing filter output values according to a predetermined tap number N; A second ROM bank composed of a plurality of ROMs storing preset values and outputting a set value stored in one ROM according to a multiplexing result of the first multiplexer; Delay outputs of the remaining (L / 2-2) bits except the first delay element of the first delay unit and the 2-bit delay output output through the next delay element, the last delay element of the second delay unit, and the previous delay element Delay outputs of the remaining (L / 2-2) bits other than the 2-bit delay output output through the second delay output and the second delay output through the first delay element and the next delay element of the first delay unit; (L / 2) for addressing the filter output value stored in the first ROM bank by combining the delayed output of the 2-bit outputted through the delayed delay element and the delayed delay element and the 4-fold clock of the symbol rate. An address generator for generating an address of bits; A second multiplexer for multiplexing and outputting a filter output value addressed and output from the first ROM bank according to a multiplexing result by the first multiplexer; According to the bit values of the 2-bit delay output output through the first delay element and the next delay element of the first delay unit and the 2-bit delay output output through the last delay element and the previous delay element of the second delay unit; After directly outputting or outputting the filter output values output from the second multiplexer, or by performing two's complement processing, the outputted filter output value is directly output or the filter output value is added by adding a set value addressed and output from the second ROM bank. A filter output value processor; A register for temporarily storing the output of said filter output value processor; And an adder which adds the filter output value temporarily stored by the register and the filter output value processed by the filter output value processing unit and outputs the filter output data as filter output data.

1 is a block diagram of a finite field impulse response filter according to a tapped delay line method.

2 is a block diagram of a finite field impulse response filter according to a lookup table method;

3 is a diagram illustrating a configuration of a modulator of a binary data transmission system to which a finite field impulse response filter according to the present invention can be applied.

4 is a diagram illustrating a form of data input to a filter illustrated in FIG. 3.

5 is a block diagram of a finite field impulse response filter according to a first embodiment of the present invention;

6 is a block diagram of a finite field impulse response filter according to a second embodiment of the present invention;

7 is a block diagram of a finite field impulse response filter according to a third embodiment of the present invention;

FIG. 8 is a detailed configuration diagram of a first signal processor and a second signal processor illustrated in FIG. 5.

FIG. 9 is a detailed configuration diagram of the first signal processing unit shown in FIG. 6.

FIG. 10 is a detailed configuration diagram of the first signal processing unit shown in FIG. 7.

11 is a view showing the operation timing of the finite field impulse response filter according to the first embodiment of the present invention.

12 is a view showing operation timing of a finite field impulse response filter according to a second embodiment of the present invention.

13 is a view showing the operation timing of the finite field impulse response filter according to the third embodiment of the present invention;

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are used as much as possible even if displayed on different drawings. In addition, in the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to the intention or custom of the user or chip designer, and the definitions should be made based on the contents throughout the present specification. In the following, L represents the filter length, m represents the oversampling rate, N represents the number of filter taps, and n represents the number of bits of data output from the ROM. FI represents the input data of the filter, FO represents the output data of the filter. The first clock CLK1 represents a clock of symbol rate, the second clock CLK2 represents a clock twice the symbol rate, and the third clock CLK3 represents a clock four times the symbol rate. The control signal CONT3 is a signal according to the counting result of the second clock CLK2, and the control signal CONT4 represents a reverse order of the result of counting the second clock CLK2. The control signal CONT3 is a signal inverted.

First, before describing the FIR filter according to the present invention, a modulator of a binary data transmission system to which the present invention can be applied will be described.

3 shows a configuration of a modulator of a binary data transmission system, wherein the modulator includes low pass filters 306 and 308. The low pass filters 306 and 308 usually use sections having a length of L as the filter length, and the sections are oversampled by m times to be implemented by a digital filter having N (L × m) filter taps. Can be. The present invention can be applied not only to the implementation of the low pass filters 306 and 308 included in the modulator of the binary data transmission system, but also to the implementation of all filters that accept data in the form of pulses mapped to ± 1 impulses. have. In FIG. 3, the signal mapping unit 304 provides a filter input form mapped to an impulse of ± 1.

On the other hand, when the digital filter is designed to have a linear phase characteristic, the filter coefficient values are usually designed to have symmetry. The symmetry of the filter coefficients means that, for example, when the filter coefficient values are 5, C-2, C-1, C0, C1, and C2, the values of C-2 and C2 are the same, and C-1 and C1 It means the same value. It should be noted that the filter coefficient values according to the present invention are also designed to have the same symmetry.

FIG. 4 is a diagram showing the type of input data applied to the low pass filters 306 and 308, in which m-fold oversampled signals are input during one symbol period. That is, the first sample of one symbol section has the actual value "± 1" mapped by the signal mapping unit 304, and the remaining m-1 samples have the form of "0". Since the input data of this type is applied to the low pass filters 306 and 308, one filter output value is obtained after L multiplications and L-1 additions are performed during one oversampling time in the low pass filters 306 and 308. During the symbol interval, m filter outputs are obtained after the multiplication by mL and the addition of m (L-1) are performed. If the FIR filter performing the above operation is to be implemented according to the lookup table method as shown in FIG. 2, the required ROM will have a capacity of ^2L .

The m filter output values output during the one symbol section in the low pass filter 306 are multiplied by the carrier wave oscillated in the local oscillator 310 and the multiplier 312, and the one symbol section in the low pass filter 308. M filter output values, which are output during the multiplication process, are oscillated by the local oscillator 310 and then multiplied by the carrier 316 multiplied by a phase shifter π / 2 by the phase shifter 314. The result of multiplication by the multiplier 312 and the multiplier 316 is added by the adder 318 and then output as a transmission signal.

Next, the configuration and operation of the FIR filter according to the present invention will be described in detail for each embodiment.

First embodiment

5 is a view showing the configuration of the FIR filter according to the first embodiment of the present invention, Figure 8 is a view showing a specific configuration of the first signal processing unit 506 and the second signal processing unit 508 shown in FIG. 11 is a view showing the operation timing of the FIR filter according to the first embodiment.

Referring to FIG. 5, the FIR filter of the present invention includes delay units 502 and 504, signal processors 506, 508, 518, 520, ROM banks 510, 512, 524, 526, multiplexers 514, 516, adders 522, and counters 528. It is made to include. The delay unit 502 is formed by connecting a series of L / 2 delay elements, and each delay element sequentially delays and outputs input data according to a predetermined symbol rate CLK1. The delay unit 504 is composed of a series of L / 2 delay elements that are symmetrical with respect to each delay element of the first delay unit 502, and each delay element is the first according to the symbol rate CLK1. The delayed output from the delay unit 502 is sequentially delayed and output.

신호로서 출력한다. 여기서 OUT신호 및

신호는 심볼레이트의 오버샘플링레이트/2배에 해당하는 클럭으로, OUT신호는 제1멀티플렉서(514) 및 제3롬뱅크(524)에 CONT3신호로서 인가되고

신호는 제2멀티플렉서(516) 및 제4롬뱅크(526)에 CONT4신호로서 인가된다.Each of the first and second ROM banks 510 and 512 includes a plurality of ROMs that store filter output values according to a predetermined number of taps (N). Here, each of the ROMs of the first and second ROM banks 502 and 504 has a capacity of 2 ^{(L / 2-2)} . The counter 528 inputs and counts the clock CLK2 twice the symbol rate, and then outputs the count result to the OUT signal.

Output as a signal. Where OUT signal and

The signal is a clock corresponding to an oversampling rate / 2 times the symbol rate, and the OUT signal is applied to the first multiplexer 514 and the third ROM bank 524 as a CONT3 signal.

The signal is applied to the second multiplexer 516 and the fourth ROM bank 526 as a CONT4 signal.

The first signal processing unit 506 has the remainder except for the 2-bit delay output output through the first delay element x (n) and the next delay element x (n-1) of the first delay unit 502 ( A delay output of the L / 2-2) bits is used to generate an address for addressing any one of the filter output values stored in each ROM of the first ROM bank 510. The second signal processor 508 outputs two bits output through the last delay element [x (n-L + 1)] and the previous delay element [x (n-L + 2)] of the second delay unit 504. Generating an address for addressing any one of the filter output values stored in the respective ROMs of the second ROM bank 512 using the delay outputs of the remaining (L / 2-2) bits except the delay output. Play a role. The first signal processor 506 and the second signal processor 508 are configured as shown in FIG. 8, and operations thereof will be apparent from the following description.

The first multiplexer 514 sequentially multiplexes the filter output value output from the first ROM bank 510 according to the CONT3 signal from the counter 528. The second multiplexer 516 sequentially multiplexes the filter output value output from the second ROM bank 512 according to the CONT4 signal output from the counter 528.

The third signal processor 518 directly outputs or outputs the filter output values output from the first multiplexer 514 according to the control signals CONT10, CONT11, and CONT12 applied from the first signal processor 506. The processed filter output value is directly output to the adder 522 or the set value outputted from the third ROM bank 524 is added to the processed filter output value and output to the adder 522. At this time, the control signals CONT10, CONT11, and CONT12 are generated by the first signal processor 506, and the first delay element [x (n)] and the next delay element [x (n-1) of the first delay unit 502. ] Depends on the values of the 2-bit delayed output. The third ROM bank 524 is composed of ROMs corresponding to the first ROM bank 510. Each of the ROMs stores preset values, which are stored by the CONT3 signal output from the counter 528. Will be output.

The fourth signal processing unit 520 directly outputs or outputs the filter output values output from the second multiplexer 516 according to the control signals CONT20, CONT21, and CONT22 applied from the second signal processing unit 508. The processed filter output value is directly output to the adder 522 or the set value outputted from the fourth ROM bank 526 is added to the processed filter output value and output to the adder 522. At this time, the control signals CONT20, CONT21, and CONT22 are generated by the second signal processing unit 508, and the final delay element [x (n-L + 1)] and the previous delay element [x () of the second delay unit 504. n-L + 2)] is determined according to the values of the 2-bit delay output. The fourth ROM bank 526 is composed of ROMs corresponding to the second ROM bank 512. Each of the ROMs stores preset values, and the stored setting values are generated by the CONT4 signal output from the counter 528. Will be output.

The FIR filter configured as shown in FIG. 5 has four specific values (2 × h [0], 2 × h [1], 2 × h [2]) to further reduce the capacity of the ROM banks 510 and 512. And auxiliary ROMs 524 and 526 for storing 2xh [3]).

First, the present invention divides a delay line for storing data (0 or 1 corresponding to ± 1) into every first symbol section into a first delay unit 502 and a second delay unit 504, thereby combining the number of memory addresses. To reduce from 2 ^L to (2 ^{L / 2} +2 ^{L / 2} ). Such a method is a technique disclosed under Korean Patent Application No. 96-21065, titled "Limited Impulse Response Filter and its Filtering Method," filed previously by the present applicant as described in the prior art.

In addition, the present invention allows the data once inputted to be maintained for one symbol period as an address necessary to calculate m filter output values, that is, the delay line is operated by the symbol clock CLK1, and the first ROM bank 510 and The counter outputs of the modulo-3 counter 528 operated by the m / 2 times the symbol rate of the second ROM bank 512, that is, the clock rate CLK2 of the symbol rate in FIG. According to the present invention, the CONT3 and CONT4 control the outputs of the multiplexers 514 and 516, the third and second ROM banks 524 and 526, and then add the respective outputs to the adder 522. M filter values are output.

The process of acquiring m filter output values while maintaining the once input data for one symbol period obtains the same result as performing m convolution while shifting the data input to the delay units 502 and 504 m times for one symbol period. Since the positions of the N filter output values are fixedly stored in the first and second ROM banks 510 and 512, the L filter coefficient values multiplied by the actual data values when m filter output values are calculated are also m. It is fixed corresponding to the number of times. These operations are summarized in Table 1 below.

division Filter coefficient values corresponding to the first delay unit 502 Filter coefficient values corresponding to the second delay unit 504 n = 0n = 1 · n = m-2n = m-1 h [0], h [n + m],... … … , h [n + (L / 2-1) m] h [1], h [n + m + 1],... H [n + (L / 2-1) m] ... h [m-2], h [n + 2m-2],... , h [n + (L / 2-1) m] h [m-1], h [n + 2m-1],... , h [n + (L / 2-1) m] h [n + (L / 2-1) m],... , h [n + 2m-1], h [m-1] h [n + (L / 2-1) m],... h [n + 2m-2], h [m-2] .h [n + (L / 2-1) m]; … , h [n + m + 1], h [1] h [n + (L / 2-1) m],... … H [n + m], h [0]

Referring to Table 1, the array of filter coefficient values by which the non-zero filter input values of the delay unit 504 are multiplied when m = 0 is the filter coefficient value of the delay unit 502 when m = m-1. It can be seen that the positional arrangement of the filter coefficient values of the delay unit 504 in the reverse order with respect to the arrangement of the sigma units is equal to the positional arrangement of the filter coefficient values of the delay unit 502 when m = m-2. have. m = 2,... The same rule applies when, m = m-1. Therefore, the output values of the second ROM bank 512 output by the address generated by the delay unit 504 may be obtained as values stored in the first ROM bank 510. Therefore, in FIG. 5, it can be concluded that all desired filter output values can be obtained using only one memory bank of the first and second ROM banks 510 and 512.

It is the first signal processing unit 506 and the second signal processing unit 508 that can be configured as a plurality of exclusive logical sum circuits as shown in FIG. 8 to enable the operation described above. The first signal processing unit 506 uses the most significant bit MSB (x [n]) of the address determined by the delay unit 502 as the control signal CONT10 to form a common input of the exclusive OR circuits, and the delay unit. The values of the other addresses determined by 502 are different inputs of the exclusive OR circuits, and perform the complementary operation of 1 when the control signal indicates an address larger than 2L / 2-1. After this operation is completed, the complementary operation of 1 is repeated once again for the remaining bits except the most significant bit by using the exclusive logical sum output value of the next higher bit (x [n-1]) as the control signal CONT11. In this way, the first signal processing unit 506 uses the three control signals CONT10, CONT11, and CONT12 that control the third signal processing unit 518, and a (L / 2-2) bit memory address for the first ROM bank 510. Generates. The second signal processing unit 508 uses the most significant bit MSB (x [n-L + 1]) of the address determined by the delay unit 504 as the control signal CONT20 to serve as a common input of the exclusive logical sum circuits. The values of the other addresses determined by the delay unit 504 are different inputs of the exclusive OR circuits, and when the control signal indicates an address larger than 2L / 2-1, a complementary operation of 1 is performed. After this operation is completed, the complementary operation of 1 is repeated once again for the remaining bits except the most significant bit by using the exclusive OR value of the next higher bit (n [n-L + 2]) as the control signal CONT21. In this way, the second signal processing unit 508 controls the three control signals CONT20, CONT21, and CONT22 that control the fourth signal processing unit 520, and the (L / 2-2) bit memory addresses for the second ROM bank 512. Generates.

Configuring the first signal processing unit 506 and the second signal processing unit 508 to perform the above operation is because the actual values multiplied by the filter coefficient values are ± 1, the binary data of L / 2 bits constituting the binary address Given that the values are symmetric about a 2L / 2-1 value, the memory stored values specified by addresses greater than or equal to 2L / 2-1 are equal to two of the memory stored values specified by addresses less than 2L / 2-1. Memory stored values specified by an address more than 2L / 2-2, which are obtained by calculating the complement, are also specified by a complement value of 2 of the memory stored values specified by an address less than 2L / 2-2. X h [0], 2 x h [1], 2 x h [2], and 2 x h [3]). Therefore, the memory capacity can be reduced once again to 2L / 2-2.

To make the process easier, I will use an example of a 48-tap FIR filter with M = 4 and L = 12. In this case, the process of obtaining four filter output values while maintaining the data once input for one symbol section CLK1 is as follows.

Taking into account the symmetry of the FIR filter coefficient values, the filter coefficient values multiplied by the input data values of the first delay line 502 and the second delay line 504 are arranged according to the value of m as shown in Table 2 below. Can be.

Filter coefficient values corresponding to the first delay unit 502 Filter coefficient values corresponding to the second delay unit 504 m = 0 (0) h [0], h [4], h [8], h [12], h [16], h [20] (3) 'h [23], h [19], h [15], h [11], h [7], h [3] m = 1 H [1], h [5], h [9], h [13], h [17], h [21] (2) 'h [22], h [18], h [14], h [10], h [6], h [2] m = 2 (2) h [2], h [6], h [10], h [14], h [18], h [22] (1) 'h [21], h [17], h [13], h [9], h [5], h [1] m = 3 H [3], h [7], h [11], h [15], h [19], h [23] (0) 'h [20], h [16], h [12], h [8], h [4], h [0]

Referring to Table 2, the filter coefficient values multiplied by the data of the second delay unit 504 when m = 0 is multiplied by the data of the first delay unit 502 when m = 3. It can be seen that the filter coefficient values are in the reverse order, and when m = 1, m = 2, m = 2, m = 1, and m = 3, m = 1. Therefore, since the filter input data values multiplied corresponding to the filter coefficient values are ± 1, the filter output values pre-calculated and stored in the first and second ROM banks 510 and 512 may be configured with the same data. . That is, the first and second ROM banks 510 and 512 are the same ROM banks in which the same filter output value is stored at the same address.

Now, the filtering process of the first delay unit 502 with m = 0 will be described. In this case, since the number of input data is six (L / 2 = 12/2), the total number of memory addresses is 2 ⁶ = 64. However, since the filter input data input through the delay line part has a value of ± 1 (a value mapped to 0 → 1,1 → -1 and may be reversely mapped), the input data value is (1,1,1 , 1,1,1), i.e., (-1, -1, -1, -1, -1, -1), the filter output value is (0,0,0,0,0, 0), i.e., (+ 1, + 1, + 1, + 1, + 1, + 1), can be obtained by taking two's complement of the corresponding filter output value. This process is expressed as follows.

Filter output (111111) = -h [0] -h [4] -h [8] -h [12] -h [14] -h [18]

=-{h [0] + h [4] + h [8] + h [12] + h [14] + h [18]}

=-{Filter output (000000)}

Filter output (100000) = -h [0] + h [4] + h [8] + h [12] + h [14] + h [18]

=-{h [0] -h [4] -h [8] -h [12] -h [14] -h [18]}

=-{Filter out (011111)}

Therefore, as shown in Equation 1 and Equation 2, the filter output values when the combination of input data is 32 (100000) or more are the filter output values when the combination of input data is 31 (011111) or less. It can be seen that it can be obtained simply by taking 2's complement. In other words, this means that filtering corresponding to 64 address combinations can be performed with only 32 address combinations.

In addition, filter output values corresponding to 16 (10000) or more and 31 (11111) or less address combinations have a complementary value of 2 when the address combination is 15 (01111) or less. ], 2xh [1], 2xh [2], and 2xh [3]. This process is expressed as follows.

Filter output (011111) = h [0] -h [4] -h [8] -h [12] -h [16] -h [20]

= 2h [0]-{h [0] + h [4] + h [8] + h [12] + h [16] + h [20]}

= 2h [0]-{filter output (000000)}

Filter output (010000) = h [0] -h [4] + h [8] + h [12] + h [16] + h [20]

= 2h [0]-{h [0] + h [4] -h [8] -h [12] -h [16] -h [20]}

= 2h [0]-{filter output (001111)}

Therefore, as shown in Equations 3 and 4, the filter output values when the combination of input data is 16 (010000) or more and 31 (011111) or less are 16 (010000). It can be seen that it is simply obtained by taking two's complement to the filter output values in the following cases and adding a specific value thereto. In other words, this means that filtering corresponding to 32 address combinations can be performed with only 16 address combinations.

Combining these two processes, we will describe the overall process of obtaining 64 filter outputs using only 16 address combinations.

Filter output (100000) = -h [0] + h [4] + h [8] + h [12] + h [16] + h [20]

=-{h [0] -h [4] -h [8] -h [12] -h [16] -h [20]}

=-{Filter output (011111)}

=-{2h [0] -filter output (000000)}

Filter output (101111) = -h [0] + h [4] -h [8] -h [12] -h [16] -h [20]

=-{h [0] -h [4] + h [8] + h [12] + h [16] + h [20]}

=-{Filter out (010000)}

=-{2h [0] -filter (001111)}

Therefore, as shown in Equations 5 and 6, the filter output values when the combination of input data is 16 (010000) or more are the filter output values when the combination of input data is 16 (010000) or less. It can be seen that it can be obtained simply by using. In other words, this means that filtering corresponding to 64 address combinations can be performed with only 16 address combinations.

Table 3 below shows values stored in the first ROM bank 510 corresponding to the 48-tap FIR filter. In this case, m = 0.

ROM ADDRESS Saved value (filter output value) 0 h [0] + h [4] + h [8] + h [12] + h [16] + h [20] One h [0] + h [4] + h [8] + h [12] + h [16] -h [20] 2 h [0] + h [4] + h [8] + h [12] -h [16] + h [20] 3 h [0] + h [4] + h [8] + h [12] -h [16] -h [20] 4 h [0] + h [4] + h [8] -h [12] + h [16] + h [20] 5 h [0] + h [4] + h [8] -h [12] + h [16] -h [20] 6 h [0] + h [4] + h [8] -h [12] -h [16] + h [20] 7 h [0] + h [4] + h [8] -h [12] -h [16] -h [20] 8 h [0] + h [4] -h [8] + h [12] + h [16] + h [20] 9 h [0] + h [4] -h [8] + h [12] + h [16] -h [20] 10 h [0] + h [4] -h [8] + h [12] -h [16] + h [20] 11 h [0] + h [4] -h [8] + h [12] -h [16] -h [20] 12 h [0] + h [4] -h [8] -h [12] + h [16] + h [20] 13 h [0] + h [4] -h [8] -h [12] + h [16] -h [20] 14 h [0] + h [4] -h [8] -h [12] -h [16] + h [20] 15 h [0] + h [4] -h [8] -h [12] -h [16] -h [20]

So far, the operation of the present invention has been briefly described with an example of a 48-tap FIR filter. The third signal processing unit 518 and the fourth signal processing unit 520 enable such an operation. The third signal processor 518 and the fourth signal processor 520 receive the control signals CONT10, CONT11, CONT12, CONT20, CONT21, and CONT22 from the first signal processor 506 and the second signal processor 508. By performing the operation according to the combination of Table 4 below, the intermediate filter output value input to the adder 522 is finally generated.

CONT10 (CONT20) CONT11 (CONT21) CONT12 (CONT22) Output of third signal processor (or fourth signal processor) 0 0 0 1st bank output value (2nd bank output value) + 0 0 One One -1 rom bank output value (-2 rom bank output value) + 3 rd bank output value (4 rom bank output value) One 0 One -1 rom bank output value (-2 rom bank output value) + 0 One One One 1st Roman Bank Output Value (2nd Roman Bank Output Value)-3rd Roman Bank Output Value (4th Roman Bank Output Value)

출력: 3,2,1,0,3,2,1,0 …)를 제2멀티플렉서(516)를 제어하는 제어신호로서 사용하여 제1멀티플렉서(514)의 출력값과의 동기를 맞추도록 하였다. 즉 제1멀티플렉서(514)가 CONT3에 의해 제1롬뱅크(510)의 #0 출력값을 선택하면, 제2멀티플렉서(516)는 CONT4에 의해 제2롬뱅크(512)의 #3 출력값을 선택하도록 함으로써 m=0일 때의 전체 필터출력값을 얻도록 한 것이다. 또한 이러한 CONT3,CONT4 제어신호는 제3롬뱅크(524)와 제4롬뱅크(526)의 메모리 어드레스로서 사용되어 제3신호처리부(518)와 제4신호처리부(520)로 적절한 값을 멀티플렉서(514,516)와 동기가 맞은 상태에서 공급하는 역할을 하고 있다.Finally, a first multiplexer 514 and a second multiplexer 516 associated with CONT3 and CONT4 will now be described. As described above, the filter coefficient values multiplied with the input data of the second delay unit 504 when m = 0 is multiplied by the input data of the first delay unit 502 when m = 3. Of the control signal CONT3 (the OUT output of the counter 524: 0,1,2,3,0,1, ...) of the control signal CONT4 (counter 524) that controls the first multiplexer 154.

Output: 3,2,1,0,3,2,1,0... ) Is used as a control signal for controlling the second multiplexer 516 to synchronize with the output value of the first multiplexer 514. That is, when the first multiplexer 514 selects the # 0 output value of the first rombank 510 by CONT3, the second multiplexer 516 selects the # 3 output value of the second rombank 512 by CONT4. By doing this, the total filter output value is obtained when m = 0. In addition, the CONT3 and CONT4 control signals are used as memory addresses of the third and second ROM banks 524 and 526, so that the third signal processor 518 and the fourth signal processor 520 may use multiplexers. 514,516) is in sync with the supply.

In summary, the FIR filter according to the present invention generates a memory address through two delay lines when the m times oversampled signal is input for one symbol period, and is already stored in two storage means. Among the filter output values, the filter output value corresponding to the generated memory address is selected and output. Accordingly, the memory capacity required for implementing a filter having a filter length L, the number of taps N, and the oversampling ratio m can be reduced from ^2L to ( ^{2L / 2-2} ) × m.

As described above, the FIR filter described above is related to a filter that can be implemented only by a double clock speed CLK2 of the symbol rate CLK1 and can significantly reduce the amount of memory required. Hereinafter, a filter that can significantly reduce the memory capacity required for the filter implementation by using a clock speed four times greater than the symbol rate will be described in detail with reference to FIGS. 6 and 7. Of course, since the basic principles of FIGS. 6 and 7 are the same as those of FIG. 5 described above, overlapping descriptions will not be repeated.

As shown in FIGS. 6 and 7, when the clock CLK3 of symbol rate is used, the required memory capacity can be reduced to 1/2 again compared to the method of FIG. If a faster clock rate is used, for example, using eight times the symbol rate, two different filters can be implemented using only the memory capacity of one filter using four times the clock. .

Second embodiment

FIG. 6 is a diagram illustrating a configuration of an FIR filter according to a second embodiment of the present invention. FIG. 9 is a diagram illustrating a detailed configuration of the first signal processing unit 608 shown in FIG. 6, and FIG. FIG. 3 illustrates an operation timing of an FIR filter according to an embodiment. FIG.

The FIR filter shown in FIG. 6 uses a clock CLK3 four times the symbol rate compared to the FIR filter shown in FIG. 5, and uses the clock to multiplex the addresses supplied to each ROM bank. Also, by constructing a lookup table 610 having a connected address without using the separate ROM bank used in FIG. 5, the need for the first multiplexer 514 and the second multiplexers 516 required in FIG. 5 is eliminated. Overall, the hardware size can be reduced. An embodiment in which the first signal processor 608 of FIG. 6 is implemented in this manner is illustrated in FIG. 9, and the operation timing of the FIR filter according to the embodiments of FIGS. 6 and 9 is illustrated in FIG. 12. As shown. Referring to FIG. 9, the first of FIG. 5 is used except for multiplexing the addresses using the clock CLK3 four times the symbol rate and using the output of the external modulo-3 counter 606 to generate the addresses. It can be seen that the signal processing unit 506 and the second signal processing unit 508 has the same structure as the implementation method. In addition, the second signal processor 612 of FIG. 6 also performs the same functions as those of the third signal processor 518 and the fourth signal processor 520 of FIG. 5, that is, the operations shown in <Table 4>.

)를 출력한다. 룩업테이블(610)은 소정 탭수(N)에 따른 필터출력값들을 저장하고 있으며, 2^L/2의 용량을 갖는다.Referring to FIG. 6, the FIR filter according to the second embodiment of the present invention includes first and second delay units 602 and 604, first and second signal processors 608 and 612, a lookup table 610, and a counter 606. And a multiplexer 620, a rombank 618, a register 614, and an adder 616. The first delay unit 602 is formed by connecting a series of L / 2 (L is the filter length) delay elements, and each delay element sequentially delays and outputs the input data according to a predetermined symbol rate CLK1. . The second delay unit 604 is composed of a series of L / 2 delay elements that are symmetrical with respect to each delay element of the first delay unit 602, and each delay element is determined according to the symbol rate CLK1. The delayed output from the first delay unit 602 is sequentially delayed and output. The counter 606 counts the clock CLK2 twice the symbol rate, and outputs the first output signal OUT indicating the counting result and the second output signal indicating the inverse counting result.

) The lookup table 610 stores filter output values according to the predetermined tap number N, and has a capacity of 2 ^{L / 2} .

신호를 조합하여 룩업테이블(608)에 저장되어 있는 필터출력값을 어드레싱하기 위한 L/2비트의 어드레스를 생성한다. 이러한 동작은 신호처리부(608)가 도 9에 도시된 바와 같이 구성됨으로써 가능하다.The first signal processor 608 generates an address for addressing the filter output value stored in the lookup table 610. That is, the first signal processor 608 excludes the 2-bit delay output output through the first delay element x (n) and the next delay element x (n-1) of the first delay unit 602. Delay outputs of the remaining (L / 2-2) bits and the last delay element [x (n-L + 1)] and the previous delay element [x (n-L + 2)] of the second delay unit 604. The delayed outputs of the remaining (L / 2-2) bits except for the 2-bit delayed outputs through the first delay unit 602 of the first delay unit 602 and the next delayed element [x (n 2 bits of delay output and the last delay element [x (n-L + 1)] of the second delay unit 604 and the previous delay element [x (n-L + 2)]. 2-bit delay output and OUT signal from counter 606

The signals are combined to generate an L / 2 bit address for addressing the filter output value stored in the lookup table 608. This operation is possible by the signal processing unit 608 configured as shown in FIG.

신호를 입력하여 상기 심볼레이트의 4배 클럭(CLK3)에 따라 멀티플렉싱하여 출력한다. 그리고 나머지 다수의 멀티플렉서들(914∼917)은 제1지연부(602)의 최초 지연소자 및 그 다음 지연소자를 통해 출력되는 2비트 지연출력을 제외한 나머지 (L/2-2)비트의 지연출력 데이터들과, 이 지연출력 데이터 각각에 대응하는 제2지연부(604)의 최종 지연소자 및 그 이전 지연소자를 통해 출력되는 2비트 지연출력을 제외한 나머지 (L/2-2)비트의 지연출력 데이터들을 상기 심볼레이트의 4배 클럭(CLK3)에 따라 멀티플렉싱하여 출력한다.Referring to FIG. 9, the multiplexer 911 includes delay output data through the first delay element [x (n)] of the first delay unit 602 and a final delay element [x (n−L + 1) of the second delay unit. ) Is multiplexed according to the clock CLK3 of the symbol rate, and the result of the multiplexing is output as the control signal CONT30. The multiplexer 912 includes delay output data through the delay element [x (n-1)] after the first delay element of the first delay unit 602 and the delay element [before the last delay element of the second delay unit 604]. Delay output data through x (n-L + 2)] is multiplexed and output according to the clock CLK3 of the symbol rate. Multiplexer 913 is configured to output signals from counter 606 and

The signal is input and multiplexed according to the clock CLK3 of the symbol rate and output. The remaining multiplexers 914 to 917 are delayed outputs of the remaining (L / 2-2) bits except for the 2-bit delay outputs output through the first delay element and the next delay element of the first delay unit 602. Delayed output of (L / 2-2) bits except for the 2-bit delayed output through the data and the last delayed element of the second delay unit 604 corresponding to each of the delayed output data and the previous delayed element. The data are multiplexed and output according to the clock CLK3 of the symbol rate.

The exclusive OR circuit 918 performs an exclusive OR operation on the output of the first multiplexer 911 and the output of the second multiplexer 912 and outputs the second control signal CONT31. The exclusive logic sum circuit 919 performs an exclusive logic sum operation on the first control signal CONT30 and the second control signal CONT32 and outputs it as the third control signal CONT33. The exclusive OR circuits 920 to 923 are (L / 2-2) exclusive OR circuits corresponding to the multiplexers 914 to 917, respectively, and the first control signal CONT30 is one common input and the multiplexers are provided. Each of the outputs is taken as another input (914 to 917), and the result of the exclusive logical operation is outputted. Exclusive logical sum circuits 924 to 927 are (L / 2-2) exclusive logical sum circuits corresponding to each of the plurality of exclusive logical sum circuits 920 to 923, and the second control signal CONT31 is used as one common input. Each output of the exclusive OR circuits 920 to 923 is used as another input, and the result of the exclusive OR operation is output. The 2-bit output value from the multiplexer 913 and the (L / 2-2) bit output value from the exclusive OR circuits 924 to 927 are addresses for addressing the filter output value stored in the lookup table 610. Is output.

The second signal processor 612 directly outputs or complements two of the filter output values addressed and output from the lookup table 610 according to the control signals CONT30, CONT31, and CONT32 generated by the first signal processor 608. After outputting, the outputted filter output value is directly outputted, or the filter output value is added to the set value outputted from the rombank 618. Here, the control signals CONT30, CONT31, and CONT32 are 2-bit delays output through the first delay element [x (n)] and the next delay element [x (n-1)] of the first delay unit 602, as described above. Output and the bit values of the 2-bit delay output output through the last delay element [x (n-L + 1)] and the previous delay element [x (n-L + 2)] of the second delay unit 604. The signal is determined by the combination.

The second signal processor 612 performs the same operation as shown in Table 4 above. That is, the second signal processor 612 directly outputs the filter output value output from the lookup table 610 when the first control signal CONT30, the second control signal CONT31, and the third control signal CONT32 are all at a "low" level. do. When the first control signal CONT30 is at the "low" level and the second control signal CONT31 and the third control signal CONT32 are at the "high" level, the second signal processing unit 612 outputs the filter output value output from the lookup table 610. 2 is complemented and the set value outputted from the ROM bank 618 is added to this complemented result. When the second control signal CONT31 is at the "low" level and the first control signal CONT30 and the third control signal CONT32 are at the "high" level, the second signal processing unit 612 outputs the filter output value output from the lookup table 610. 2 is complemented and outputted. When the first control signal CONT30, the second control signal CONT31, and the third control signal CONT32 are all at the "high" level, the second signal processing unit 612 complements the set value output from the ROM bank 618 by two. The addition result is added after the filter output value output from the lookup table 610 is added to the complementary result.

신호를 심볼레이트의 4배 클럭(CLK3)에 따라 멀티플렉싱하여 롬뱅크(618)로 출력한다. 롬뱅크(618)는 각각이 미리 설정된 값을 저장하고 있는 다수의 롬들로 이루어지며 멀티플렉서(620)로부터의 출력값에 따라 상기 다수의 롬중 어느 한 롬에 저장되어 있는 값을 제2신호처리부(612)로 출력한다. 레지스터(614)는 제2신호처리부(612)로부터 출력되는 필터출력값을 일시적으로 저장한다. 가산기(616)는 상기 레지스터(614)에 의해 일시적으로 저장된 필터출력값과 제2신호처리부(612)에 의해 처리된 필터출력값을 가산하여 필터 출력데이터로 FO서 출력한다.Multiplexer 620 receives the OUT signal from counter 606 and

The signal is multiplexed according to the clock rate CLK3 four times the symbol rate and output to the ROM bank 618. The ROM bank 618 is composed of a plurality of ROMs, each of which stores a predetermined value, and the second signal processor 612 stores a value stored in any one of the plurality of ROMs according to an output value from the multiplexer 620. Will output The register 614 temporarily stores the filter output value output from the second signal processor 612. The adder 616 adds the filter output value temporarily stored by the register 614 and the filter output value processed by the second signal processor 612 to output the FO as filter output data.

Third embodiment

7 is a view showing the configuration of the FIR filter according to a third embodiment of the present invention, FIG. 10 is a view showing the specific configuration of the first signal processing unit 708 shown in FIG. 7, and FIG. 13 is the third FIG. 3 illustrates an operation timing of an FIR filter according to an embodiment. FIG.

The FIR filter illustrated in FIG. 7 is designed to have a structure similar to that of the FIR filter illustrated in FIG. 5. A first signal processor 708 using one ROM bank 712 and one multiplexer 714 to generate addresses input to the first ROM bank 712 using a quadratic clock CLK3 of symbol rate. ) And the output values of modulo-3 counter 706. The FIR filter has a structure similar to that of the FIR filter shown in FIG. 5 but has the same memory capacity as the FIR filter shown in FIG. 6.

Referring to FIG. 7, the FIR filter according to the third embodiment of the present invention includes delay units 702 and 704, signal processors 708 and 716, ROM banks 712 and 722, multiplexers 710 and 714, and counters 706. , A register 718, and an adder 720. The first delay unit 702 is formed by connecting a series of L / 2 (L is filter length) delay elements, and each delay element sequentially delays and outputs the input data according to a predetermined symbol rate CLK1. . The second delay unit 704 is composed of a series of L / 2 delay elements that are symmetrical with respect to each delay element of the first delay unit 702, and each delay element is formed according to the symbol rate CLK2. The delayed output from the one delay unit 702 is sequentially delayed and output.

신호를 출력한다. 멀티플렉서(710)는 상기 카운터(706)로부터 출력되는 OUT신호와

신호를 심볼레이트의 4배 클럭(CLK3)에 따라 멀티플렉싱하여 CONT43신호를 출력한다. 제1롬뱅크(712)는 소정 탭수(N)에 따른 필터출력값들을 저장하고 있는 다수의 롬들로 이루어진다. 이 제1롬뱅크(712)의 각 롬들은 2^(L/2-2)의 용량을 갖는다. 제2롬뱅크(722)는 미리 설정된 값들을 저장하고 있는 다수의 롬들로 이루어지며 멀티플렉서(710)의 멀티플렉싱 결과인 CONT43신호에 따라 어느 한 롬에 저장되어 있는 설정값을 출력한다.The counter 706 counts the clock CLK2 twice the symbol rate and indicates the OUT signal indicating the counting result and the inverse counting result.

Output the signal. The multiplexer 710 is connected to the OUT signal output from the counter 706.

The CONT43 signal is output by multiplexing the signal according to the clock CLK3 of the symbol rate. The first ROM bank 712 includes a plurality of ROMs that store filter output values according to a predetermined tap number N. FIG. Each of the ROMs of the first ROM bank 712 has a capacity of 2 ^{(L / 2-2)} . The second ROM bank 722 is composed of a plurality of ROMs which store preset values, and outputs a set value stored in one ROM according to the CONT43 signal which is a result of multiplexing of the multiplexer 710.

The first signal processing unit 708 generates an address of (L / 2-2) bits for addressing the filter output value stored in the first ROM bank 712. That is, the first signal processing unit 708 excludes the 2-bit delay output output through the first delay element x (n) and the next delay element x (n-1) of the first delay unit 702. Delay outputs of the remaining (L / 2-2) bits and the last delay element [x (n-L + 1)] and the previous delay element [x (n-L + 2)] of the second delay unit 704. The delay outputs of the remaining (L / 2-2) bits except for the 2-bit delay output output through the first delay element [x (n)] and the next delay element [x (n) of the first delay unit 702 are output. 2 bits of delay output and the last delay element [x (n-L + 1)] and the previous delay element [x (n-L + 2)] of the second delay unit 704. The address of the (L / 2-2) bit for addressing the filter output value stored in the first ROM bank 712 in combination with the 2-bit delay output outputted through the 4-bit clock (CLK3) and the symbol rate. Create This operation is possible by the first signal processing unit 708 configured as shown in FIG.

Referring to FIG. 10, the first signal processing unit 708 includes multiplexers 1001 to 1005 and exclusive logic circuits 1006 to 1013. The multiplexer 1001 stores delay output data [x (n) through the first delay element of the first delay unit 702 and delay output data [x (n-L) through the last delay element of the second delay unit 704. +1)] is multiplexed according to the clock CLK3 four times the symbol rate, and this multiplexing result is output as the first control signal CONT40. The multiplexer 1002 stores the delay output data [x (n-1)] through the delay element after the first delay element of the first delay unit 702 and the delay element before the final delay element of the second delay unit 704. The delayed output data [x (n-L + 2)] is multiplexed according to the clock CLK3 of the symbol rate and output. The multiplexers 1003 to 1005 are delayed output data of the remaining (L / 2-2) bits except for the 2-bit delay outputs output through the first delay element and the next delay element of the first delay unit 702. And (L / 2-2) bits of delay output data except for the 2-bit delay output output through the last delay element and the previous delay element of the second delay unit 704 corresponding to each of the delay output data. The signals are multiplexed according to the clock signal CLK3 of the symbol rate and output.

The exclusive logical sum circuit 1006 performs an exclusive logical sum operation on the output of the first control signal CONT40 and the multiplexer 1002 and outputs the second control signal CONT41. The exclusive logic sum circuit 1007 performs an exclusive logic sum operation on the first control signal CONT40 and the second control signal CONT41 and outputs it as the third control signal CONT42. The plurality of exclusive OR circuits 1008 to 1010 are (L / 2-2) exclusive OR circuits corresponding to each of the multiplexers 1003 to 1005, and the first control signal CONT40 is one common input. The outputs of each of the multiplexers 1003 to 1005 are the other inputs, and are output by performing exclusive logical operation on them. The plurality of exclusive OR circuits 1011 to 1013 are (L / 2-2) exclusive OR circuits corresponding to each of the exclusive OR circuits 1008 to 1010, and the second control signal CONT41 is used as one common input. Each of the outputs of the exclusive OR circuits 1008 to 1010 is taken as another input, and the exclusive OR is performed. At this time, the operation results of the exclusive OR circuits 1008 to 1010 are output as addresses of (L / 2-2) bits for addressing the first ROM bank 712.

The multiplexer 714 multiplexes the filter output value addressed and output from the first ROM bank 712 according to the CONT43 signal, which is a result of the multiplexing by the multiplexer 710.

The second signal processor 716 directly outputs or outputs the filter output values output from the multiplexer 714 according to the control signals CONT40, CONT41, and CONT42 generated by the first signal processor 708, and then complements the two. The filter output value is directly output or the set value addressed and output from the second ROM bank 722 is added to the filter output value. As described above, the control signals CONT40, CONT41, and CONT42 include a 2-bit delay output and a final delay element of the second delay unit 704, which are output through the first delay element of the first delay unit 702 and the next delay element. It is determined by the bit values of the 2-bit delay output output through the previous delay element.

The second signal processor 716 performs the same operation as shown in Table 4 above. That is, the second signal processor 716 directly outputs the filter output value output from the multiplexer 714 when the first control signal CONT40, the second control signal CONT41, and the third control signal CONT42 are all at a "low" level. When the first control signal CONT40 is at the "low" level and the second control signal CONT41 and the third control signal CONT42 are at the "high" level, the second signal processing unit 716 outputs the filter output value output from the multiplexer 714. And the set value outputted from the second ROM bank 722 is added to this maintenance result. When the second control signal CONT41 is at the "low" level and the first control signal CONT40 and the third control signal CONT42 are at the "high" level, the second signal processor 716 outputs the filter output value output from the multiplexer 714. Complement the output to output. When the first control signal CONT40, the second control signal CONT41, and the third control signal CONT42 are all at the "high" level, the second signal processor 716 complements the set value output from the second ROM bank 722 by two. The filter output value output from the multiplexer 714 is added to this complementary result, and this addition result is output.

The register 718 temporarily stores the filter output value output from the second signal processor 716. The adder 720 adds the filter output value temporarily stored by the register 718 and the filter output value processed by the second signal processor 716 to output the filter output data FO.

As described above, the present invention generates a memory address through two delay lines, and taps for selecting and outputting filter output values corresponding to the generated memory addresses among filter output values previously stored in one or two storage means. A delay line method and a lookup table method provide a mixed FIR filter. Accordingly, the memory capacity required can be further reduced, and the number of components required for implementing the FIR filter can be further reduced.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

Claims (26)

For finite field impulse response filters: A series of L / 2 (L is filter length) delay elements connected to each other, each delay element including a first delay unit for sequentially delaying and outputting input data according to a predetermined symbol rate; It consists of a series of L / 2 delay elements in a symmetric relationship with respect to each delay element of the first delay unit, each delay element is sequentially output delayed delay output from the first delay unit in accordance with the symbol rate A second delay unit; A first and second ROM banks each comprising a plurality of ROMs storing filter output values according to a predetermined tap number N; Are stored in each ROM of the first ROM bank by using the delay outputs of the remaining (L / 2-2) bits except for the first delay element of the first delay unit and the 2-bit delay output output through the next delay element. A first address generator for generating a first address for addressing any one of the filter output values; Are stored in each ROM of the second ROM bank using delay outputs of the remaining (L / 2-2) bits except the 2-bit delay outputs output through the last delay element and the previous delay element of the second delay unit. A second address generator for generating a second address for addressing any one of the filter output values; A first multiplexer for sequentially multiplexing the filter output value output from the first ROM bank according to an oversampling rate / 2 times the clock of the symbol rate; A second multiplexer for multiplexing and outputting the filter output value output from the second ROM bank in a reverse order to the multiplexing order by the first multiplexer; The filter outputs the filter output values directly outputted from the first multiplexer or the two's complement processing according to the values of the 2-bit delay outputs output through the first delay element and the next delay element of the first delay unit. A first filter output value processing unit for directly outputting an output value or adding and outputting a first preset value to the filter output value; The filter outputs the filter output values directly output from the second multiplexer or outputs by complementing two according to the values of the 2-bit delay outputs output through the last delay element and the previous delay element of the second delay unit. A second filter output value processing unit for directly outputting an output value or adding and outputting a second preset value to the filter output value; And an adder configured to add filter output values output from the first filter output value processor and the second filter output value processor to output as filter output data. The finite field impulse response filter according to claim 1, wherein each of the ROMs of the first and second ROM banks has a capacity of 2 ^{(L / 2-2)} . The method of claim 1, wherein the first address generating unit, A first complementary processor for outputting the data of the remaining (L / 2-1) bits by one's complement or directly outputting the data of the remaining (L / 2-1) bits according to the bit value of the data output through the first delay element of the first delay unit; According to the result of the complement by the first complementer for the data output through the delay element after the first delay element of the first delay unit, the complementary results of the remaining (L / 2-2) bits by the first complementer are set to 1; A finite field impulse response filter, characterized in that it consists of a second complementary firearm for outputting the complementary output or directly outputting the same as the first address. 4. The method of claim 3, wherein the first complementarizer is configured for the delayed outputs of the remaining (L / 2-1) bits when the bit value of the data output through the first delay element of the first delay unit is at the "high" level. A finite field impulse response filter, characterized by performing a complementary processing of 1 to output. The method of claim 3, wherein the second complementarizer has a remainder when the result of the complementarization of the first complementarizer for data output through the delay element after the first delay element of the first delay unit is "high" level. 2-2) a complementary impulse response filter characterized in that it is generated as the first address by performing a complement of 1 on bits of complementary results. The method of claim 3, wherein the first complementarizer is configured to generate data output through the first delay element of the first delay unit as one common input and to use the remaining (L / 2-1) bits of data as different inputs (L). / 2-1) finite field impulse response filter, characterized in that implemented by two exclusive logic circuit. 4. The second complementarizer of claim 3, wherein the second complementarizer uses one common input as a result of the complementation of the first complementarizer for data output through the delay element after the first delay element of the first delay unit. 2-2) is implemented by (L / 2-2) exclusive OR circuits having different inputs of bits of data, and outputs the outputs of the exclusive OR circuits as the second address. filter. The method of claim 1, wherein the second address generating unit, A first complementary processor for outputting the data of the remaining (L / 2-1) bits by one's complement or directly outputting the data of the remaining (L / 2-1) bits according to the bit value of the data output through the last delay element of the second delay unit; According to the complementary result of the first complementarizer for the data output through the delay element before the last delay element of the second delay unit, the complementary results of the remaining (L / 2-2) bits of the first complementarizer are set to 1's. A finite field impulse response filter, characterized in that it consists of a second complementary firearm for outputting it by complementary output or by directly outputting it as the second address. 10. The method of claim 8, wherein the first complementarizer is configured for the delay outputs of the remaining (L / 2-1) bits when the bit value of the data output through the last delay element of the second delay unit is at the "high" level. A finite field impulse response filter, characterized by performing a complementary processing of 1 to output. 10. The method of claim 8, wherein the second complementarizer has a remainder when the result of the complementarization of the first complementarizer for data output through the delay element before the last delay element of the first delay unit is "high" level. 2-2) a complementary impulse response filter characterized in that it is generated as the second address by performing a complement of 1 on bits of complementary results. 10. The apparatus of claim 8, wherein the first complementarizer is configured to output data output through the last delay element of the second delay unit as one common input and to use the remaining (L / 2-1) bits of data as different inputs (L). / 2-1) finite field impulse response filter, characterized in that implemented by two exclusive logic circuit. 10. The method of claim 8, wherein the second complementarizer comprises one common input of the complementary result of the first complementarizer for data output through the delay element before the last delay element of the second delay unit as one common input. 2-2) is implemented by (L / 2-2) exclusive OR circuits having different inputs of bits of data, and outputs the outputs of the exclusive OR circuits as the second address. filter. The method of claim 3, wherein the first filter output value processing unit, A first operation value obtained by performing an exclusive logical operation on an output value through the first delay element of the first delay unit, an output value through the first delay element of the first delay unit, and an output value through the delay element following the first delay element, and the first When the output value through the first delay element of the delay unit and the second operation value obtained by the exclusive logical summation of the first operation value are both at the "low" level, the filter output value output from the first multiplexer is directly output to the adder, When the output value through the first delay element of the first delay unit is at the "low" level, and the first operation value and the second operation value are the "high" level, the filter output value output from the first multiplexer is complemented by two. Process and add the first set value to the complementary result, and output the addition result to the adder; When the first operation value is "low" level and the output value through the first delay element of the first delay unit and the second operation value are "high" level, the filter output value output from the first multiplexer is complemented by two. Process and output to the adder, When the output value through the first delay element of the first delay unit, the first operation value and the second operation value are all at the "high" level, the first set value is complemented by two, and the first complementary value is converted into the complementary result. And adding the filter output value outputted from the multiplexer and outputting the addition result to the adder. The method of claim 8, wherein the second filter output value processing unit, A first operation value obtained by performing an exclusive logical operation on an output value through the last delay element of the second delay unit, an output value through the last delay element of the second delay unit, and an output value through the delay element before the last delay element, and the second When the output value through the final delay element of the delay unit and the second operation value obtained by the exclusive logical operation of the first operation value are both at the "low" level, the filter output value output from the second multiplexer is directly output to the adder, When the output value through the last delay element of the second delay unit is at the "low" level, and the first operation value and the second operation value are the "high" level, the filter output value output from the second multiplexer is complemented by two. Process and add the second set value to the complementary result, and output the addition result to the adder; When the first operation value is "low" level and the output value through the last delay element of the second delay unit and the second operation value are "high" level, the filter output value output from the second multiplexer is complemented by two. Process and output to the adder, If the output value, the first operation value and the second operation value through the final delay element of the second delay unit are all at the "high" level, the second set value is complemented by two and the second complementary result is the second complementary result. And adding the filter output value outputted from the multiplexer and outputting the addition result to the adder. 15. The method of any one of claims 1 to 14, wherein the clock is inputted and counted twice the symbol rate, and the count result is generated as a clock corresponding to an oversampling rate / 2 times the symbol rate. And a counter for applying a clock to the first multiplexer and applying a clock according to the inverse count result to the second multiplexer as a second clock. 16. The apparatus of claim 15, further comprising a third ROM bank corresponding to each of the ROMs of the first ROM bank, each of the ROMs having a predetermined value, wherein the third ROM bank is connected to the first clock. And a set value stored in one ROM determined by the first output value as the first set value. 16. The system of claim 15, further comprising a fourth ROM bank corresponding to each of the ROMs of the second ROM bank, each of the ROMs having a predetermined value, wherein the fourth ROM bank is connected to the second clock. And outputting the set value stored in any one ROM determined by the second set value as the second set value. In the finite field impulse response filter, A series of L / 2 (L is filter length) delay elements connected to each other, each delay element including a first delay unit for sequentially delaying and outputting input data according to a predetermined symbol rate; It consists of a series of L / 2 delay elements in a symmetric relationship with respect to each delay element of the first delay unit, each delay element is sequentially output delayed delay output from the first delay unit in accordance with the symbol rate A second delay unit; A counter for counting a clock twice the symbol rate and outputting a first output signal representing the counting result and a second output signal representing the inverse counting result; A look-up table storing filter output values according to a predetermined number of taps (N); Delay outputs of the remaining (L / 2-2) bits except the first delay element of the first delay unit and the 2-bit delay output output through the next delay element, the last delay element of the second delay unit, and the previous delay element Delay outputs of the remaining (L / 2-2) bits other than the 2-bit delay output output through the second delay output and the second delay output through the first delay element and the next delay element of the first delay unit; L / 2 for addressing the filter output value stored in the lookup table by combining a delay output of 2 bits output through the last delay element and the previous delay element of the delay unit with the first output signal and the second output signal. An address generator for generating a bit address; According to the bit values of the 2-bit delay output output through the first delay element and the next delay element of the first delay unit and the 2-bit delay output output through the last delay element and the previous delay element of the second delay unit; A filter output value processing unit for directly outputting or outputting the filter output values addressed and output from the lookup table, and outputting the outputted filter output value directly or adding the preset value to the filter output value; A register for temporarily storing the output of the filter output value processor; And an adder which adds a filter output value temporarily stored by the register and a filter output value processed by the filter output value processing unit and outputs the filter output data as filter output data. 19. The finite field impulse response filter of claim 18, wherein the lookup table has a capacity of 2 ^{L / 2} . The method of claim 18, A multiplexer for inputting the first output signal and the second output signal and multiplexing the input signals according to a clock four times the symbol rate; Each of the ROMs includes a plurality of ROMs storing preset values. The ROM bank outputs a value stored in any one of the plurality of ROMs to the filter output value processor according to the output value from the multiplexer. Finite field impulse response filter, characterized in that consisting of. The method of claim 20, wherein the address generator, Multiplexing the delay output data through the first delay element of the first delay unit and the delay output data through the last delay element of the second delay unit according to a clock four times the symbol rate and outputting the multiplexing result as a first control signal; The first multiplexer, Multiplexing the delayed output data through the delay element after the first delay element of the first delay unit and the delayed output data through the delay element before the last delay element of the second delay unit according to a clock four times the symbol rate. 2 multiplexer, A third multiplexer for multiplexing the first output signal and the second output signal according to a clock four times the symbol rate; Delay output data of the remaining (L / 2-2) bits except for the 2-bit delay outputs outputted through the first delay element and the next delay element of the first delay unit, and the corresponding delay output data respectively. A plurality of delay output data of the (L / 2-2) bits other than the 2-bit delay output output through the last delay element and the previous delay element of the second delay unit are multiplexed and output according to a clock 4 times the symbol rate. Multiplexer, A first exclusive logic sum circuit for performing an exclusive logic operation on the output of the first multiplexer and the output of the second multiplexer and outputting the result as a second control signal; A second exclusive logic sum circuit for performing an exclusive logic sum operation on the first control signal and the second control signal and outputting the result as a third control signal; (L / 2-2) exclusive logical sum circuits corresponding to each of the multiplexers, wherein the first control signal is one common input and the output of each of the multiplexers is another input. A first group exclusive logical sum circuit for outputting the exclusive logical sum operation; (L / 2-2) exclusive logical sum circuits corresponding to each of the first group exclusive logical sum circuits, the second control signal being one common input, and each exclusive logical sum of the first group exclusive logical sum circuit. It consists of a second group exclusive logical sum circuit that outputs the circuit as another input and outputs them by performing an exclusive logical sum operation. And outputting the 2-bit output value from the third multiplexer and the (L / 2-2) bit output value from the second group exclusive OR circuit as an address for addressing the lookup table. The method of claim 21, wherein the filter output value processing unit, When the first control signal, the second control signal and the third control signal are all at the "low" level, the filter output value output from the lookup table is directly output. When the first control signal is at the "low" level and the second control signal and the third control signal are at the "high" level, the filter output value output from the lookup table is complemented by two, and the complementary result is displayed. The set value outputted from the ROM bank is added and outputted. When the second control signal is at the "low" level and the first control signal and the third control signal are at the "high" level, the filter output value output from the lookup table is processed by two's complement, and is output. When the first control signal, the second control signal and the third control signal are all at the "high" level, the set value output from the ROM bank is complemented by 2 and is output from the lookup table in the complementary result. A finite field impulse response filter, characterized by adding the filter output value and outputting this addition result. In the finite field impulse response filter, A series of L / 2 (L is filter length) delay elements connected to each other, each delay element including a first delay unit for sequentially delaying and outputting input data according to a predetermined symbol rate; It consists of a series of L / 2 delay elements in a symmetric relationship with respect to each delay element of the first delay unit, each delay element is sequentially output delayed delay output from the first delay unit in accordance with the symbol rate A second delay unit; A counter for counting a clock twice the symbol rate and outputting a first output signal representing the counting result and a second output signal representing the inverse counting result; A first multiplexer for multiplexing the first output signal and the second output signal according to a clock four times the symbol rate; A first ROM bank comprising a plurality of ROMs storing filter output values according to a predetermined tap number N; A second ROM bank composed of a plurality of ROMs storing preset values and outputting a set value stored in one ROM according to a multiplexing result of the first multiplexer; Delay outputs of the remaining (L / 2-2) bits except the first delay element of the first delay unit and the 2-bit delay output output through the next delay element, the last delay element of the second delay unit, and the previous delay element Delay outputs of the remaining (L / 2-2) bits other than the 2-bit delay output output through the second delay output and the second delay output through the first delay element and the next delay element of the first delay unit; (L / 2) for addressing the filter output value stored in the first ROM bank by combining the delayed output of the 2-bit outputted through the delayed delay element and the delayed delay element and the 4-fold clock of the symbol rate. An address generator for generating an address of bits; A second multiplexer for multiplexing and outputting a filter output value addressed and output from the first ROM bank according to a multiplexing result by the first multiplexer; According to the bit values of the 2-bit delay output output through the first delay element and the next delay element of the first delay unit and the 2-bit delay output output through the last delay element and the previous delay element of the second delay unit; After directly outputting or outputting the filter output values output from the second multiplexer, or by performing two's complement processing, the outputted filter output value is directly output or the filter output value is added by adding a set value addressed and output from the second ROM bank. A filter output value processor; A register for temporarily storing the output of the filter output value processor; And an adder which adds a filter output value temporarily stored by the register and a filter output value processed by the filter output value processing unit and outputs the filter output data as filter output data. 24. The finite field impulse response filter as claimed in claim 23, wherein each of the first ROM banks has a capacity of 2 ^{(L / 2-2)} . The method of claim 23, wherein the address generator, Multiplexing the delay output data through the first delay element of the first delay unit and the delay output data through the last delay element of the second delay unit according to a clock four times the symbol rate and outputting the multiplexing result as a first control signal; The third multiplexer, Multiplexing the delayed output data through the delay element after the first delay element of the first delay unit and the delayed output data through the delay element before the last delay element of the second delay unit according to a clock four times the symbol rate. 4 multiplexer, Delay output data of the remaining (L / 2-2) bits except for the 2-bit delay outputs outputted through the first delay element and the next delay element of the first delay unit, and the corresponding delay output data respectively. A plurality of delay output data of the (L / 2-2) bits other than the 2-bit delay output output through the last delay element and the previous delay element of the second delay unit are multiplexed and output according to a clock 4 times the symbol rate. Multiplexer, A first exclusive logic sum circuit for performing an exclusive logic operation on the outputs of the first control signal and the fourth multiplexer and outputting the second control signal as a second control signal; A second exclusive logic sum circuit for performing an exclusive logic sum operation on the first control signal and the second control signal and outputting the result as a third control signal; (L / 2-2) exclusive logical sum circuits corresponding to each of the multiplexers, wherein the first control signal is one common input and the output of each of the multiplexers is another input. A first group exclusive logical sum circuit for outputting the exclusive logical sum operation; (L / 2-2) exclusive logical sum circuits corresponding to each of the first group exclusive logical sum circuits, the second control signal being one common input, and each exclusive logical sum of the first group exclusive logical sum circuit. And a second group exclusive OR circuit which uses the output of the circuit as another input and performs an exclusive logical operation on these, and outputs the operation result as an address of (L / 2-2) bits for addressing the first ROM bank. Finite field impulse response filter. The method of claim 25, wherein the filter output value processing unit, When the first control signal, the second control signal and the third control signal are all at the "low" level, the filter output value output from the second multiplexer is directly output. When the first control signal is at the "low" level and the second control signal and the third control signal are at the "high" level, the filter output value output from the second multiplexer is subjected to two's complement, and the result of the complementary result is obtained. Adds and outputs a set value output from the second bank; When the second control signal is at the "low" level and the first control signal and the third control signal are at the "high" level, the filter output value output from the second multiplexer is output by two's complement processing. When the first control signal, the second control signal and the third control signal are all at the "high" level, the set value outputted from the second ROM bank is complemented by 2 and the second multiplexer is applied to the complementary result. A finite field impulse response filter characterized by adding the filter output value outputted from the output unit and outputting this addition result.

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