KR20010063848A - Manufacturing method for metal line contact of semiconductor device - Google Patents
Manufacturing method for metal line contact of semiconductor device Download PDFInfo
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- KR20010063848A KR20010063848A KR1019990061952A KR19990061952A KR20010063848A KR 20010063848 A KR20010063848 A KR 20010063848A KR 1019990061952 A KR1019990061952 A KR 1019990061952A KR 19990061952 A KR19990061952 A KR 19990061952A KR 20010063848 A KR20010063848 A KR 20010063848A
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- conductive layer
- forming
- insulating film
- metal wiring
- wiring contact
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 95
- 239000002184 metal Substances 0.000 title claims abstract description 95
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000010410 layer Substances 0.000 claims abstract description 115
- 239000011229 interlayer Substances 0.000 claims abstract description 53
- 238000000034 method Methods 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000001465 metallisation Methods 0.000 description 4
- 239000010949 copper Substances 0.000 description 3
- 230000003685 thermal hair damage Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 금속배선 콘택 형성방법에 관한 것으로서, 특히 금속배선 콘택과 다결정실리콘층 계면의 접촉영역을 증가시켜 콘택특성을 향상시키는 반도체소자의 금속배선 콘택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal interconnection contact of a semiconductor device, and more particularly, to a method for forming a metal interconnection contact of a semiconductor device to improve contact characteristics by increasing a contact area between a metallization contact and a polysilicon layer interface.
일반적으로, 소자간이나 소자와 외부회로 사이를 전기적으로 접속시키기 위한 반도체소자의 배선은, 배선을 위한 소정의 콘택홀 및 비아홀을 배선재료로 매립하여 배선층을 형성하고, 후속 공정을 거쳐 이루어지며 낮은 저항을 필요로 하는 곳에는 금속배선을 사용한다.In general, the wiring of a semiconductor device for electrically connecting between devices or between an element and an external circuit is formed by filling a predetermined contact hole and via hole for wiring with a wiring material, forming a wiring layer, and performing a subsequent process. Metal wiring is used where resistance is required.
상기 금속배선은 알루미늄(Al)에 소량의 실리콘이나 구리(Cu)가 포함되거나 실리콘과 구리가 모두 포함되어 비저항이 낮으면서 가공성이 우수한 알루미늄합금을 배선재료로 하여 물리기상증착(physical vapor deposition, 이하 PVD 라함)방법의 스퍼터링으로 상기의 콘택홀 및 비아홀을 매립하는 방법으로 형성된다.The metal wiring includes a small amount of silicon or copper (Cu) in aluminum (Al), or both silicon and copper, and has a low resistivity and excellent workability. PVD) is formed by the method of filling the contact hole and the via hole by sputtering.
하부전극으로 사용되는 다결정실리콘층은 접합영역이나 비트라인에 연결되어 그라운드 전압(ground voltage) 또는 네가티브 전압(negative voltage)을 바이어스(bias)해주고 상부전극에는 포지티브전압(positive voltage)을 바이어스해주는 것이 일반적이다. 이때, 유전체막의 파괴를 일으켜 두개의 전극 사이에 컨덕팅 채널(conducting channel)을 형성하기 위한 전압은 7V이상이 필요하다.The polysilicon layer used as the lower electrode is connected to the junction region or the bit line to bias the ground voltage or negative voltage, and to bias the positive voltage on the upper electrode. to be. At this time, the voltage for forming a conducting channel between the two electrodes by causing the dielectric film to break is required at least 7V.
상기 상부전극에 포지티브 전압을 바이어스해줄때 금속배선 콘택을 이용하여 패드에 연결된 상태로 포지티브전압을 바이어스한다. 이때, 전자의 이동이 정공보다 빠르므로 상부전극에 양의 전압을 인가해주는 것이다.When biasing the positive voltage to the upper electrode, the positive voltage is biased while being connected to the pad using a metal wiring contact. At this time, since the electron movement is faster than the hole, a positive voltage is applied to the upper electrode.
높은 전압이 금속배선 콘택과 상부전극 사이에 걸리게 되면 열손상, 저항증가 등에 의해 상기 상부전극이 녹는 컷-오프(cut-off)현상이 발생하게 된다. 즉, 유전체막이 파괴되어야 하는데 상기 상부전극이 먼저 녹아버려 소자를 사용할 수 없게 된다.When a high voltage is applied between the metallization contact and the upper electrode, a cut-off phenomenon occurs in which the upper electrode is melted due to thermal damage and an increase in resistance. That is, the dielectric film must be destroyed, but the upper electrode is melted first, so that the device cannot be used.
상기와 같이 종래기술에 따른 반도체소자의 금속배선 콘택 형성방법은, 반도체소자가 고집적화되어 감에 따라 금속배선 콘택이 하부 도전배선, 예를들어 다결정실리콘층과의 접촉면적이 작기 때문에 고전압이 인가되는 경우 열손상(thermal damage)으로 인해 하부의 도전배선이 녹는 현상이 발생하여 컷-오프현상을 유발시키기 때문에 이를 방지하기 위하여 콘택의 개수를 증가시키거나, 콘택면적을 증가시킬 수 있지만, 소자의 고집적화에 불리하다.As described above, in the method of forming a metal interconnection contact of a semiconductor device according to the related art, a high voltage is applied because the contact area of a metal interconnect contact with a lower conductive interconnection, for example, a polysilicon layer is small, as the semiconductor device becomes highly integrated. In this case, the lower conductive wiring melts due to thermal damage, which causes a cut-off phenomenon. Therefore, the number of contacts may be increased or the contact area may be increased. Is disadvantageous.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 금속배선 콘택과 하부 도전배선과의 접촉면적을 증가시켜 고전압이 인가되어도 상기 도전배선이 녹지 않게 함으로써 소자의 특성 및 공정 수율을 향상시키는 반도체소자의 금속배선 콘택 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the problems of the prior art, a semiconductor device that improves the characteristics and process yield of the device by increasing the contact area between the metal wiring contact and the lower conductive wiring so that the conductive wiring does not melt even when a high voltage is applied. The purpose of the present invention is to provide a method for forming a metal wiring contact.
도 1a 내지 도 1c 는 본 발명의 제1실시예에 따른 반도체소자의 금속배선 콘택 형성방법을 도시한 단면도.1A to 1C are cross-sectional views illustrating a method for forming a metal wiring contact in a semiconductor device according to a first embodiment of the present invention.
도 2 는 본 발명의 제2실시예에 따른 반도체소자의 금속배선 콘택 형성방법을 도시한 단면도.2 is a cross-sectional view illustrating a method for forming a metallization contact of a semiconductor device according to a second exemplary embodiment of the present invention.
도 3 은 본 발명의 제3실시예에 따른 반도체소자의 금속배선 콘택 형성방법을 도시한 단면도.3 is a cross-sectional view illustrating a metal wiring contact forming method of a semiconductor device according to a third exemplary embodiment of the present invention.
도 4 는 본 발명의 제4실시예에 따른 반도체소자의 금속배선 콘택 형성방법을 도시한 단면도.4 is a cross-sectional view illustrating a method for forming a metallization contact of a semiconductor device according to a fourth embodiment of the present invention.
< 도면의 주요 부분에 대한 간단한 설명 ><Brief description of the main parts of the drawing>
10, 20, 30, 40 : 반도체기판 11, 21, 31, 41 : 제1층간절연막10, 20, 30, 40: semiconductor substrate 11, 21, 31, 41: first interlayer insulating film
12, 23, 34, 44 : 제2층간절연막 패턴 13, 22, 42 : 제1도전층 패턴12, 23, 34, 44: second interlayer insulating film pattern 13, 22, 42: first conductive layer pattern
14 : 희생절연막 패턴 15 : 제2도전층14: sacrificial insulating film pattern 15: the second conductive layer
16 : 제3층간절연막 17, 24, 35, 45 : 금속층16: third interlayer insulating film 17, 24, 35, 45: metal layer
32 : 제1도전층 33, 43 : 제2도전층 패턴32: first conductive layer 33, 43: second conductive layer pattern
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 금속배선 콘택 형성방법은,Metal interconnection contact forming method of a semiconductor device according to the present invention for achieving the above object,
반도체기판 상부에 제1층간절연막을 형성하고, 상기 제1층간절연막 상부에금속배선 콘택보다 넓은 부분을 보호하는 제1도전층 패턴을 형성하는 공정과,Forming a first interlayer insulating film on the semiconductor substrate and forming a first conductive layer pattern on the first interlayer insulating film to protect a portion wider than the metal wiring contact;
전체표면 상부에 제2층간절연막을 형성한 다음, 전면식각하여 상기 제1도전층 패턴을 노출시키는 공정과,Forming a second interlayer insulating film over the entire surface and then etching the entire surface to expose the first conductive layer pattern;
상기 제1도전층 패턴 상부에 금속배선 콘택으로 예정되는 부분을 보호하는 희생절연막 패턴을 형성하는 공정과,Forming a sacrificial insulating film pattern on a portion of the first conductive layer pattern to protect a portion of the first conductive layer pattern, the metal wiring contact;
전체표면 상부에 제2도전층을 형성하고, 제3층간절연막을 형성하여 평탄화시키는 공정과,Forming a second conductive layer over the entire surface, and forming and planarizing a third interlayer insulating film;
금속배선 콘택으로 예정되는 부분을 노출시키는 금속배선 콘택마스크를 식각마스크로 사용하여 상기 제3층간절연막, 제2도전층 및 희생절연막 패턴을 식각하여 금속배선 콘택홀을 형성하는 공정과,Etching the third interlayer insulating film, the second conductive layer, and the sacrificial insulating film pattern using a metal wiring contact mask that exposes a predetermined portion of the metal wiring contact as an etching mask to form a metal wiring contact hole;
전체표면 상부에 상기 금속배선 콘택홀을 통하여 상기 제2도전층과 제1도전층 패턴과 접속되는 금속층을 형성하는 공정을 포함하는 것을 제1특징으로 한다.It is a 1st characteristic that the process includes forming the metal layer connected with the said 2nd conductive layer and a 1st conductive layer pattern through the said metal wiring contact hole on the whole surface.
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 금속배선 콘택 형성방법은,Metal interconnection contact forming method of a semiconductor device according to the present invention for achieving the above object,
반도체기판 상부에 제1층간절연막을 형성하는 공정과,Forming a first interlayer insulating film on the semiconductor substrate;
상기 제1층간절연막 상부에 금속배선 콘택으로 예정되는 부분을 보호하는 희생절연막 패턴을 형성하는 공정과,Forming a sacrificial insulating film pattern on the first interlayer insulating film to protect a portion of the first interlayer insulating film, the metal wiring contact;
전체표면 상부에 도전층을 형성하고, 제2층간절연막을 형성하여 평탄화시키는 공정과,Forming a conductive layer over the entire surface, and forming and planarizing a second interlayer insulating film;
금속배선 콘택으로 예정되는 부분을 노출시키는 금속배선 콘택마스크를 식각마스크로 사용하여 상기 제2층간절연막, 도전층 및 희생절연막 패턴을 식각하여 금속배선 콘택홀을 형성하는 공정과,Etching the second interlayer insulating film, the conductive layer, and the sacrificial insulating film pattern using a metal wiring contact mask that exposes a predetermined portion of the metal wiring contact as an etching mask to form a metal wiring contact hole;
전체표면 상부에 상기 금속배선 콘택홀을 통하여 상기 도전층과 접속되는 금속층을 형성하는 공정을 포함하는 것을 제2특징으로 한다.It is a 2nd characteristic that the process includes forming the metal layer connected with the said conductive layer through the said metal wiring contact hole on the whole surface.
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 금속배선 콘택 형성방법은,Metal interconnection contact forming method of a semiconductor device according to the present invention for achieving the above object,
반도체기판 상부에 제1층간절연막과 제1도전층을 순차적으로 형성하는 공정과,Sequentially forming a first interlayer insulating film and a first conductive layer on the semiconductor substrate;
상기 제1도전층 상부에 금속배선 콘택으로 예정되는 부분을 보호하는 희생절연막 패턴을 형성하는 공정과,Forming a sacrificial insulating film pattern on a portion of the first conductive layer to protect a portion of the first conductive layer, the metal wiring contact;
전체표면 상부에 제2도전층을 형성하고, 제2층간절연막을 형성하여 평탄화시키는 공정과,Forming a second conductive layer over the entire surface, forming a second interlayer insulating film, and planarizing the same;
금속배선 콘택으로 예정되는 부분을 노출시키는 금속배선 콘택마스크를 식각마스크로 사용하여 상기 제2층간절연막, 제2도전층 및 희생절연막 패턴을 식각하여 금속배선 콘택홀을 형성하는 공정과,Etching the second interlayer insulating film, the second conductive layer, and the sacrificial insulating film pattern by using a metal wiring contact mask that exposes a predetermined portion of the metal wiring contact as an etching mask to form a metal wiring contact hole;
전체표면 상부에 상기 금속배선 콘택홀을 통하여 상기 제2도전층과 제1도전층과 접속되는 금속층을 형성하는 공정을 포함하는 것을 제3특징으로 한다.A third feature is a step of forming a metal layer connected to the second conductive layer and the first conductive layer through the metal wiring contact hole on the entire surface.
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 금속배선 콘택 형성방법은,Metal interconnection contact forming method of a semiconductor device according to the present invention for achieving the above object,
반도체기판 상부에 제1층간절연막을 형성하고, 상기 제1층간절연막 상부에금속배선 콘택보다 좁은 부분을 보호하는 제1도전층 패턴을 형성하는 공정과,Forming a first interlayer insulating film on the semiconductor substrate, and forming a first conductive layer pattern on the first interlayer insulating film to protect a narrower portion than the metal wiring contact;
상기 제1도전층 패턴 상부에 금속배선 콘택으로 예정되는 부분을 보호하는 희생절연막 패턴을 형성하는 공정과,Forming a sacrificial insulating film pattern on a portion of the first conductive layer pattern to protect a portion of the first conductive layer pattern, the metal wiring contact;
전체표면 상부에 제2도전층을 형성하고, 제2층간절연막을 형성하여 평탄화시키는 공정과,Forming a second conductive layer over the entire surface, forming a second interlayer insulating film, and planarizing the same;
금속배선 콘택으로 예정되는 부분을 노출시키는 금속배선 콘택마스크를 식각마스크로 사용하여 상기 제2층간절연막, 제2도전층 및 희생절연막 패턴을 식각하여 상기 제1도전층 패턴을 노출시키는 금속배선 콘택홀을 형성하는 공정과,A metal wiring contact hole for exposing the first conductive layer pattern by etching the second interlayer insulating layer, the second conductive layer, and the sacrificial insulating layer pattern by using a metal wiring contact mask that exposes a predetermined portion of the metal wiring contact as an etch mask. Forming a process,
전체표면 상부에 상기 금속배선 콘택홀을 통하여 상기 제2도전층과 제1도전층 패턴과 접속되는 금속층을 형성하는 공정을 포함하는 것을 제4특징으로 한다.It is a 4th characteristic including the process of forming the metal layer connected to the said 2nd conductive layer pattern and the 1st conductive layer pattern through the said metal wiring contact hole on the whole surface.
이하, 첨부된 도면을 참고로 하여 본 발명을 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described the present invention.
도 1a 내지 도 1c 는 본 발명의 제1실시예에 따른 반도체소자의 금속배선 콘택 형성방법을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a method for forming a metal wiring contact in a semiconductor device according to a first embodiment of the present invention.
먼저, 반도체기판(10) 상부에 제1층간절연막(11)을 형성한 다음, 상기 제1층간절연막(11) 상부에 제1도전층(도시안됨)을 형성한다.First, a first interlayer insulating film 11 is formed on the semiconductor substrate 10, and then a first conductive layer (not shown) is formed on the first interlayer insulating film 11.
다음, 상기 제1도전층은 금속배선 콘택보다 넓은 부분을 노출시키는 식각마스크로 상기 제1도전층을 식각하여 제1도전층 패턴(13)을 형성한다. 이때, 상기 제1도전층은 다결정실리콘층으로 형성한다.Next, the first conductive layer is an etch mask that exposes a wider portion than the metal wiring contact to etch the first conductive layer to form a first conductive layer pattern 13. In this case, the first conductive layer is formed of a polycrystalline silicon layer.
그 다음, 전체표면 상부에 제2층간절연막(12)을 형성한 후 전면식각공정으로 상기 제2층간절연막(12)을 제거하여 상기 제1도전층 패턴(13)을 노출시킨다.Next, the second interlayer insulating layer 12 is formed on the entire surface, and the second interlayer insulating layer 12 is removed by an entire surface etching process to expose the first conductive layer pattern 13.
다음, 전체표면 상부에 희생절연막(도시안됨)을 2000 ∼ 3000Å 두께로 형성하고, 금속배선콘택으로 예정되는 부분을 보호하는 금속배선 콘택마스크를 식각마스크로 사용하여 상기 희생절연막을 식각하여 상기 제1도전층 패턴(13) 상부에 희생절연막 패턴(14)을 형성한다. (도 1a참조)Next, a sacrificial insulating film (not shown) is formed on the entire surface to a thickness of 2000 to 3000Å, and the sacrificial insulating film is etched using a metal wiring contact mask as an etching mask to protect a portion intended as a metal wiring contact. A sacrificial insulating film pattern 14 is formed on the conductive layer pattern 13. (See FIG. 1A)
그리고, 전체표면 상부에 제2도전층(15)을 형성하되, 다결정실리콘층을 이용하여 형성한다. (도 1b참조)Then, the second conductive layer 15 is formed on the entire surface, but using a polysilicon layer. (See FIG. 1B)
다음, 상기 제2도전층(15) 상부에 제3층간절연막(16)을 형성하여 평탄화시킨다.Next, a third interlayer insulating layer 16 is formed on the second conductive layer 15 to be planarized.
그 다음, 금속배선 콘택으로 예정되는 부분을 노출시키는 금속배선 콘택마스크를 식각마스크로 사용하여 상기 제3층간절연막(16), 제2도전층(15) 및 희생절연막 패턴(14)을 식각하여 상기 제1도전층 패턴(13)을 노출시키는 금속배선 콘택홀(도시안됨)을 형성한다.Next, the third interlayer insulating layer 16, the second conductive layer 15, and the sacrificial insulating layer pattern 14 are etched using a metal wiring contact mask that exposes a portion intended to be a metal wiring contact as an etching mask. A metal wiring contact hole (not shown) that exposes the first conductive layer pattern 13 is formed.
그 후, 전체표면에 금속층(17)을 형성하되, 상기 금속층(17)이 상기 금속배선 콘택홀을 통하여 상기 제2도전층(15) 및 제1도전층 패턴(13)에 접속되게 형성한다. (도 1c참조)Thereafter, the metal layer 17 is formed on the entire surface, and the metal layer 17 is formed to be connected to the second conductive layer 15 and the first conductive layer pattern 13 through the metal wiring contact hole. (See FIG. 1C)
도 2 는 본 발명의 제2실시예에 따른 반도체소자의 금속배선 콘택 형성방법을 도시한 단면도로서, 반도체기판(20) 상부에 제1층간절연막(21)을 형성하고, 금속배선 콘택으로 예정되는 부분을 보호하는 희생절연막 패턴(도시안됨)을 형성한 다음, 제1도전층을 형성한 후 제1실시예에서와 같은 후속공정을 실시하여 금속배선 콘택을 형성한다. 이때, 상기 제1층간절연막(21)을 형성한 다음, 도전층을 형성하지 않기 때문에 제1실시예보다 금속배선 콘택과 도전층간에 접촉면적이 적다.FIG. 2 is a cross-sectional view illustrating a method for forming a metal interconnection contact of a semiconductor device according to a second embodiment of the present invention, in which a first interlayer insulating film 21 is formed on a semiconductor substrate 20, and the metal interconnection contact is formed. After forming a sacrificial insulating film pattern (not shown) that protects the portion, the first conductive layer is formed and then a subsequent process as in the first embodiment is performed to form a metal wiring contact. At this time, since the conductive layer is not formed after the first interlayer insulating film 21 is formed, the contact area between the metal wiring contact and the conductive layer is smaller than that of the first embodiment.
도 3 은 본 발명의 제3실시예에 따른 반도체소자의 금속배선 콘택 형성방법을 도시한 단면도로서, 반도체기판(30) 상부에 제1층간절연막(31) 상부에 제1도전층(32)을 형성한 다음 패터닝하지 않고, 제1실시예에서와 같은 후속공정을 실시한다.3 is a cross-sectional view illustrating a method for forming a metal interconnection contact of a semiconductor device according to a third exemplary embodiment of the present invention, wherein the first conductive layer 32 is disposed on the first interlayer insulating layer 31 on the semiconductor substrate 30. After the formation, the pattern is subjected to the subsequent steps as in the first embodiment without patterning.
도 4 는 본 발명의 제4실시예에 따른 반도체소자의 금속배선 콘택 형성방법을 도시한 단면도로서, 반도체기판(40) 상부에 제1층간절연막(41)을 형성하고, 상기 제1층간절연막(41) 상부에 금속배선 콘택으로 예정되는 부분보다 좁은 부분을 보호하는 제1도전층 패턴(42)을 형성한다.4 is a cross-sectional view illustrating a method for forming a metal wiring contact of a semiconductor device in accordance with a fourth embodiment of the present invention. The first interlayer insulating film 41 is formed on the semiconductor substrate 40, and the first interlayer insulating film ( 41) A first conductive layer pattern 42 is formed on the upper portion of the first conductive layer pattern 42 to protect a narrower portion than the portion intended to be a metal wiring contact.
다음, 금속배선 콘택으로 예정되는 부분을 보호하는 희생절연막 패턴(도시안됨)을 형성한 후, 전체표면 상부에 제2도전층(도시안됨)을 형성하고, 제1실시예에서와 같은 후속공정을 실시한다.Next, after forming a sacrificial insulating film pattern (not shown) that protects a portion intended as a metal wiring contact, a second conductive layer (not shown) is formed over the entire surface, and a subsequent process as in the first embodiment is performed. Conduct.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 금속배선 콘택 형성방법은, 반도체소자의 고집접화에 의해 접촉면적이 작은 금속배선 콘택과 다결정실리콘층의 접촉면적을 콘택의 개수를 증가시키지 않고 접촉면적을 증가시킬 수 있으르로 높은 전압을 필요로 하는 회로에 높은 전압을 인가하는 경우 발생하는 열손상에 의해 상기 다결정실리콘층이 녹아서 컷-오프현상이 발생하는 것을 방지하고, 소자의 특성 및 수율을 향상시키며 그에 따른 반도체소자의 고집적화를 유리하게 하는 이점이 있다.As described above, in the method for forming a metal wiring contact of a semiconductor device according to the present invention, the contact area between a metal wiring contact having a small contact area and a polysilicon layer due to high integration of the semiconductor device is increased without increasing the number of contacts. Since the polysilicon layer melts due to thermal damage generated when a high voltage is applied to a circuit requiring a high voltage, the cut-off phenomenon can be prevented and the characteristics and yield of the device can be improved. There is an advantage to improve and advantageously high integration of the semiconductor device.
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