KR960004077B1 - Manufacturing process of semiconductor contact device - Google Patents

Manufacturing process of semiconductor contact device Download PDF

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Publication number
KR960004077B1
KR960004077B1 KR92024506A KR920024506A KR960004077B1 KR 960004077 B1 KR960004077 B1 KR 960004077B1 KR 92024506 A KR92024506 A KR 92024506A KR 920024506 A KR920024506 A KR 920024506A KR 960004077 B1 KR960004077 B1 KR 960004077B1
Authority
KR
South Korea
Prior art keywords
forming
manufacturing process
contact device
semiconductor contact
conducting
Prior art date
Application number
KR92024506A
Other languages
Korean (ko)
Other versions
KR940016486A (en
Inventor
Jae-Kap Kim
Original Assignee
Hyundai Electronics Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Priority to KR92024506A priority Critical patent/KR960004077B1/en
Publication of KR940016486A publication Critical patent/KR940016486A/en
Application granted granted Critical
Publication of KR960004077B1 publication Critical patent/KR960004077B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

forming an interlayer insulating film(4) on a first conducting line(30), forming a contact mask(5) after depositing photosensitive film and exposing the first conducting line(30) by forming a contact hole on an interlayer insulation film(4) using a contact mask(5); forming a connection part(45) by etching the exposed first conduction line(30) with constant depth after the first step; a forming a second conducting ling(6) on the connection part(45) and the contact hole of the interlayer insulation film (4) after the second step.
KR92024506A 1992-12-16 1992-12-16 Manufacturing process of semiconductor contact device KR960004077B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92024506A KR960004077B1 (en) 1992-12-16 1992-12-16 Manufacturing process of semiconductor contact device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92024506A KR960004077B1 (en) 1992-12-16 1992-12-16 Manufacturing process of semiconductor contact device

Publications (2)

Publication Number Publication Date
KR940016486A KR940016486A (en) 1994-07-23
KR960004077B1 true KR960004077B1 (en) 1996-03-26

Family

ID=19345792

Family Applications (1)

Application Number Title Priority Date Filing Date
KR92024506A KR960004077B1 (en) 1992-12-16 1992-12-16 Manufacturing process of semiconductor contact device

Country Status (1)

Country Link
KR (1) KR960004077B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100596898B1 (en) * 1999-12-24 2006-07-04 주식회사 하이닉스반도체 Manufacturing method for metal line contact of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100596898B1 (en) * 1999-12-24 2006-07-04 주식회사 하이닉스반도체 Manufacturing method for metal line contact of semiconductor device

Also Published As

Publication number Publication date
KR940016486A (en) 1994-07-23

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