KR20010063833A - A Method of Fabricating a Semiconductor Devices - Google Patents

A Method of Fabricating a Semiconductor Devices Download PDF

Info

Publication number
KR20010063833A
KR20010063833A KR1019990061934A KR19990061934A KR20010063833A KR 20010063833 A KR20010063833 A KR 20010063833A KR 1019990061934 A KR1019990061934 A KR 1019990061934A KR 19990061934 A KR19990061934 A KR 19990061934A KR 20010063833 A KR20010063833 A KR 20010063833A
Authority
KR
South Korea
Prior art keywords
contact
contact hole
spacer
gate electrode
forming
Prior art date
Application number
KR1019990061934A
Other languages
Korean (ko)
Inventor
남동균
이승구
Original Assignee
윤종용
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 윤종용, 삼성전자 주식회사 filed Critical 윤종용
Priority to KR1019990061934A priority Critical patent/KR20010063833A/en
Publication of KR20010063833A publication Critical patent/KR20010063833A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to increase the area of a contact by removing a gate side wall spacer in active region and at the same time to reduce a contact resistance through an additional ion implantation. CONSTITUTION: The method is for forming a common contact over a gate electrode(15) and an active region in a semiconductor device. According to the method, a contact hole(33) is formed on an inter layer insulation film(13). Then, a side wall spacer(17) of the gate electrode revealed by the formation of the contact hole is removed, and the contact hole is buried by a conductive layer. After removing the spacer, an impurity ion is implanted into the contact hole. The spacer is formed with an Al2O3. The common contact is formed by stacking a barrier metal(51) and a contact metal(53) on the common contact hole.

Description

반도체 장치 제조 방법 {A Method of Fabricating a Semiconductor Devices}A method of fabricating a semiconductor devices

본 발명은 반도체 장치 제조 방법에 관한 것으로, 보다 상세하게는 공통 콘택을 가지는 반도체 장치에서 공통 콘택을 형성하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a common contact in a semiconductor device having a common contact.

반도체 장치를 형성함에 있어서 기판에 형성된 트랜지스터의 게이트 전극과 소오스/드레인 영역의 한 쪽에 공통의 전압을 인가하도록 형성하는 경우가 있다.이 경우에 게이트 전극과 소오스/드레인 영역을 하나의 도전 패턴으로 연결하되, 게이트 전극 아래에는 게이트 절연막이 놓이도록 형성할 수 있으나, 일단 MOS 트랜지스터 구조를 형성한 다음에 게이트 전극과 소오스/드레인 영역에 걸쳐서 콘택을 형성함으로써 공통의 전압을 인가할 수 있다.In forming a semiconductor device, a common voltage may be applied to one of a gate electrode and a source / drain region of a transistor formed on a substrate. In this case, the gate electrode and the source / drain region are connected in one conductive pattern. However, the gate insulating layer may be formed under the gate electrode. However, once the MOS transistor structure is formed, a common voltage may be applied by forming a contact over the gate electrode and the source / drain regions.

도1은 종래의 경우에서 상술한 공통 콘택을 형성한 상태를 나타내는 단면도이다. 여기서 게이트 전극(15)의 측벽에는 기판에 LDD 구조를 형성하기 위한 실리콘 질화막 스페이서(17)가 형성되어 있고, 게이트 전극 위쪽에는 절연성 캡핑막이 없으며, 폴리실리콘층 위로 금속 실리사이드층 등의 도전층이 겹쳐져서 게이트 전극(15)이 형성된다. 그리고, 활성 영역에서도 표면에 금속 실리사이드층이 형성되는 경우가 많다.1 is a cross-sectional view showing a state in which the common contact described above is formed in the conventional case. Here, the silicon nitride film spacer 17 is formed on the sidewall of the gate electrode 15 to form the LDD structure on the substrate, and there is no insulating capping film on the gate electrode, and a conductive layer such as a metal silicide layer is superimposed on the polysilicon layer. The gate electrode 15 is formed. In addition, the metal silicide layer is often formed on the surface of the active region.

게이트 전극(15)과 게이트 전극 측면의 한 활성 영역 부분 위쪽으로는 비트 라인과의 연결을 위한 하나의 메탈 콘택이 형성되어 외부에서 인가되는 신호 전압을 동시에 게이트 전극(15)과 활성 영역 부분에 전달하게 된다. 이런 형태의 공통 콘택(19)은 흔히 NC(Null Contact)라고도 약칭되는데, 현재 SRAM 공정 등에서 일반적으로 사용되며, 레이 아웃(Lay Out) 상의 셀의 단면적을 줄여서 캐시(cache)의 메모리 용량을 높이기 위한 고집적화에 많이 이용된다.A metal contact for connecting the bit line is formed above the gate electrode 15 and a portion of the active region on the side of the gate electrode to simultaneously transmit an externally applied signal voltage to the gate electrode 15 and the active region. Done. This type of common contact 19 is often abbreviated as NC (Null Contact), which is generally used in SRAM process, etc. and is used to increase the memory capacity of the cache by reducing the cross-sectional area of the cell on the layout. It is often used for high integration.

그런데, 이런 공통 콘택을 형성함에 있어서, 소자의 집접도를 높이기 위해 소자를 형성하기 위한 패턴이나 콘택의 선폭이 줄어들면서 공통 콘택의 형성 가능 면적도 줄어들게 된다. 특히, 두개의 전극과 콘택 면적을 나누어야 하는 공통 콘택의 특성상 개개 전극과 접촉하는 콘택의 면적은 더욱 작아지므로 콘택을 통한 도전성을 확보하는 것이 큰 과제가 되고 있다. 또한, 도1에서도 볼 수 있듯이 게이트 전극(15) 측부의 활성 영역과의 콘택에서 접촉 면적은 게이트 전극(15) 측벽에 형성된 스페이서(17)로 인하여 많이 줄어드는 것을 알 수 있다.However, in forming such a common contact, the line width of the pattern or contact for forming the element is reduced in order to increase the degree of contact of the element, and thus the formable area of the common contact is reduced. In particular, due to the characteristics of the common contact that needs to be divided between the two electrodes, the area of the contact making contact with the respective electrodes becomes smaller. Therefore, it is a big problem to secure the conductivity through the contact. In addition, as shown in FIG. 1, it can be seen that the contact area in contact with the active region of the side of the gate electrode 15 is greatly reduced due to the spacer 17 formed on the sidewall of the gate electrode 15.

본 발명은 상술한 문제점을 해결하기 위한 것으로, 측벽 스페이서가 형성된 게이트 전극과 그 측부 활성영역이 하나의 콘택에 접속될 때, 접촉 면적의 제약으로 인하여 콘택의 역할을 제대로 할 수 없는 문제점을 해결하기 위해 새로운 공통 콘택의 형성 방법을 제공하는 것을 목적으로 한다.The present invention is to solve the above-mentioned problems, when the gate electrode and the side active region formed sidewall spacer is connected to one contact, to solve the problem that can not play the role of the contact properly due to the constraint of the contact area The object of the present invention is to provide a method of forming a new common contact.

도1은 종래 기술에 따라 공통 콘택을 형성한 상태를 나타내는 단면도;1 is a cross-sectional view showing a state in which a common contact is formed according to the prior art;

도2 내지 도5는 본 발명에 따라 반도체 장치에서 공통 콘택을 형성하는 방법을 순차적으로 나타내는 공정 단면도이다.2 to 5 are cross-sectional views sequentially illustrating a method of forming a common contact in a semiconductor device according to the present invention.

※도면의 주요 부분에 대한 부호의 설명※ Explanation of code for main part of drawing

10: 기판 11: 필드 절연막10: substrate 11: field insulating film

13: 층간 절연막 15: 게이트 전극13: interlayer insulating film 15: gate electrode

17: 스페이서 19: 공통 콘택17: spacer 19: common contact

31: 금속 실리사이드 33: 공통 콘택 홀31: metal silicide 33: common contact hole

51: 베리어 메탈 53: 콘택 메탈51: barrier metal 53: contact metal

상기 목적을 달성하기 위한 본 발명은, 반도체 장치에서 게이트 전극과 인근 활성 영역에 걸쳐 공통 콘택을 형성함에 있어서, 층간 절연막층에 콘택 홀을 형성하는 단계, 상기 콘택 홀 형성에 의해 드러난 상기 게이트 전극의 측벽 스페이서 부분을 제거하는 단계, 상기 콘택 홀을 도전층으로 매립하는 단계를 구비하여 이루어진다.According to an aspect of the present invention, there is provided a method of forming a common contact between a gate electrode and an adjacent active region in a semiconductor device, the method comprising: forming a contact hole in an interlayer insulating layer; Removing the sidewall spacer portion, and filling the contact hole with a conductive layer.

스페이서는 기판에 LDD 구조를 형성하기 위해 사용되는 것이 대부분이므로 불순물 주입 농도가 낮고 도전성이 떨어진다. 따라서, 본 발명에서 스페이서 부분을 제거하는 단계에 이어서 상기 콘택 홀을 통해 불순물 이온주입을 실시하는 단계가 더 구비되는 것이 콘택 저항을 줄이기 위해 바람직하다. 콘택을 위해 콘택 홀을 매립하는 재질로는 비트 라인 콘택을 형성하기 위한 텅스텐 금속이나 기타 금속층, 금속 실리사이드층을 사용할 수 있고, 사전에 확산 방지용 베리어 메탈을 적층하는 것이 일반적이다.Since the spacer is mostly used to form the LDD structure on the substrate, the impurity implantation concentration is low and the conductivity is poor. Therefore, in the present invention, it is preferable to further reduce the contact resistance by performing impurity ion implantation through the contact hole subsequent to removing the spacer portion. As a material for filling the contact hole for contact, a tungsten metal or other metal layer or metal silicide layer for forming a bit line contact may be used, and a barrier metal for diffusion prevention is generally laminated in advance.

스페이서는 일반적으로 콘택 홀이 형성되는 층간 절연막과 차별화된 실리콘 질화막 재질로 형성하게 되는데, 콘택 홀을 식각 형성하는 과정에서 남게 되므로 별도의 식각 과정에서 다른 식각 물질을 이용하여 제거하게 된다. 이때 층간 절연막과의 차별화 및 식각시의 편의를 위해서는 실리콘 질화막보다 건식 이방성 식각에서 실리콘 산화막에 비해 식각율이 매우 작고, 습식 식각으로는 더 쉽게 제거되는 산화 알루미늄(Al2O3)을 사용하는 것이 바람직하다.The spacer is generally formed of a silicon nitride film material which is different from the interlayer insulating film on which the contact hole is formed. Since the spacer remains during the etching process, the spacer is removed using another etching material in a separate etching process. In this case, for the purpose of differentiation from the interlayer insulating film and for the convenience of etching, it is preferable to use aluminum oxide (Al 2 O 3 ), which has a very small etching rate compared to the silicon oxide film in dry anisotropic etching, and is more easily removed by wet etching. desirable.

이하 도면을 참조하면서 본 발명의 실시예를 통해 본 발명을 좀 더 살펴보기로 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

도2 내지 도5는 본 발명에 따라 반도체 장치에서 공통 콘택을 형성하는 방법을 순차적으로 나타내는 공정 단면도이다.2 to 5 are cross-sectional views sequentially illustrating a method of forming a common contact in a semiconductor device according to the present invention.

도2는 반도체 기판에 소자 분리를 실시하고 MOS 트랜지스터 구조를 형성한 상태를 나타낸다. 소자 분리는 STI 방법에 의해 이루어졌으며, 필드 절연막(11) 사이의 기판(10)의 P-WELL 부분에 MOS 트랜지스터가 구성되어 있다. 트랜지스터 구성은 기판(10)에 게이트 전극(15)을 형성한 다음에 N- 이온주입을 실시하고, 게이트 전극(15) 측벽에 산화 알루미늄(Al2O3)을 적층하고 에치 백하여 스페이서(17)를 형성한 상태에서, N+로 고농도 불순물 이온주입을 실시하여 소오스/드레인 영역과 채널 및 LDD의 구조를 이룬 것이다.Fig. 2 shows a state in which device isolation is performed on a semiconductor substrate and a MOS transistor structure is formed. Device isolation was performed by the STI method, and a MOS transistor is formed in the P-WELL portion of the substrate 10 between the field insulating films 11. In the transistor configuration, the gate electrode 15 is formed on the substrate 10, followed by N-ion implantation, and aluminum oxide (Al 2 O 3 ) is laminated and etched back on the sidewall of the gate electrode 15 to form a spacer 17. ), A high concentration of impurity ions are implanted with N + to form a source / drain region, a channel, and an LDD.

도3은 도2의 상태에서 활성 영역에 코발트나 텅스텐 금속을 적층하고 분위기를 조성하여 금속 실리사이드(31)를 형성한 다음, 층간 절연막(13)을 적층하고 패턴닝하여 일부 영역에 공통 콘택 홀(33)을 형성한 상태를 나타낸다. 층간 절연막(13)을 적층하기 전에 별도의 식각 저지층을 형성하여 공통 콘택 형성시에 편의를 도모할 수도 있다. 게이트 전극(15) 측벽의 스페이서(17)는 잔류하고 있으며, 공통 콘택 홀(33) 저부에는 게이트 전극(15) 및 액티브 영역 상면의 금속 실리사이드(31)가 노출되어 있다.3 illustrates the formation of a metal silicide 31 by stacking cobalt or tungsten metal in an active region and forming an atmosphere in the state of FIG. 2, and then stacking and patterning an interlayer insulating layer 13 to form a common contact hole ( 33) is shown. Prior to stacking the interlayer insulating film 13, a separate etch stop layer may be formed for convenience in forming a common contact. The spacer 17 on the sidewall of the gate electrode 15 remains, and the gate electrode 15 and the metal silicide 31 on the upper surface of the active region are exposed at the bottom of the common contact hole 33.

도4는 도3의 상태에서 습식 식각을 통해 스페이서(17)를 제거하고 노출된 LDD 영역에 불순물 농도를 높여 도전성을 강화하기 위해 비소나 인 등의 N형 불순물 이온주입을 실시하는 상태를 나타낸다. 산화 알루미늄 스페이서(17) 가운데 노출된 부분은 습식 식각을 통해 쉽게 제거된다. 스페이서(17)가 제거된 부분에는 금속 실리사이드(31)가 형성되어 있지 않으며, 보다 나은 오믹 콘택을 형성하기 위해 높은 농도로 불순물 이온주입이 이루어지는 것이다.FIG. 4 illustrates a state in which N-type impurity ions such as arsenic or phosphorus are implanted to remove the spacers 17 through wet etching and to enhance conductivity by increasing an impurity concentration in the exposed LDD region. The exposed portion of the aluminum oxide spacer 17 is easily removed by wet etching. The metal silicide 31 is not formed at the portion where the spacer 17 is removed, and impurity ion implantation is performed at a high concentration to form a better ohmic contact.

도5는 도4의 상태에서 공통 콘택 홀(33)에 배리어 메탈(51)과 콘택 메탈(53)을 적층하여 공통 콘택을 형성한 상태를 나타낸다. 베리어 메탈(51)로는 티타늄막과 티타늄 질화막을 겹쳐서 사용하며, 콘택 메탈(53)로는 텅스텐 막을 많이 사용한다.FIG. 5 illustrates a state in which the common contact is formed by stacking the barrier metal 51 and the contact metal 53 in the common contact hole 33 in the state of FIG. 4. As the barrier metal 51, a titanium film and a titanium nitride film are overlapped, and as the contact metal 53, a tungsten film is used a lot.

본 발명에 따르면, 게이트 전극과 인근 활성 영역에 걸쳐 형성되는 공통 콘택을 형성함에 있어서, 활성 영역에서 콘택의 면적을 좁히고 있는 게이트 측벽 스페이서를 제거하여 콘택의 면적을 넓히는 동시에 이온주입의 추가 실시를 통해 콘택 저항을 줄일 수 있다. 또한, 산화 알루미늄 스페이서를 사용하여 공정을 정확하고 간편하게 진행할 수 있다.According to the present invention, in forming a common contact formed over a gate electrode and an adjacent active region, by removing the gate sidewall spacer that narrows the contact area in the active region, the contact area is increased, and ion implantation is further performed. Contact resistance can be reduced. In addition, the aluminum oxide spacer can be used to make the process accurate and simple.

Claims (3)

반도체 장치에서 게이트 전극과 인근 활성 영역에 걸쳐 공통 콘택을 형성함에 있어서,In forming a common contact across a gate electrode and an adjacent active region in a semiconductor device, 층간 절연막층에 콘택 홀을 형성하는 단계,Forming a contact hole in the interlayer insulating film layer, 상기 콘택 홀 형성에 의해 드러난 상기 게이트 전극의 측벽 스페이서 부분을 제거하는 단계 및Removing sidewall spacer portions of the gate electrode exposed by the contact hole formation; and 상기 콘택 홀을 도전층으로 매립하는 단계를 구비하여 이루어지는 반도체 장치 제조 방법.And filling the contact hole with a conductive layer. 제 1 항에 있어서,The method of claim 1, 상기 스페이서 부분을 제거하는 단계에 이어서 상기 콘택 홀에 불순물 이온주입을 실시하는 단계가 더 구비되는 것을 특징으로 하는 반도체 장치 제조 방법.And performing impurity ion implantation into the contact hole subsequent to removing the spacer portion. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 스페이서는 산화 알루미늄(Al2O3)으로 형성하는 것임을 특징으로 하는 반도체 장치 제조 방법.And the spacer is formed of aluminum oxide (Al 2 O 3 ).
KR1019990061934A 1999-12-24 1999-12-24 A Method of Fabricating a Semiconductor Devices KR20010063833A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019990061934A KR20010063833A (en) 1999-12-24 1999-12-24 A Method of Fabricating a Semiconductor Devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019990061934A KR20010063833A (en) 1999-12-24 1999-12-24 A Method of Fabricating a Semiconductor Devices

Publications (1)

Publication Number Publication Date
KR20010063833A true KR20010063833A (en) 2001-07-09

Family

ID=19629494

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019990061934A KR20010063833A (en) 1999-12-24 1999-12-24 A Method of Fabricating a Semiconductor Devices

Country Status (1)

Country Link
KR (1) KR20010063833A (en)

Similar Documents

Publication Publication Date Title
KR100414220B1 (en) Semiconductor device having shared contact and fabrication method thereof
US8053307B2 (en) Method of fabricating semiconductor device with cell epitaxial layers partially overlap buried cell gate electrode
KR100385408B1 (en) Semiconductor device and manufacturing method thereof
US7675110B2 (en) Semiconductor device and method of manufacturing the same
JP2633650B2 (en) Semiconductor memory device and method of manufacturing the same
US7307324B2 (en) MOS transistor in an active region
KR970003953A (en) Highly Integrated DRAM Cells and Manufacturing Method Thereof
US20010012673A1 (en) Mos transistor having self-aligned well bias area and method of fabricating the same
US20010009805A1 (en) Borderless contact structure and method of forming the same
JP3857622B2 (en) Semiconductor device and manufacturing method thereof
KR0139188B1 (en) Method of fabrication non-volatile semiconductor memory device
JP3195785B2 (en) Semiconductor storage device and method of manufacturing the same
US6635538B2 (en) Method of manufacturing a semiconductor device
KR100318320B1 (en) Method for fabricating semiconductor device
US6486516B1 (en) Semiconductor device and a method of producing the same
US7119435B2 (en) Semiconductor device with source/drain extension layer
KR100642649B1 (en) Semiconductor device applying well bias and method offabricating the same
JPH05291518A (en) Semiconductor device and its manufacture
KR20010063833A (en) A Method of Fabricating a Semiconductor Devices
KR100707538B1 (en) method for manufacturing of semiconductor device
KR20050052027A (en) Semiconductor device having a recessed gate electrode and fabrication method thereof
KR20020015818A (en) semiconductor device and method for manufacturing the same
KR100209707B1 (en) Method for forming wiring of semiconductor device
KR100333360B1 (en) A method of fabricating a semiconductor device
US20050151191A1 (en) Semiconductor device and method of manufacturing the same

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination