KR20010063682A - Method for attaching semiconductor chip using flip chip bonding technic - Google Patents
Method for attaching semiconductor chip using flip chip bonding technic Download PDFInfo
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- KR20010063682A KR20010063682A KR1019990061749A KR19990061749A KR20010063682A KR 20010063682 A KR20010063682 A KR 20010063682A KR 1019990061749 A KR1019990061749 A KR 1019990061749A KR 19990061749 A KR19990061749 A KR 19990061749A KR 20010063682 A KR20010063682 A KR 20010063682A
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- semiconductor chip
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- thermoplastic resin
- printed circuit
- bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81909—Post-treatment of the bump connector or bonding area
- H01L2224/8191—Cleaning, e.g. oxide removal step, desmearing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
본 발명은 반도체 장치의 제조 방법에 관한 것으로서, 더욱 상세하게는 범프가 형성된 반도체 칩을 기판에 실장하는 플립 칩 본딩(flip chip bonding) 기술을 이용하는 반도체 칩 패키지 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor chip package using flip chip bonding technology in which a bumped semiconductor chip is mounted on a substrate.
플립 칩 본딩 기술은 집적회로가 형성된 반도체 칩에 그 집적회로와 전기적으로 연결되는 범프를 형성하고, 이를 이용하여 반도체 칩을 기판에 직접 실장하는 기술이다. 플립 칩 본딩 기술은 범프를 반도체 칩의 실장과 전기적인 연결이 동시에 이루어질 수 있고 전기적인 경로가 짧기 때문에 소형화와 경량화 및 고밀도 실장이 필요한 전자제품의 제조에 많이 이용된다. 그러나, 플립 칩 본딩 기술을 이용하여 기판에 직접 반도체 칩을 실장하기 위해서는 반도체 칩에 대한 신뢰성 검증에 어려움이 있기 때문에, 현재 플립 칩 본딩 기술은 볼 그리드 어레이 패키지(BGA; Ball Grid Array Package)와 소위 칩 스케일 패키지(Chip Scale Package) 또는 칩 사이즈 패키지(Chip Size Package)라 불리는 칩 크기 수준의 반도체 칩 패키지의 제조에 많이 적용된다. 플립 칩 본딩 기술을 이용하는 볼 그리드 어레이 패키지의 제조 공정을 간략하게 소개하기로 한다.Flip chip bonding technology is a technique for forming a bump electrically connected to the integrated circuit in the semiconductor chip formed with an integrated circuit, and using this to directly mount the semiconductor chip on the substrate. Flip chip bonding technology is widely used in the manufacture of electronic products that require miniaturization, light weight, and high density mounting because bumps can be electrically connected to a semiconductor chip and are electrically connected at the same time. However, since it is difficult to verify the reliability of the semiconductor chip in order to mount the semiconductor chip directly on the substrate using the flip chip bonding technology, the flip chip bonding technology is a ball grid array package (BGA) and a so-called ball grid array package (BGA). It is widely applied to the manufacture of semiconductor chip packages of chip size level, called chip scale package or chip size package. The manufacturing process of a ball grid array package using flip chip bonding technology will be briefly introduced.
도 1내지 도 4는 일반적인 볼 그리드 어레이 패키지 제조 공정을 나타낸 개략 단면도이다.1 to 4 are schematic cross-sectional views showing a general ball grid array package manufacturing process.
도 1내지 도 4를 참조하면, 볼 그리드 어레이 패키지 제조를 위해서는 먼저 도 1과 같이 접합패드가 형성된 인쇄회로기판(21)에 플럭스(27)를 도포시키고, 도 2와 같이 솔더 범프(solder bump; 13)가 접합패드(23)에 접촉되도록 반도체 칩(11)을 인쇄회로기판(21)에 정렬하여 예비 접합시키며, 도 3과 같이 리플로우(reflow) 공정을 진행하여 솔더 범프(13)와 접합패드(23)를 접합시키고, 도 4와 같이 솔더범프(13)와 접합패드(23)의 접합이 완료된 상태에서 외부환경으로부터의 보호를 위하여 반도체 칩(11)과 인쇄회로기판(21) 사이의 공간을 필러(filler)를 포함하는 충전재(35)로 언더-필(under-fill)하며, 반도체 칩(11)이 실장된 인쇄회로기판(21)에 솔더 볼(25)을 부착시켜 볼 그리드 어레이 패키지(100)를 완성한다.1 to 4, in order to manufacture a ball grid array package, a flux 27 is first applied to a printed circuit board 21 on which a bonding pad is formed, as shown in FIG. 1, and solder bumps are formed as shown in FIG. 2. The semiconductor chip 11 is preliminarily bonded to the printed circuit board 21 so that the 13 is in contact with the bonding pad 23, and the solder chip 13 is bonded to the solder bump 13 by performing a reflow process as shown in FIG. 3. The pads 23 are bonded to each other, and as shown in FIG. 4, between the semiconductor chip 11 and the printed circuit board 21 for protection from the external environment in the state where the solder bumps 13 and the bonding pads 23 are completed. Ball grid array by under-filling the space with a filler 35 including a filler and attaching solder balls 25 to the printed circuit board 21 on which the semiconductor chip 11 is mounted. Complete the package 100.
이와 같은 볼 그리드 어레이 패키지 제조에 있어서 알 수 있듯이, 플립 칩 본딩 기술을 이용한 반도체 칩 실장 방법은 소자의 동작에 대한 신뢰성을 확보하기 위하여 반도체 칩과 인쇄회로기판 사이의 공간에 충전재를 주입하여 봉지하는 언더-필 공정이 필요하다. 충전재는 물리적 또는 화학적인 외부환경으로부터 보호를 할뿐만 아니라 온도변화에 따른 반도체 칩과 인쇄회로기판의 열팽창 계수의 차에 의해 발생하는 열응력에 대한 보강재로서의 역할도 하기 때문에, 플립 칩 본딩 기술을 이용한 반도체 칩 실장에 있어서 매우 중요하다.As can be seen in the manufacture of such a ball grid array package, a semiconductor chip mounting method using flip chip bonding technology is to inject and seal a filler in the space between the semiconductor chip and the printed circuit board in order to ensure the reliability of the operation of the device. Under-fill process is required. The fillers not only protect from physical or chemical external environments but also serve as reinforcements for thermal stress caused by the difference in thermal expansion coefficient of semiconductor chips and printed circuit boards due to temperature changes. It is very important for semiconductor chip mounting.
그러나, 반도체 칩과 인쇄회로기판 사이의 공간이 매우 작고 반도체 칩의 크기가 커짐에 따라 충전에 소요되는 시간이 길어지고 내부에 위치하는 범프에 의해 충전재의 흐름에 있어서의 불균형이 발생된다. 이는 보이드(void) 발생의 원인으로서 작용한다. 그리고, 언더-필 공정은 경화 과정이 필요하므로 생산성 저하의 원인으로도 작용한다.However, as the space between the semiconductor chip and the printed circuit board is very small and the size of the semiconductor chip increases, the time required for charging becomes longer and an imbalance in the flow of the filler occurs due to the bumps located therein. This acts as a cause of void generation. In addition, since the under-fill process requires a curing process, it also acts as a cause of the decrease in productivity.
또한, 소재 측면에서 볼 때 반도체 칩과 인쇄회로기판 사이의 공간에서 충전재의 주입에 필요한 흐름성을 얻기 위해 점도 및 필러의 양과 크기의 제약이 존재하며, 이로 인한 수지 및 필러 선택의 폭이 제한된다. 이는 신뢰성 측면의 취약성을 초래한다.In addition, in terms of the material, there are restrictions on the viscosity and the amount and size of the filler to obtain the flowability required for the filling of the filler in the space between the semiconductor chip and the printed circuit board, thereby limiting the range of resin and filler selection. . This results in a vulnerability in terms of reliability.
본 발명의 목적은 언더-필 공정을 생략함으로써 이에 다란 제반 관련 공정을 생략할 수 있고, 충전재의 선택 폭을 넓힐 수 있는 플립 칩 본딩 기술을 이용한 반도체 칩 실장 방법을 제공하는 데에 있다.An object of the present invention is to provide a semiconductor chip mounting method using a flip chip bonding technology that can omit all the related processes by omitting the under-fill process, and can widen the selection of the filler.
도 1내지 도 4는 일반적인 볼 그리드 어레이 패키지 제조 공정을 나타낸 개략 단면도,1 to 4 is a schematic cross-sectional view showing a general ball grid array package manufacturing process,
도 5내지 도 9는 본 발명에 따른 반도체 칩 실장 방법에 따른 제조 공정을 나타낸 개략 단면도이다.5 to 9 are schematic cross-sectional views showing a manufacturing process according to the semiconductor chip mounting method according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10; 웨이퍼 11; 반도체 칩10; Wafer 11; Semiconductor chip
12; 스크라이브 라인 13; 범프12; Scribe line 13; Bump
15; 열가소성 수지층 21; 인쇄회로기판15; Thermoplastic resin layer 21; Printed circuit board
23; 접합패드 25; 솔더 볼23; Bonding pads 25; Solder ball
35; 충전재35; filling
100; 볼 그리드 어레이 패키지(BGA; Ball Grid Array Package)100; Ball Grid Array Package (BGA)
이와 같은 목적을 달성하기 위한 본 발명에 따른 플립 칩 본딩 기술을 이용한 반도체 칩 실장 방법은,A semiconductor chip mounting method using a flip chip bonding technology according to the present invention for achieving the above object,
⒜ 내부의 집적회로와 전기적으로 연결되는 복수의 범프와 그 범프를 덮도록 열가소성 수지층이 형성된 반도체 칩을 준비하는 단계, ⒝ 인쇄회로기판의 접합패드와 상기 범프가 접촉되도록 상기 반도체 칩을 상기 인쇄회로기판에 정렬하는 단계, 및 ⒞ 상기 범프와 상기 접합패드를 열압착시켜 접합시킴과 동시에 열가소성 수지로 인쇄회로기판과 반도체 칩 사이의 공간을 충전시키는 단계를 포함하는 것을 특징으로 한다.하는 preparing a semiconductor chip having a plurality of bumps electrically connected to an integrated circuit therein and a thermoplastic resin layer covering the bumps; 인쇄 printing the semiconductor chip such that the bonding pads of the printed circuit board are in contact with the bumps; And aligning the bump and the bonding pad by thermocompression bonding and filling the space between the printed circuit board and the semiconductor chip with a thermoplastic resin.
이하 첨부 도면을 참조하여 본 발명에 따른 플립 칩 본딩 기술을 이용한 반도체 칩 실장 방법을 보다 상세하게 설명하고자 한다.Hereinafter, a semiconductor chip mounting method using flip chip bonding technology according to the present invention will be described in detail with reference to the accompanying drawings.
도 5내지 도 9는 본 발명에 따른 반도체 칩 실장 방법에 따른 제조 공정을 나타낸 개략 단면도이다.5 to 9 are schematic cross-sectional views showing a manufacturing process according to the semiconductor chip mounting method according to the present invention.
도 5에 도시된 것과 같이 먼저 일반적인 범프 형성 기술을 이용하여 웨이퍼(10)의 각 단위 반도체 칩(11)에 범프(13)를 형성한다. 범프(13)는 반도체 칩(11)의 접속 단자로서의 기능을 수행하게 되는 것으로 웨이퍼 상태에서 일괄적으로 형성될 수 있다. 여기서, 범프(13)는 솔더 범프로서 볼 형태를 가지고 있으나 다른 형태를 가질 수도 있다. 이와 같은 범프 형성 기술은 공지의 기술로서 그에 대한 상세한 설명을 생략하기로 한다.As shown in FIG. 5, a bump 13 is first formed on each unit semiconductor chip 11 of the wafer 10 using a general bump forming technique. The bumps 13 perform functions as connection terminals of the semiconductor chip 11 and may be formed collectively in a wafer state. Here, the bump 13 may have a ball shape as the solder bump but may have another shape. Such bump formation techniques are well known techniques, and detailed description thereof will be omitted.
다음에, 도 6에 도시된 것과 같이 범프(13)가 형성된 웨이퍼(10)에 열가소성 수지를 도포하여 열가소성 수지층(15)을 형성한다. 이때, 열가소성 수지층(15)의 높이는 범프(13)의 높이보다 약간 높도록 형성하는 것이 바람직하며, 그 이유는 후속으로 이어지는 공정 설명에 기술된다. 열가소성 수지층(15)의 형성은 스핀 코팅(spin coating)법이나 프린팅(printing)법, 및 스프레이(spray)법 등을 사용하여 이루어질 수 있다.Next, as shown in FIG. 6, a thermoplastic resin is applied to the wafer 10 on which the bumps 13 are formed to form the thermoplastic resin layer 15. At this time, the height of the thermoplastic resin layer 15 is preferably formed to be slightly higher than the height of the bump 13, and the reason is described in the subsequent process description. The thermoplastic resin layer 15 may be formed using a spin coating method, a printing method, a spray method, or the like.
여기서, 열가소성 수지의 도포 전에 먼저 범프(13)에 대한 세정 작업을 진행하여 열가소성 수지가 반도체 칩(11)의 표면과 범프(15)의 사이에 불순물이 존재하지 않도록 하며, 열가소성 수지의 도포는 범프(15)의 산화를 최소화할 수 있도록 세정 후 조속한 시간 내에 이루어지도록 하는 것이 바람직하다.Here, before the thermoplastic resin is applied, the bump 13 is first cleaned, so that the thermoplastic resin is free of impurities between the surface of the semiconductor chip 11 and the bumps 15, and the thermoplastic resin is bumped. In order to minimize the oxidation of (15), it is preferable to make it within a prompt time after cleaning.
여기서, 열가소성 수지는 구성 성분 내에 필러를 포함하도록 하여 기계적 특성이 향상되도록 하고, 필러의 크기는 필요에 따라 조절해 준다. 그리고, 열가소성 수지는 반도체 칩의 표면에 형성된 박막 소재 및 인쇄회로기판의 포토레지스트와 비티 레진 등과의 접착력을 고려하여 결정될 수 있다. 또한, 열가소성 수지의 융점은 약 200~220℃ 사이가 적합한 데, 그 이유는 열 특성에 문제가 없어야 하며, 리플로우 전에 소정 점도의 겔 상태로 변해서 범프(13)의 부착이 가능하도록 해야 하기 때문이다.Here, the thermoplastic resin is to include the filler in the component to improve the mechanical properties, the size of the filler is adjusted as necessary. The thermoplastic resin may be determined in consideration of the adhesive force between the thin film material formed on the surface of the semiconductor chip and the photoresist and bitty resin of the printed circuit board. In addition, the melting point of the thermoplastic resin is suitable between about 200 ~ 220 ℃, because there should be no problem in the thermal properties, because it must be changed to a gel state of a predetermined viscosity before reflow to allow the bump 13 to be attached. to be.
열가소성 수지의 도포 후에 경화 과정을 거쳐 열가소성 수지층(15)의 형성이 완료되면 도 7에 도시된 것과 같이 웨이퍼(10)를 스크라이브 라인(12)을 따라 절단하여 범프(13)가 형성된 단위 반도체 칩(11)으로 분리시킨다.When the formation of the thermoplastic resin layer 15 is completed after the application of the thermoplastic resin and the formation of the thermoplastic resin layer 15 is completed, the unit semiconductor chip having the bumps 13 formed by cutting the wafer 10 along the scribe line 12 as shown in FIG. 7. Separate with (11).
이렇게 분리된 반도체 칩(11)을 도 8에 도시된 것과 같이 범프(13)와 접합패드(23)가 접촉되도록 인쇄회로기판(21)의 정해진 위치에 반도체 칩(11)을 정렬하고 일정한 압력으로 누른 상태에서 리플로우 공정을 진행한다. 리플로우 공정은 수지가 소정 점도의 겔 상태로 될 수 있도록 200~220℃ 온도 조건 상태를 길게 유지하고, 그 후에 범프(13)가 접합패드(23)에 충분히 접합될 수 있도록 최고 온도조건을 조성한다. 이렇게 함으로써 열가소성 수지는 반도체 칩(11)을 누르는 압력에 의해 도 9에 도시된 것과 같이 반도체 칩(11)의 모서리 부분에까지 덮이게 된다. 이는 열가소성 수지가 범프(13)의 높이보다 더 높게 형성하였기 때문에 반도체 칩(11)의 모서리 부분에까지 덮여질 수 있기에 충분하다. 한편, 반도체 칩(11)의 범프(13)는 인쇄회로기판(21)의 접합패드(23)와 접합되어 반도체 칩(11)이 인쇄회로기판(21)에 실장된다. 이때 범프(11)의 산화가 열경화성 수지의 도포 전에 실시한 범프 세정 작업에 의해 최소화되었기 때문에 종래에 실시하던 별도의 플럭스 도포 공정은 진행하지 않아도 된다.As shown in FIG. 8, the separated semiconductor chip 11 is aligned with the semiconductor chip 11 at a predetermined position of the printed circuit board 21 such that the bump 13 and the bonding pad 23 come into contact with each other. Press and hold the reflow process. The reflow process maintains a temperature condition of 200-220 ° C. for a long time so that the resin can be in a gel state of a predetermined viscosity, and then creates a maximum temperature condition so that the bump 13 can be sufficiently bonded to the bonding pad 23. do. In this way, the thermoplastic resin is covered to the edge portion of the semiconductor chip 11 by the pressure for pressing the semiconductor chip 11 as shown in FIG. 9. This is sufficient to cover the edge of the semiconductor chip 11 because the thermoplastic resin is formed higher than the height of the bump 13. Meanwhile, the bump 13 of the semiconductor chip 11 is bonded to the bonding pads 23 of the printed circuit board 21 so that the semiconductor chip 11 is mounted on the printed circuit board 21. At this time, since the oxidation of the bump 11 is minimized by the bump cleaning operation performed before the application of the thermosetting resin, a separate flux coating step conventionally performed does not need to be performed.
이상과 같은 플립 칩 본딩 기술을 이용한 반도체 칩 실장 방법은, 전술한 실시예에서 소개한 바와 같이 웨이퍼 상태에서 형성되는 열가소성 수지층의 형성으로 별도의 언더-필 공정을 필요로 하지 않는다. 종래와 같이 충전 소요 시간이나 충전재 흐름성 등은 고려하지 않아도 된다. 따라서, 반도체 칩과 인쇄회로기판 사이의공간에서 충전재의 주입에 필요한 흐름성을 얻기 위해 점도 및 필러의 양과 크기의 제약이 해소되며, 충전재로 사용되는 열가소성 수지의 선택 폭이 넓어진다.The semiconductor chip mounting method using the flip chip bonding technique as described above does not require a separate under-fill process by forming the thermoplastic resin layer formed in the wafer state as described in the above-described embodiment. It is not necessary to consider the charging time, filler flowability, etc. as in the prior art. Therefore, in order to obtain the flowability required for the injection of the filler in the space between the semiconductor chip and the printed circuit board, restrictions on the amount and size of the viscosity and the filler are eliminated, and the selection range of the thermoplastic resin used as the filler is widened.
또한, 열가소성 수지의 형성이 웨이퍼 상태에서 이루어지기 때문에 반도체 칩을 실장할 때마다 언더-필 공정을 실시하는 것보다도 더 단순화된 제조 공정을 갖는다.In addition, since the formation of the thermoplastic resin is performed in the wafer state, it has a simplified manufacturing process than performing the under-fill process every time the semiconductor chip is mounted.
이와 같은 플립 칩 본딩 기술을 이용한 반도체 칩 실장 방법은 반도체 칩을 주기판에 직접 실장하거나 플립 칩 본딩을 이용하는 반도체 칩 패키지의 제조에 모두 적용될 수 있으며, 본 발명의 기술적 중심 사상을 벗어나지 않는 범위 내에서 다양한 형태의 변형 실시가 가능하다.Such a semiconductor chip mounting method using a flip chip bonding technique may be applied to both the direct mounting of a semiconductor chip on a main board or to fabrication of a semiconductor chip package using flip chip bonding, and may be variously performed without departing from the technical spirit of the present invention. Modifications of the form are possible.
이상과 같은 본 발명에 의한 플립 칩 본딩 기술을 이용한 반도체 칩 실장 방법에 따르면, 충전재의 필러 크기나 흐름성을 고려하지 않아도 되어 언더-필에 대한 제약이 크게 감소되고, 반도체 칩 실장 후에 이루어지는 언더-필 공정을 생략할 수 있어 공정이 단순화되고 생산성이 향상된다.According to the semiconductor chip mounting method using the flip chip bonding technique according to the present invention as described above, the fillers do not need to consider the filler size or flowability of the filler material, which significantly reduces the under-fill, and the under-chip formed after the semiconductor chip is mounted. The peel process can be omitted, which simplifies the process and increases productivity.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030049284A (en) * | 2001-12-14 | 2003-06-25 | 삼성전기주식회사 | Package substrate for flip chip bonding |
| KR100484889B1 (en) * | 2002-09-19 | 2005-04-28 | 재단법인서울대학교산학협력재단 | Solderfill for semiconductor package assembly and manufacturing method the same |
| KR100484888B1 (en) * | 2002-11-07 | 2005-04-28 | 재단법인서울대학교산학협력재단 | Flip chip mounting method using a solderfill |
| KR100484891B1 (en) * | 2002-09-18 | 2005-04-28 | 재단법인서울대학교산학협력재단 | One step flip chip mounting method |
| KR100520080B1 (en) * | 2003-07-18 | 2005-10-12 | 삼성전자주식회사 | Surface Mounting Method of Semi-conduct Chip on PCB |
| WO2007114537A1 (en) * | 2006-04-03 | 2007-10-11 | International Display Solutions Co., Ltd. | Flexible printed circuit board having flip chip bonding area with top layer bump and inner layer trace aligned therein |
| KR200453646Y1 (en) * | 2010-12-02 | 2011-05-19 | 임재하 | Exhaust pipe of lift for lift device |
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| KR101518760B1 (en) * | 2014-12-31 | 2015-05-08 | 주식회사 자이스 | Attaching method for chip using conductive adhesive |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09260825A (en) * | 1996-03-18 | 1997-10-03 | Ibiden Co Ltd | Solder feeder |
| JPH09283555A (en) * | 1996-04-16 | 1997-10-31 | Toshiba Corp | Mounting structure of semiconductor chip, manufacture of semiconductor package and semiconductor package |
| KR19980044706A (en) * | 1996-12-07 | 1998-09-05 | 김광호 | Manufacturing Method of Ball Grid Array Package |
| JP4343286B2 (en) * | 1998-07-10 | 2009-10-14 | シチズンホールディングス株式会社 | Manufacturing method of semiconductor device |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030049284A (en) * | 2001-12-14 | 2003-06-25 | 삼성전기주식회사 | Package substrate for flip chip bonding |
| KR100484891B1 (en) * | 2002-09-18 | 2005-04-28 | 재단법인서울대학교산학협력재단 | One step flip chip mounting method |
| KR100484889B1 (en) * | 2002-09-19 | 2005-04-28 | 재단법인서울대학교산학협력재단 | Solderfill for semiconductor package assembly and manufacturing method the same |
| KR100484888B1 (en) * | 2002-11-07 | 2005-04-28 | 재단법인서울대학교산학협력재단 | Flip chip mounting method using a solderfill |
| KR100520080B1 (en) * | 2003-07-18 | 2005-10-12 | 삼성전자주식회사 | Surface Mounting Method of Semi-conduct Chip on PCB |
| WO2007114537A1 (en) * | 2006-04-03 | 2007-10-11 | International Display Solutions Co., Ltd. | Flexible printed circuit board having flip chip bonding area with top layer bump and inner layer trace aligned therein |
| KR200453646Y1 (en) * | 2010-12-02 | 2011-05-19 | 임재하 | Exhaust pipe of lift for lift device |
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| KR100674501B1 (en) | 2007-01-25 |
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