KR20010063499A - Method for forming contact plug of semiconductor device by using low dielectric substance - Google Patents
Method for forming contact plug of semiconductor device by using low dielectric substance Download PDFInfo
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- KR20010063499A KR20010063499A KR1019990060586A KR19990060586A KR20010063499A KR 20010063499 A KR20010063499 A KR 20010063499A KR 1019990060586 A KR1019990060586 A KR 1019990060586A KR 19990060586 A KR19990060586 A KR 19990060586A KR 20010063499 A KR20010063499 A KR 20010063499A
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- low dielectric
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000000126 substance Substances 0.000 title abstract description 5
- 239000003989 dielectric material Substances 0.000 claims abstract description 17
- 239000011229 interlayer Substances 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims abstract description 17
- 150000004767 nitrides Chemical class 0.000 claims abstract description 17
- 238000005498 polishing Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 229920000642 polymer Polymers 0.000 description 12
- 238000007517 polishing process Methods 0.000 description 8
- 238000000151 deposition Methods 0.000 description 4
- 239000002002 slurry Substances 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자 제조 분야에 관한 것으로, 특히 콘택 플러그를 형성하기 위한 식각 공정과 화학적기계적 연마 공정을 이용하여 이웃하는 플러그를 물리적 및 전기적으로 분리하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor device manufacturing, and more particularly to a method for physically and electrically separating neighboring plugs using an etching process and a chemical mechanical polishing process for forming contact plugs.
종래의 EM(enlarged margin) SAC(self align contact) 공정 방법을 첨부된 도면 도1a 내지 도1c 그리고 도2를 참조하여 설명한다. 도1a 내지 도1c의 (A)는 도2의 A-A' 선을 따른 단면도이고, (B)는 B-B' 선을 따른 단면도이다.A conventional method of enlarging margin (EM) self align contact (SAC) will be described with reference to FIGS. 1A to 1C and FIG. 2. (A) is sectional drawing along the AA 'line of FIG. 2, (B) is sectional drawing along the BB' line.
도1a의 (A) 및 (B)는 게이트 산화막(11) 상에 형성된 장벽금속막 또는 폴리실리콘막으로 이루어지는 제1 전도막(12), 텅스텐 또는 실리사이드로 이루어지는 제2 전도막(13), 완충산화막(14) 및 마스크 질화막(15)을 선택적으로 식각하여 워드라인을 형성하고, 완료된 반도체 기판(10) 상부에 층간절연 산화막(17)을 증착하고 평탄화를 위한 화학적기계적연마(chemical mechanical polishing, 이하 CMP라 함) 공정을 실시한 상태를 보이고 있다. 이때, 후속으로 진행되는 SAC 공정에서 층간절연 산화막(17)에 대한 마스크 질화막(15)의 식각 선택비를 확보하기 위하여 층간절연 산화막(17)의 CMP 후 마스크 질화막(15) 상에 1500 Å 두께(d1)의 층간절연 산화막(17)이 잔류하여야 한다.1A and 1B show a first conductive film 12 made of a barrier metal film or a polysilicon film formed on the gate oxide film 11, a second conductive film 13 made of tungsten or silicide, and a buffer The oxide film 14 and the mask nitride film 15 are selectively etched to form word lines, and the interlayer insulating oxide film 17 is deposited on the completed semiconductor substrate 10 and chemical mechanical polishing (hereinafter, referred to as planarization) is performed. CMP) process is shown. In this case, in order to secure the etching selectivity of the mask nitride film 15 with respect to the interlayer insulating oxide film 17 in a subsequent SAC process, a thickness of 1500 Å on the mask nitride film 15 after the CMP of the interlayer insulating oxide film 17 ( The interlayer insulating oxide film 17 of d1) must remain.
도1b의(A) 및 (B)는 CMP 공정이 완료된 층간절연 산화막(17) 상에 'I'자형 또는 'T'자형 마스크를 사용하여 플러그 형성 영역의 층간절연 산화막(17)을 노출시키는 포토레지스트 패턴(PR)을 형성한 것을 보이고 있다.1B and (B) show a photo exposing the interlayer insulating oxide film 17 in the plug formation region by using an 'I' or 'T' shape mask on the interlayer insulating oxide film 17 on which the CMP process is completed. It has shown that the resist pattern PR was formed.
도1c의 (A) 및 (B)는 상기 포토레지스트 패턴(PR)을 식각마스크로 이용한 SAC 공정으로 층간절연 산화막(17) 및 게이트 산화막(11)을 선택적으로 제거하여플러그와 접할 반도체 기판(10)을 노출시킨 상태를 보이고 있다. 이러한 SAC 공정 과정에서 마스크 질화막(15)의 손실이 발생하여 단차(d2)가 발생한다.1A and 1B illustrate a semiconductor substrate 10 to be in contact with a plug by selectively removing the interlayer insulating oxide layer 17 and the gate oxide layer 11 by an SAC process using the photoresist pattern PR as an etching mask. ) Is exposed. In this SAC process, the loss of the mask nitride film 15 occurs, resulting in a step d2.
후속 플러그용 전도막의 CMP 공정에서 이때 발생된 약 500 Å 높이의 단차로 인해 이웃하는 플러그가 연결되는 것을 방지하기 위하여 과도연마를 진행하여야 한다. 미설명 도면부호 'T'는 이러한 과도연마 종점을 나타낸다.In the subsequent CMP process of the conductive film for the plug, over-polishing should be performed to prevent the neighboring plug from being connected due to the step difference of about 500 Å. Unexplained reference numeral 'T' indicates this end of overpolishing.
전술한 바와 같은 연마 과정에서는 산화막, 전도막, 질화막 등의 각기 다른 성질의 물질을 연마해야 하기 때문에 콘택 플러그의 완전한 분리를 위하여 과도연마를 필수적으로 실시하여야 하는데, 이로 인해 다시 워드라인 상부의 마스크 질화막(15)의 손실이 발생하게 되고, 심할 경우 워드라인이 노출되는 문제가 발생한다. 워드라인이 노출되지 않도록 하기 위하여 연마 두께를 감소시키면 도1c의 (B)와 같이 발생한 단차 부분에 플러그용 전도막의 잔여물이 잔류하게 되고, 잔류된 전도막은 후속 공정에서 원치않는 연결 통로로 작용하여 소자의 불량을 야기시킨다.In the polishing process as described above, since materials of different properties such as oxide film, conductive film, and nitride film must be polished, over-polishing is essential for the complete separation of the contact plug. A loss of (15) occurs and, in severe cases, a word line is exposed. If the polishing thickness is reduced to prevent the word line from being exposed, the residue of the plug conductive film remains in the stepped portion as shown in FIG. 1C, and the remaining conductive film serves as an unwanted connection path in a subsequent process. Cause device failure.
상기와 같은 문제점을 해결하기 위한 본 발명은 콘택 플러그 형성 과정에서 단차 발생을 유발하지 않아 과도연마 공정을 생략하고 소자의 불량을 효과적으로 방지할 수 있는, 반도체 소자의 콘택 플러그 형성 방법을 제공하는데 그 목적이 있다.The present invention for solving the above problems does not cause a step in the process of forming a contact plug to omit the over-polishing process and to effectively prevent the defect of the device, to provide a method for forming a contact plug of a semiconductor device There is this.
도1a 내지 도1c는 종래 기술에 따른 반도체 소자의 콘택 플러그 형성 공정 단면도,1A to 1C are cross-sectional views of a process for forming a contact plug of a semiconductor device according to the prior art;
도2는 워드라인과 콘택 플러그의 배치를 개략적으로 보이는 레이아웃,2 is a layout schematically showing the arrangement of a word line and a contact plug;
도3a 내지 도3f는 본 발명의 실시예에 따른 반도체 소자의 콘택 플러그 형성 공정 단면도.3A to 3F are cross-sectional views of a process for forming a contact plug of a semiconductor device according to an embodiment of the present invention.
*도면의 주요부분에 대한 도면 부호의 설명** Description of reference numerals for the main parts of the drawings *
35: 마스크 절연막 37: 저유전 폴리머35: mask insulating film 37: low dielectric polymer
38: 실렌-산화막38: silane-oxide
상기와 같은 목적을 달성하기 위한 본 발명은 그 상부가 질화막으로 덮인 워드라인 형성이 완료된 반도체 기판 상에 저유전 물질막을 도포하는 제1 단계; 상기 저유전물질막을 선택적으로 식각하여 플러그 영역의 상기 반도체 기판을 노출시키는 제2 단계; 상기 제2 단계가 완료된 전체 구조 상에 전도막을 형성하는 제3 단계; 상기 전도막을 식각하여 상기 저유전물질막을 노출시키는 제4 단계 상기 저유전물질막을 제거하는 제5 단계; 상기 제5 단계가 완료된 전체 구조 상에 층간절연 산화막을 형성하는 제6 단계; 및 상기 워드라인 상부의 상기 질화막이 노출될 때까지 상기 층간절연 산화막 및 상기 플러그 영역의 상기 전도막을 연마하여 플러그를 형성하는 제7 단계를 포함하는 반도체 소자의 콘택 플러그 형성 방법을 제공한다.The present invention for achieving the above object is a first step of applying a low dielectric material film on the semiconductor substrate is completed, the word line is covered with a nitride film on top; Selectively etching the low dielectric material film to expose the semiconductor substrate in a plug region; A third step of forming a conductive film on the entire structure of which the second step is completed; A fourth step of etching the conductive film to expose the low dielectric material film; a fifth step of removing the low dielectric material film; A sixth step of forming an interlayer insulating oxide film on the entire structure in which the fifth step is completed; And a seventh step of forming a plug by polishing the interlayer insulating oxide film and the conductive film of the plug region until the nitride film on the word line is exposed.
본 발명은 SAC 공정시 워드라인을 덮고 있는 마스크 질화막의 손실을 감소시키고 콘택 플러그 형성의 공정 마진을 확보하기 위한 것으로, 워드라인 형성이 완료된 반도체 기판 상부에 유전율이 2.3 내지 2.9인 저유전 물질막을 증착하고 선택적으로 식각하여 플러그와 접할 반도체 기판 부분을 노출시킨 다음, 플러그용 전도막 증착 및 CMP 공정을 진행하여 플러그를 형성하고, 저유전물질막을 제거한 다음, 층간절연 산화막을 형성하고 연마공정을 실시하여 플러그를 노출시키는데 특징이 있다.The present invention is to reduce the loss of the mask nitride film covering the word line during the SAC process and to secure the process margin of contact plug formation, depositing a low dielectric material film having a dielectric constant of 2.3 to 2.9 on the semiconductor substrate where the word line formation is completed And selectively etch to expose the portion of the semiconductor substrate to be in contact with the plug. Then, the plug conductive film deposition and CMP process are performed to form a plug, the low dielectric material film is removed, an interlayer insulating oxide film is formed, and the polishing process It is characterized by exposing the plug.
이하, 도2 및 도3a 내지 도3f를 참조하여 본 발명의 실시예에 따른 콘택 플러그 형성 방법을 설명한다. 도3a 내지 도3f의 (A)는 도2의 A-A' 선을 따른 단면도이고, (B)는 B-B' 선을 따른 단면도이다.Hereinafter, a method for forming a contact plug according to an embodiment of the present invention will be described with reference to FIGS. 2 and 3A to 3F. 3A to 3F are cross-sectional views taken along a line A-A 'of FIG. 2, and (B) is a cross-sectional view taken along a line B-B'.
먼저 도3a의 (A) 및 (B)에 도시한 바와 같이, 게이트 산화막(31) 상에 형성된 장벽금속막 또는 폴리실리콘막으로 이루어지는 제1 전도막(32), 텅스텐 또는 실리사이드로 이루어지는 제2 전도막(33), 완충산화막(34) 및 마스크 질화막(35)을 선택적으로 식각하여 워드라인을 형성하고, 완료된 반도체 기판(30) 상부에 마스크 질화막(35)에 대한 식각선택비가 40 이상이고 유전율이 2.65인 SiLK(C86H56On) 등의 저유전 폴리머(37)를 6000 Å 두께로 도포한다. 상기 저유전 폴리머(37)를 대신하여 유전율이 2.65인 BCB(bis-benzocycle buten), 유전율이 2.7인 메틸실세큐옥산(methylsilsesquioxane), 유전율이 2.9인 APL(advenced planarization layer), 유전율이 2.7인 파릴렌-엔(parlylene-N), 유전율이 2.3인 파릴렌-에프(parlylene-F) 등을 형성할 수도 있다.First, as shown in FIGS. 3A and 3B, the first conductive film 32 made of the barrier metal film or the polysilicon film formed on the gate oxide film 31, the second conductive film made of tungsten or silicide The film 33, the buffer oxide film 34, and the mask nitride film 35 are selectively etched to form a word line, and the etching selectivity for the mask nitride film 35 is over 40 on the completed semiconductor substrate 30 and the dielectric constant is A low dielectric polymer 37, such as SiLK (C 86 H 56 O n ), which is 2.65, is applied to a thickness of 6000 kPa. In place of the low dielectric polymer 37, a bis-benzocycle buten (BCB) having a dielectric constant of 2.65, methylsilsesquioxane having a dielectric constant of 2.7, an advanced planarization layer (APL) having a dielectric constant of 2.9, and a parryl having a dielectric constant of 2.7 Parlylene-N, parlylene-F having a dielectric constant of 2.3, and the like.
저유전 폴리머(37)는 포토레지스트와 식각선택비 차이가 거의 나지 않기 때문에 하드마스크를 형성하여야 한다. 따라서, 본 발명의 실시예에서는 저유전 폴리머(37) 상에 포토레지스트에 대한 식각 선택비가 3:1 이상이고, 저유전 폴리머(37)에 대한 식각선택비가 2:1 이상인 실렌-산화막(38) 등을 2000 Å 두께로 증착하고, 이를 패터닝하여 하드마스크로 이용한다. 상기 실렌-산화막(38)은 다음의 화학식1에 따라 형성된 산화막이다.Since the low dielectric polymer 37 has little difference in etching selectivity from the photoresist, a hard mask must be formed. Therefore, in the exemplary embodiment of the present invention, the silane selectivity of the photoresist on the low dielectric polymer 37 is 3: 1 or more, and the silane selectivity ratio of the low dielectric polymer 37 is 2: 1 or more. Etc. are deposited to a thickness of 2000 mm 3, and then patterned and used as a hard mask. The silane-oxide film 38 is an oxide film formed according to the following Chemical Formula 1.
다음으로 도3b에 도시한 바와 같이 하드마스크 패턴 형성을 위해 실렌-산화막(38)을 식각하는 공정과 저유전 폴리머(37) 및 게이트 산화막(31)을 식각하는 공정을 각각 30 % 과도식각으로 진행하여 워드라인 상부를 덮고 있는 마스크 질화막(35)의 손실은 100 Å 이내로 조절하면서 플러그와 연결될 반도체 기판(30)을 노출시킨다.Next, as shown in FIG. 3B, the process of etching the silane-oxide film 38 and the process of etching the low dielectric polymer 37 and the gate oxide film 31 are performed at 30% transient etching, respectively, to form a hard mask pattern. As a result, the loss of the mask nitride film 35 covering the upper portion of the word line is exposed to within 100 mW, thereby exposing the semiconductor substrate 30 to be connected to the plug.
이어서 도3c에 도시한 바와 같이 전체 구조 상에 플러그를 이룰 3000 Å 두께의 폴리실리콘막(39)을 증착한다. 폴리실리콘막(39) 증착 과정에서 저유전 폴리머(37)가 열화되는 것을 방지하기 위하여 일반적인 모노-실란계(monosilane, SiH4)가 아닌 디-실란계(disilane, Si2H6)를 저압화학기상증착법(low pressure chemical vapor deposition) 방법으로 증착하며, 이때 최대 증착온도는 480 ℃가 되도록 한다.Then, as shown in Fig. 3C, a polysilicon film 39 having a thickness of 3000 Å is deposited on the entire structure. In order to prevent the low dielectric polymer 37 from deteriorating during the deposition of the polysilicon film 39, a disilane (Si 2 H 6 ), rather than a general monosilane (SiH 4 ) is used. It is deposited by low pressure chemical vapor deposition, and the maximum deposition temperature is 480 ℃.
다음으로 도3d에 도시한 바와 같이, 저유전 폴리머(37) 상부의 폴리실리콘막(39)을 에치백(etch back)한다. 이때, 워드라인 상부의 폴리실리콘(39)막도 에치백하여 이후 워드라인 절연막을 평탄화하기 위한 CMP 공정의 연마 대상 두께를 감소시켜 전체적으로 연마 균일도가 향상되도록 한다.Next, as shown in FIG. 3D, the polysilicon film 39 on the low dielectric polymer 37 is etched back. At this time, the polysilicon 39 film on the word line is also etched back to reduce the polishing target thickness of the CMP process to planarize the word line insulating film to improve the polishing uniformity as a whole.
이후 진행되는 캐패시터 형성 공정은 저유전 폴리머(37)의 열화가 발생하는 고온에서 진행되기 때문에 캐패시터 형성 이전에 저유전 폴리머(37) 제거 공정을 진행하여야 한다.Going on Since the capacitor formation process is performed at a high temperature where deterioration of the low dielectric polymer 37 occurs, the low dielectric polymer 37 removal process must be performed before the formation of the capacitor.
따라서 도3e에 도시한 바와 같이, 실렌-산화막(38) 및 저유전 폴리머(37)를 제거하고, 전체 구조 상에 층간절연 산화막(40)을 증착한다. 이때, 마스크 질화막(35) 상의 층간절연 산화막(40) 두께는 500 Å 정도가 되도록 하여, 이후 실시될 연마공정의 부담을 줄이고 연마 균일도를 향상시킨다.Therefore, as shown in Fig. 3E, the silane-oxide film 38 and the low dielectric polymer 37 are removed, and the interlayer insulating oxide film 40 is deposited over the entire structure. At this time, the thickness of the interlayer dielectric oxide film 40 on the mask nitride film 35 is about 500 GPa, thereby reducing the burden of the polishing process to be performed later and improving the polishing uniformity.
다음으로 도3f에 도시한 바와 같이, 콜로이드(colloidal) 또는 슬러리 입자와 입자가 연결되어 있는 퓸드(fumed) 형태의 SiO2, ZrO2또는 CeO2계 슬러리로 층간절연 산화막(40) 및 폴리실리콘막(30)을 연마하여 폴리실리콘막(39)으로 이루어지는 플러그를 형성한다. 이때, 마스크 질화막(35)의 단차 부분도 함께 연마하여 제거한다. 한편, 상기 슬러리 내의 연마제 농도는 0.5 wt % 내지 10 wt %, 연마제의 수소이온 농도(pH)는 3 내지 10이 되도록 한다.Next, as shown in FIG. 3F, the interlayer insulating oxide film 40 and the polysilicon film are formed of fumed SiO 2 , ZrO 2, or CeO 2 based slurry in which colloidal or slurry particles and particles are connected. (30) is polished to form a plug made of the polysilicon film (39). At this time, the stepped portion of the mask nitride film 35 is also polished and removed. Meanwhile, the abrasive concentration in the slurry is 0.5 wt% to 10 wt%, and the hydrogen ion concentration (pH) of the abrasive is 3 to 10.
전술한 바와 같이 이루어지는 본 발명은 플러그 형성을 위해 CMP 공정으로 제거해야 두께가 1000 Å 이하로 감소하여 연마공정의 부담이 감소한다. 따라서, 여러가지 슬러리를 사용하여 다단계로 CMP 공정을 실시하지 않아도 되기 때문에 웨이퍼의 시간당 처리량을 증가시킬 수 있으며 연마 균일도를 향상시키고 전, 후속 공정의 여유도 확보로 반도체 소자의 수율 및 생산량을 증가시킬 수 있다.The present invention made as described above should be removed by the CMP process to form a plug, the thickness is reduced to less than 1000 kPa to reduce the burden of the polishing process. Therefore, the multi-stage CMP process can be avoided by using various slurries, which can increase the throughput per hour of the wafer, improve the uniformity of the wafer, and increase the yield and yield of the semiconductor device by securing the margin of the previous and subsequent processes. have.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 이웃하는 플러그를 분리시키기 위한 CMP 공정에서의 연마대상 두께가 1000 Å 이하로 감소하여 연마공정의 부담이 감소하므로 연마공정을 보다 단순화시킬 수 있어 웨이퍼의 시간당 처리량을 증가시키고, 연마 균일도 확보와 전, 후속 공정의 여유도를 확보하여 반도체 소자의 수율 및 생산성을 향상시킬 수 있다.In the present invention made as described above, the thickness of the polishing target in the CMP process for separating neighboring plugs is reduced to 1000 mm or less, thereby reducing the burden of the polishing process, thereby simplifying the polishing process, thereby increasing the throughput per wafer. In addition, it is possible to improve the yield and productivity of the semiconductor device by ensuring the polishing uniformity and the margin of the previous and subsequent processes.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100427718B1 (en) * | 2002-06-29 | 2004-04-28 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
| KR100439771B1 (en) * | 2001-12-15 | 2004-07-12 | 주식회사 하이닉스반도체 | Method for preventing hardmask loss of semicondctor device |
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1999
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100439771B1 (en) * | 2001-12-15 | 2004-07-12 | 주식회사 하이닉스반도체 | Method for preventing hardmask loss of semicondctor device |
| KR100427718B1 (en) * | 2002-06-29 | 2004-04-28 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
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