KR20000044554A - Method for fabricating polysilicon plug - Google Patents
Method for fabricating polysilicon plug Download PDFInfo
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- KR20000044554A KR20000044554A KR1019980061053A KR19980061053A KR20000044554A KR 20000044554 A KR20000044554 A KR 20000044554A KR 1019980061053 A KR1019980061053 A KR 1019980061053A KR 19980061053 A KR19980061053 A KR 19980061053A KR 20000044554 A KR20000044554 A KR 20000044554A
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- film
- polysilicon
- forming
- polishing
- interlayer insulating
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 61
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 61
- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000005498 polishing Methods 0.000 claims abstract description 48
- 239000011229 interlayer Substances 0.000 claims abstract description 37
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 239000000126 substance Substances 0.000 claims abstract description 15
- 239000002002 slurry Substances 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims description 3
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims description 3
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 claims description 2
- 229910010037 TiAlN Inorganic materials 0.000 claims 1
- 238000007517 polishing process Methods 0.000 abstract description 10
- 238000009413 insulation Methods 0.000 abstract 5
- 238000000151 deposition Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000003628 erosive effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000011856 silicon-based particle Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
본 발명은 반도체 소자 제조 분야에 관한 것으로, 특히 폴리실리콘 플러그(polysilicon plug) 형성 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a method for forming a polysilicon plug.
일반적으로 폴리실리콘 플러그 형성 공정에서는 화학적 기계적 연마(chemical mechanical polishing) 공정이 이용된다. 즉, 반도체 기판 상에 형성된 층간절연막을 사진공정과 식각공정을 실시하여 선택적으로 제거해서 콘택홀을 형성하고, 플러그 형성용 폴리실리콘막을 증착한 다음 화학적 기계적 연마 공정을 실시하여 층간절연막 상에 있는 모든 폴리실리콘막을 제거하여 콘택홀 내에 폴리실리콘 플러그를 형성한다. 이러한, 폴리실리콘막 연마 공정에서는 폴리실리콘막과 산화막의 연마 특성이 유사하기 때문에 산화막 제거용 슬러리(slurry)를 사용하여 평탄화공정을 실시하는데, 폴리실리콘막과 산화막인 층간절연막간의 연마선택비가 낮음으로 인하여 연마 공정시 층간절연막 상에 있는 폴리실리콘막을 모두 제거하는 동안 콘택홀 내부의 폴리실리콘막이 과도하게 연마되는 디싱(dishing) 현상이 발생할 수 있으며, 또한 폴리실리콘 플러그의 밀도가 높은 지역의 경우 층간절연막이 과도하게 연마되는 침식(erosion)이 일어나게 되어 폴리실리콘의 결정 성장을 불균일하게 하여 전기적 특성을 약화시키는 결과를 낳는다. 또한, 평탄화 공정시 발생하는 연마 불균일도에 따라 층간절연막 상에 잔류하는 폴리실리콘막에 의해 이후 실시되는 열처리 과정에서 실리콘 입자들이 층간절연막 내부로 확산되면서 폴리실리콘 플러그 콘택의 누설 전류를 증가시킨다.In general, a chemical mechanical polishing process is used in the polysilicon plug forming process. That is, the interlayer insulating film formed on the semiconductor substrate is selectively removed by performing a photo process and an etching process to form a contact hole, a polysilicon film for plug formation is deposited, and then a chemical mechanical polishing process is performed to remove all the interlayer insulating film on the interlayer insulating film. The polysilicon film is removed to form a polysilicon plug in the contact hole. In the polysilicon film polishing process, since the polishing properties of the polysilicon film and the oxide film are similar, the planarization process is performed using a slurry for removing the oxide film, and the polishing selectivity between the polysilicon film and the interlayer insulating film as the oxide film is low. As a result, a dishing phenomenon may occur in which the polysilicon film inside the contact hole is excessively polished while removing all of the polysilicon film on the interlayer insulating film during the polishing process. This excessively polished erosion occurs, resulting in non-uniform crystal growth of polysilicon and weakening electrical properties. In addition, according to the polishing non-uniformity generated during the planarization process, the silicon particles are diffused into the interlayer insulating film by the polysilicon film remaining on the interlayer insulating film, thereby increasing the leakage current of the polysilicon plug contact.
이러한 문제점을 해결하기 위하여 화학적 기계적 연마시 폴리실리콘막과 층간절연막간의 연마선택비가 좋은 폴리실리콘 연마용 슬러리를 이용하는 방법이 제시되기도 하였다. 그러나, 이 방법은 폴리실리콘 연마용 슬러리 형성을 위한 별도의 혼합장치 및 공급 장치를 준비해야 하고, 또한 산화막 연마용 슬러리와 혼재하여 사용할 경우 화학적 기계적 연마 공정을 거치는 다른 소자 제조 공정에서 원하지 않는 오염 입자(particle)가 발생하게 된다.In order to solve this problem, a method of using a polysilicon polishing slurry having a good polishing selectivity between the polysilicon film and the interlayer insulating film during chemical mechanical polishing has been proposed. However, this method requires the preparation of a separate mixing device and a supply device for forming a polysilicon polishing slurry, and also when used in combination with an oxide polishing slurry, unwanted contaminant particles in other device fabrication processes undergoing a chemical mechanical polishing process. Particles are generated.
도1 내지 도3을 참조하여 종래 기술에 따른 폴리실리콘 플러그 형성 방법의 문제점을 보다 상세히 설명한다.Referring to Figures 1 to 3 will be described in more detail the problem of the polysilicon plug forming method according to the prior art.
도1은 워드라인(11) 등의 형성이 완료된 반도체 기판(10) 상에 층간절연막(11)을 형성하고, 사진 공정과 식각 공정을 통해 층간절연막(11)을 선택적으로 식각하여 반도체 기판(10)을 노출시키는 콘택홀(13)을 형성한 다음, 플러그 형성을 위한 폴리실리콘막(14)을 전체 구조 상에 형성한 상태를 보이고 있다.1 shows an interlayer insulating film 11 formed on a semiconductor substrate 10 on which word lines 11 and the like are formed, and selectively etches the interlayer insulating film 11 through a photo process and an etching process. ), And then the polysilicon film 14 for plug formation is formed on the entire structure.
이어서, 산화막 연마용 슬러리를 이용하여 층간절연막(12)이 노출될 때까지 화학적 기계적 연마 공정을 실시해서, 층간절연막(12) 상에 폴리실리콘막(14)이 잔류되지 않도록 한다.Subsequently, the chemical mechanical polishing process is performed using the oxide film polishing slurry until the interlayer insulating film 12 is exposed to prevent the polysilicon film 14 from remaining on the interlayer insulating film 12.
이때, 산화막 연마용 슬러리를 사용한 연마 공정시 연마대상막인 폴리실리콘막(14)과 산화막으로 형성되는 층간절연막(12)간의 연마 선택비가 그리 크지 않아서 도2에 도시한 바와 같이 평탄화 공정시 층간절연막(12) 상에 있는 폴리실리콘막(14)을 모두 제거하는 동안 콘택홀(13) 내부의 폴리실리콘막(14)이 과도하게 연마되는 디싱 현상이 발생할 수 있으며, 폴리실리콘 플러그의 밀도가 높은 지역의 경우는 도3에 도시한 바와 같이 층간절연막이 과도하게 연마되는 침식이 일어나게 된다. 이에 따라, 콘택홀 내에 형성된 폴리실리콘 플러그간의 절연이 효과적으로 이루어지지 못하거나, 화학적 기계적 평탄화 공정시 발생하게 되는 연마 불균일에 의하여 층간절연막 상에 잔류되는 폴리실리콘막은 이후 실시되는 열처리 공정에서 실리콘 입자들이 층간절연막 내부로 확산되면서 폴리실리콘 플러그 콘택의 누설 전류를 증가시킨다.At this time, the polishing selectivity between the polysilicon film 14, which is the film to be polished, and the interlayer insulating film 12 formed of the oxide film during the polishing process using the oxide film polishing slurry was not so large, as shown in FIG. 2. During the removal of all of the polysilicon film 14 on the (12), dishing phenomenon may occur, in which the polysilicon film 14 inside the contact hole 13 is excessively polished, and a region having a high density of the polysilicon plug may occur. In this case, as shown in Fig. 3, erosion of the interlayer insulating film is excessively polished occurs. Accordingly, the polysilicon film remaining on the interlayer insulating film may not be effectively insulated between the polysilicon plugs formed in the contact hole or the polishing nonuniformity generated during the chemical mechanical planarization process. Diffusion into the insulating film increases the leakage current of the polysilicon plug contacts.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 폴리실리콘 플러그 형성 과정에서 실시되는 화학적 기계적 연마를 보다 정확하게 조절할 수 있는, 연마정지막을 이용한 폴리실리콘 플러그 형성 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is an object of the present invention to provide a polysilicon plug forming method using a polishing stop film that can more accurately control the chemical mechanical polishing carried out in the polysilicon plug forming process.
도1 내지 도3은 종래 기술에 따른 폴리실리콘 플러그 형성 공정 단면도,1 to 3 is a cross-sectional view of the polysilicon plug forming process according to the prior art,
도4는 본 발명의 일실시예에 따른 폴리실리콘 플러그 형성 공정 단면도.Figure 4 is a cross-sectional view of the polysilicon plug forming process according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 도면 부호의 설명* Explanation of reference numerals for the main parts of the drawings
10, 20: 반도체 기판 12, 21: 층간절연막10, 20: semiconductor substrate 12, 21: interlayer insulating film
13, 23: 콘택홀 14, 24: 폴리실리콘막13 and 23: contact holes 14 and 24: polysilicon film
22: 연마정지막22: polishing stop film
상기와 같은 목적을 달성하기 위한 본 발명은 반도체 기판 상에 형성된 층간절연막을 형성하는 제1 단계; 상기 층간절연막 상에 연마정지막을 형성하는 제2 단계; 상기 연마정지막 및 상기 층간절연막을 선택적으로 식각하여 콘택홀을 형성하는 제3 단계; 상기 제3 단계가 완료된 전체 구조 상에 폴리실리콘막을 형성하는 제4 단계; 및 상기 폴리실리콘막을 화학적 기계적 연마(chemical mechanical polishing)하여 폴리실리콘 플러그를 형성하는 제5 단계를 포함하는 반도체 소자의 폴리실리콘 플러그 형성 방법을 제공한다.The present invention for achieving the above object is a first step of forming an interlayer insulating film formed on a semiconductor substrate; Forming a polishing stop film on the interlayer insulating film; Forming a contact hole by selectively etching the polishing stop layer and the interlayer insulating layer; A fourth step of forming a polysilicon film on the entire structure in which the third step is completed; And a fifth step of forming a polysilicon plug by chemical mechanical polishing of the polysilicon film.
본 발명은 층간절연막 상에 TiN 또는 A1TiN 등으로 연마정지막을 미리 증착하고, 연마정지막 및 층간절연막을 선택적으로 식각하여 콘택홀을 형성한 다음, 플러그 형성을 위한 폴리실리콘막을 형성하고, 연마정지막이 노출될 때까지 폴리실리콘막을 화학적 기계적 연마하는데 그 특징이 있다. 이에 따라. 웨이퍼의 평탄도를 월등히 개선시킬 수 있을 뿐만 아니라 종래에 사용되던 산화막 연마용 슬러리만으로도 연마 선택비를 뛰어나게 개선시킬 수 있고, 전, 후속 공정 여유도를 확보할 수 있다.According to the present invention, a polishing stop film is deposited on the interlayer insulating film with TiN or A1TiN or the like in advance, and the contact hole is formed by selectively etching the polishing stop film and the interlayer insulating film, and then a polysilicon film for plug formation is formed. It is characterized by chemical mechanical polishing of the polysilicon film until it is exposed. Accordingly. Not only can the flatness of the wafer be significantly improved, but also the polishing slurry used in the related art can be excellently improved in polishing selection ratio, and the pre and subsequent process margin can be secured.
본 발명의 일실시예에 따른 폴리실리콘 플러그 형성 방법을 도4를 참조하여 보다 상세히 설명한다.A method of forming a polysilicon plug according to an embodiment of the present invention will be described in more detail with reference to FIG. 4.
도4에 도시한 바와 같이, 워드라인(도시하지 않음) 등의 형성이 완료된 반도체 기판(20) 상에 2000 Å 내지 10,000 Å 두께의 층간절연막(21)을 형성하고, 화학적 기계적 연마공정으로 1000 Å 내지 7000 Å 두께의 층간절연막(21)을 연마하여 평탄화시킨다. 이때, 연마제로는 실리카(SiO2), 세리아(CeO2), 알루미나(A12O3) 등으로 구성된 슬러리를 사용한다.As shown in Fig. 4, an interlayer insulating film 21 having a thickness of 2000 Å to 10,000 Å is formed on the semiconductor substrate 20 on which word lines (not shown) and the like have been formed, and then 1000 Å by a chemical mechanical polishing process. The interlayer insulating film 21 having a thickness of 7000 Å is polished and planarized. In this case, as the abrasive, a slurry composed of silica (SiO 2 ), ceria (CeO 2 ), alumina (A1 2 O 3 ), or the like is used.
이어서, 층간절연막(21) 상에 연마정지막(22)을 형성한다. 이때, 연마정지막(22)은 200 ℃ 내지 1000 ℃ 온도에서 화학기상증착법(chemical vapor deposition) 방법으로 형성된 100 Å 내지 3000 Å 두께의 TiN막일 수도 있다. TiN막에서 Ti와 N 각각의 농도는 0.1 WT% 내지 100 WT%의 범위가 되도록 한다. 또한, 상기 연마정지막(22)은 화학기상증착법으로 형성된 A1TiN막일 수도 있으며, A1TiN막에서 A1, Ti 및 N 각각의 농도는 0.1 WT% 내지 10 WT%가 되도록 한다.Subsequently, the polishing stop film 22 is formed on the interlayer insulating film 21. In this case, the polishing stop film 22 may be a TiN film having a thickness of 100 GPa to 3000 GPa formed by a chemical vapor deposition method at a temperature of 200 ° C to 1000 ° C. The concentration of Ti and N in the TiN film is in the range of 0.1 WT% to 100 WT%. In addition, the polishing stop film 22 may be an A1TiN film formed by chemical vapor deposition, and the concentration of each of A1, Ti, and N in the A1TiN film is 0.1 WT% to 10 WT%.
다음으로, 연마정지막(22) 및 층간절연막(21)을 선택적으로 식각하여 그 깊이가 2000 Å 내지 5000 Å인 콘택홀을 형성하고, 콘택홀 형성이 완료된 전체 구조 상에 화학기상증착법으로 1000 Å 내지 10,000 Å 두께의 폴리실리콘막(24)을 증착한다.Next, the polishing stop film 22 and the interlayer insulating film 21 are selectively etched to form contact holes having a depth of 2000 to 5000 Å, and 1000 Å by chemical vapor deposition on the entire structure of contact hole formation. A polysilicon film 24 having a thickness of 10,000 kPa is deposited.
이어서, 실리카, 세리아, 알루미나 등으로 구성되며 농도가 1 WT% 내지 30 WT%이고 수소이온농도가 2 pH 내지 13 pH인 슬러리를 사용하여 1 psi 내지 10 psi의 압력에서 폴리실리콘막(24)을 화학적 기계적 연마한다.Subsequently, the polysilicon film 24 was formed at a pressure of 1 psi to 10 psi using a slurry composed of silica, ceria, alumina, and the like, having a concentration of 1 WT% to 30 WT% and a hydrogen ion concentration of 2 to 13 pH. Chemical mechanical polishing.
이후, 연마정지막(22)을 완전히 제거하기 위한 공정을 실시할 수도 있다. 이때, TiN막으로 형성된 연마정지막(22) 제거시 HC1, H2SO4, NH4OH, HNO3, HF 등을 각각 사용하거나 혼합하여 사용한다.Thereafter, a process for completely removing the polishing stop film 22 may be performed. At this time, HC1, H 2 SO 4 , NH 4 OH, HNO 3 , HF, etc. are used or mixed when the polishing stop film 22 formed of the TiN film is removed.
전술한 바와 같이 이루어지는 본 발명의 일실시예에 따른 폴리실리콘 플러그 형성 공정에서는, 연마제 보다 경도가 휠씬 큰 TiN 또는 AlTiN을 연마정지막으로 사용한다. 이에 따라 연마정지막과 폴리실리콘막의 연마 선택비가 크기 때문에 폴리실리콘막을 연마하기 위한 전용 슬러리를 사용할 필요가 없을 뿐만 아니라, 폴리실리콘막이 잔류되는 것을 방지하기 위하여 과도연마(over polishing)를 실시하는 경우에도 층간절연막이 손상되는 것을 방지할 수 있어 평탄도를 확보할 수 있으며 공정 여유도를 증가시킬 수 있고 이에 따라 생산성을 향상시킬 수 있다.In the polysilicon plug forming process according to the embodiment of the present invention made as described above, TiN or AlTiN having a much higher hardness than the abrasive is used as the polishing stop film. As a result, the polishing selectivity between the polishing stop film and the polysilicon film is large, so that it is not necessary to use a dedicated slurry for polishing the polysilicon film, and even when overpolishing is performed to prevent the polysilicon film from remaining. It is possible to prevent the interlayer insulating film from being damaged, thereby ensuring flatness, increasing process margins, and thus improving productivity.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 층간절연막 상에 연마정지막을 형성하고, 연마정지막 및 층간절연막을 선택적으로 식각하여 콘택홀을 형성한 다음, 폴리실리콘막을 증착하고 화학적 기계적 평탄화 공정을 실시함으로써 웨이퍼의 평탄도를 월등히 개선할 수 있고 폴리실리콘막 전용 슬러리 없이도 연마선택비를 증가시킬 수 있으며, 전,후속 공정 여유도를 증가시킬 수 있어 반도체 소자의 수율 및 생산성을 향상시킬 수 있다.According to the present invention as described above, the polishing stop film is formed on the interlayer insulating film, the etching stop film and the interlayer insulating film are selectively etched to form a contact hole, and then the polysilicon film is deposited and the chemical mechanical planarization process is performed to planarize the wafer. It is possible to greatly improve the degree, increase the polishing selectivity even without a slurry for polysilicon film, and can increase the yield margin and productivity of the semiconductor device can be increased before and after the process margin.
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| KR100407296B1 (en) * | 2000-12-18 | 2003-11-28 | 주식회사 하이닉스반도체 | Method for chemical mechanical polishing of titanium-aluminium-nitride |
| KR100431815B1 (en) * | 2002-07-18 | 2004-05-17 | 주식회사 하이닉스반도체 | Manufacturing method of semiconductor device |
| KR100681204B1 (en) * | 2000-12-30 | 2007-02-09 | 주식회사 하이닉스반도체 | Method for forming polysilicon plug using slurry having high selectivity |
| KR100895865B1 (en) * | 2006-05-18 | 2009-05-06 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Process for Improving Copper Line Cap Formation |
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| JP4524543B2 (en) * | 2003-03-25 | 2010-08-18 | 三洋電機株式会社 | Non-aqueous electrolyte for secondary battery and non-aqueous electrolyte secondary battery |
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| US5612254A (en) * | 1992-06-29 | 1997-03-18 | Intel Corporation | Methods of forming an interconnect on a semiconductor substrate |
| KR100230353B1 (en) * | 1992-11-05 | 1999-11-15 | 윤종용 | Method of forming a contact hole in a semiconductor device |
| KR970007835B1 (en) * | 1993-12-29 | 1997-05-17 | 금성일렉트론 주식회사 | Metalizing method of semiconductor device |
| KR980005378A (en) * | 1996-06-28 | 1998-03-30 | 김광호 | Method for manufacturing a semiconductor device having an Sanyo structure |
| KR100513802B1 (en) * | 1998-10-13 | 2005-12-05 | 주식회사 하이닉스반도체 | Contact formation method of semiconductor device |
| KR20000025634A (en) * | 1998-10-13 | 2000-05-06 | 김영환 | Method for manufacturing semiconductor device for forming contact plug |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100407296B1 (en) * | 2000-12-18 | 2003-11-28 | 주식회사 하이닉스반도체 | Method for chemical mechanical polishing of titanium-aluminium-nitride |
| KR100681204B1 (en) * | 2000-12-30 | 2007-02-09 | 주식회사 하이닉스반도체 | Method for forming polysilicon plug using slurry having high selectivity |
| KR100431815B1 (en) * | 2002-07-18 | 2004-05-17 | 주식회사 하이닉스반도체 | Manufacturing method of semiconductor device |
| KR100895865B1 (en) * | 2006-05-18 | 2009-05-06 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Process for Improving Copper Line Cap Formation |
| US8193087B2 (en) | 2006-05-18 | 2012-06-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process for improving copper line cap formation |
| US8623760B2 (en) | 2006-05-18 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process for improving copper line cap formation |
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