KR980005378A - Method for manufacturing a semiconductor device having an Sanyo structure - Google Patents

Abstract

1. Field of the Invention:

To a method of manufacturing a semiconductor device having an SIO structure.

2. Technical Problems to be Solved by the Invention:

And a method of manufacturing a semiconductor device for ensuring a margin at the time of DC and BC contact etching without adding a photo process.

3. The point of the inventive solution:

A plurality of field oxide films for use as a stopper in the planarization process are formed on the sub silicon of the wafer, a first insulating film is formed on the field oxide film and the active region, and the first openings for the active contacts and the plate conductive film A first step of simultaneously forming a second opening for the contact and a third opening for the storage contact and sequentially stacking the opening and the storage polysilicon and the second insulating film on the first insulating film to form a plurality of openings; Forming a handle wafer by forming planar polysilicon on the plurality of openings, the second opening and the second insulating film, forming a bonding insulating film and a bonding insulating film for a handle wafer in order to planarize the wafer, planarizing the wafer, and; A third step of reversing the result and planarizing the wafer sub-silicon until the second insulating film on the filled-up polysilicon on the second opening is removed and forming an active region, a non-active region, an information transfer transistor, and; Forming a third insulating film on the resultant to flatten and forming a line for outputting the information.

4. Important Uses of the Invention:

And is suitable for a manufacturing method of a semiconductor device.

Description

Method for manufacturing a semiconductor device having an Sanyo structure

Since this is a trivial issue, I did not include the contents of the text.

FIG. 1 is a view showing a method of manufacturing a semiconductor device having a Sanyo structure according to an embodiment of the related art.

Claims (3)

A method for manufacturing a semiconductor device, comprising: forming a plurality of field oxide films on a sub-silicon wafer for use as a stopper in a planarization process, forming a first insulating film on the field oxide film and the active region, A first opening for contact between the first opening and the plate conductive film and a third opening for the storage contact are formed at the same time and the storage polysilicon and the second insulating film are sequentially stacked on the opening and the first insulating film, Forming a planar polysilicon layer on the plurality of openings, the second opening and the second insulating layer, forming a bonding insulating layer and a bonding insulating layer for a handle wafer in order to planarize the wafer, A second process of forming a wafer after the wafer is inverted; A third step of planarizing the second insulating film on the filled-up plate polysilicon layer of the second opening to form an active region, an inactive region, an information transmitting transistor, and a resistance poly pattern; and forming a third insulating film on the resultant And a fourth step of forming a line for flattening and outputting the information. The method of claim 1, wherein the second insulating layer formed on the second opening serves as an alignment key. The method of claim 1, wherein the openings are formed at the same time. ※ Note: It is disclosed by the contents of the first application.