KR20000044630A - Forming method of polysilicon plug for semiconductor device - Google Patents
Forming method of polysilicon plug for semiconductor device Download PDFInfo
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- KR20000044630A KR20000044630A KR1019980061129A KR19980061129A KR20000044630A KR 20000044630 A KR20000044630 A KR 20000044630A KR 1019980061129 A KR1019980061129 A KR 1019980061129A KR 19980061129 A KR19980061129 A KR 19980061129A KR 20000044630 A KR20000044630 A KR 20000044630A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
Description
본 발명은 반도체 기술에 관한 것으로, 특히 반도체 소자의 콘택 공정 중 폴리실리콘 플러그 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a method for forming a polysilicon plug during a contact process of a semiconductor device.
반도체 소자 제조시 가장 보편화된 콘택 공정은 비교적 층덮힘 특성이 우수한 알루미늄을 단독으로 사용하여 진행하는 것이었다. 그러나, 반도체 소자가 고집적화되어 감에 따라 콘택홀이 점점 더 미세화되고 있으며, 이에 따라 알루미늄막을 신뢰성 있게 매립하는데 한계가 있었다.The most common contact process in the manufacture of semiconductor devices was to use aluminum alone, which has relatively good layer covering properties. However, as semiconductor devices have been highly integrated, contact holes have become more and more fine, and thus there is a limit to reliably filling aluminum films.
이러한 콘택 공정 상의 문제점을 고려하여 콘택홀이 형성된 웨이퍼 상에 폴리실리콘막을 증착하고, 이를 화학·기계적 연마(CMP) 공정을 통해 평탄화하여 폴리실리콘 플러그를 형성하는 방법을 사용하여 왔다.In consideration of such a problem in the contact process, a polysilicon film is deposited on the wafer on which the contact hole is formed and planarized through a chemical mechanical polishing (CMP) process to form a polysilicon plug.
첨부된 도면 도 1a 및 도 1b는 종래기술에 따른 폴리실리콘 플러그 형성 공정을 도시한 것으로, 종래기술은 우선, 도 1a에 도시된 바와 같이 워드라인(11)이 형성된 실리콘 기판(10) 상에 평탄화된 층간절연막(12)을 형성하고, 사진 및 식각 공정을 통해 콘택홀을 패터닝한 다음, 전체구조 상에 폴리실리콘막(13)을 증착한다.1A and 1B illustrate a polysilicon plug forming process according to the prior art, which prior art first planarizes on a silicon substrate 10 on which a wordline 11 is formed, as shown in FIG. 1A. The interlayer insulating film 12 is formed, the contact holes are patterned through photolithography and etching, and then the polysilicon film 13 is deposited on the entire structure.
다음으로, 도 1b에 도시된 바와 같이 폴리실리콘 연마용 슬러리를 사용하여 층간절연막(12) 상에 폴리실리콘막(13)이 남지 않을 때까지 폴리실리콘막(13)의 CMP를 실시한다.Next, CMP of the polysilicon film 13 is performed using a polysilicon polishing slurry as shown in FIG. 1B until no polysilicon film 13 remains on the interlayer insulating film 12.
이때, 연마 대상막인 폴리실리콘막(13)과 층간 절연막(산화막) 간의 연마 선택비가 50:1 정도로 매우 높기 때문에 CMP 공정시 연마 불균일도가 증가하고, 이에 따라 토폴로지(topology)가 낮은 층간절연막(12) 상에 폴리실리콘 파티클(particle)(14)이 잔류하게 된다. 이러한 파티클(14)이 계속하여 잔류하게 되면 후속 열공정에 의해 실리콘(Si) 입자들이 층간절연막(12) 내부로 확산되면서 콘택의 누설전류를 증가시키는 문제점이 있었다.At this time, since the polishing selectivity between the polysilicon film 13, which is a film to be polished, and the interlayer insulating film (oxide film) is very high, such as 50: 1, the polishing nonuniformity increases during the CMP process, and thus, the interlayer insulating film having a low topology is thus obtained. Polysilicon particles 14 remain on 12). If the particles 14 remain continuously, silicon (Si) particles diffuse into the interlayer insulating layer 12 by a subsequent thermal process, thereby increasing the leakage current of the contact.
또한, 주변회로 영역(도시되지 않음)에 잔류하는 폴리실리콘막(13)을 완전히 제거하기 위하여 추가적으로 실시되는 연마에 의해 콘택의 밀도가 큰 셀 지역에서 과도한 침식(erosion) 현상(15)이 발생하여 후속 마스크 공정을 어렵게 하며, 콘택 지역의 폴리실리콘막(13)이 과도하게 연마되는 디싱(dishing) 현상(16)이 발생하게 되는 문제점이 있었다.In addition, an excessive erosion phenomenon 15 may occur in a cell region with a high density of contacts due to additional polishing to completely remove the polysilicon film 13 remaining in the peripheral circuit region (not shown). There is a problem in that a subsequent mask process is difficult and a dishing phenomenon 16 occurs in which the polysilicon film 13 in the contact region is excessively polished.
첨부된 도면 도 2a 및 도 2b는 각각 폴리실리콘용 슬러리를 사용한 CMP 공정후의 파티클 측정맵 및 주사전자현미경(SEM) 사진을 도시한 것으로, 도 2a 및 도 2b에서 중앙의 어두운 부분은 파티클을 나타낸 것이며, 그 주위의 점들이 콘택 부분을 나타내고 있다.2A and 2B illustrate particle measurement maps and scanning electron microscopy (SEM) photographs after a CMP process using polysilicon slurries, respectively, in FIG. 2A and FIG. The dots around it represent the contact portion.
이러한 폴리실리콘 파티클 문제를 해결하고자 종래에는 화학제를 기상 또는 액상 상태로 웨이퍼 표면에 노출시켜 파티클을 제거하는 방법을 사용하였다. 그러나, 이 방법은 파티클만을 선택적으로 제거하기가 힘들어 층간산화막의 손실이 크고, 폴리실리콘 파티클의 제거 효과 또한 우수하지 못한 문제점이 있었다.In order to solve the polysilicon particle problem, a method of removing particles by exposing a chemical to a wafer surface in a gaseous or liquid state has been conventionally used. However, this method has a problem that it is difficult to selectively remove only particles, so that the loss of the interlayer oxide film is large, and the removal effect of the polysilicon particles is also not excellent.
본 발명은 폴리실리콘 플러그 형성을 위한 CMP 공정시 발생하는 폴리실리콘 파티클을 제거하고, 동시에 셀 영역에서의 침식 현상과 콘택의 디싱이 작은 반도체 소자의 폴리실리콘 플러그 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to remove polysilicon particles generated during a CMP process for forming a polysilicon plug, and at the same time, to provide a method for forming a polysilicon plug of a semiconductor device having a low erosion phenomenon and dishing of contacts.
도 1a 및 도 1b는 종래기술에 따른 폴리실리콘 플러그 형성 공정도.Figures 1a and 1b is a process diagram for forming a polysilicon plug according to the prior art.
도 2a 및 도 2b는 각각 폴리실리콘용 슬러리를 사용한 CMP 공정후의 파티클 측정맵 및 주사전자현미경(SEM) 사진도.2A and 2B are particle measurement maps and scanning electron microscope (SEM) photographs after the CMP process using polysilicon slurries, respectively.
도 3a 및 도 3b는 본 발명의 일 실시예에 따른 폴리실리콘 플러그 형성 공정도.3A and 3B are process diagrams for forming a polysilicon plug according to an embodiment of the present invention.
도 4a 및 도 4b는 각각 본 발명의 일 실시예에 따라 산화막용 슬러리를 사용한 CMP까지 진행한 후의 파티클 측정맵 및 그 SEM 사진도.4A and 4B are particle measurement maps and SEM photographs thereof after advancing to CMP using the slurry for oxide films according to one embodiment of the present invention, respectively.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
20 : 실리콘 기판20: silicon substrate
21 : 워드라인21: Word line
22 : 층간절연 산화막22: interlayer insulating oxide film
23 : 폴리실리콘막23: polysilicon film
24 : 파티클24: Particles
25 : 침식 현상25: erosion phenomenon
26 : 디싱 현상26 dishing phenomenon
본 발명은 기존과 동일하게 폴리실리콘 연마용 슬러리로 CMP를 실시한 다음, 폴리실리콘과 산화막(층간절연막) 간의 연마 선택비가 낮은 산화막용 슬러리를 사용하여 추가로 2차 CMP를 실시함으로써 폴리실리콘 파티클을 제거하고 셀 영역의 층간절연막 침식 현상 및 콘택의 디싱을 최소화하는 기술이다.According to the present invention, polysilicon particles are removed by performing CMP with a polysilicon polishing slurry and further performing secondary CMP using an oxide slurry having a low polishing selectivity between polysilicon and an oxide film (interlayer insulating film). In addition, this technique is to minimize the erosion of the interlayer dielectric layer in the cell region and dishing of the contact.
상기의 기술적 과제를 달성하기 위하여 본 발명으로부터 제공되는 반도체 소자의 폴리실리콘 플러그 형성방법은, 소정의 하부층이 형성된 반도체 기판 상에 층간절연 산화막을 형성하는 제1 단계; 상기 층간절연 산화막을 선택 식각하여 콘택홀을 형성하는 제2 단계; 상기 제2 단계 수행 후, 전체구조 상부에 폴리실리콘막을 형성하는 제3 단계; 폴리실리콘 연마용 슬러리를 사용하여 상기 층간절연 산화막이 노출될 정도로 상기 폴리실리콘막을 화학·기계적 연마하는 제4 단계; 및 산화막 연마용 슬러리를 사용하여 노출된 상기 층간절연 산화막의 일부 두께를 화학·기계적 연마함으로써 상기 제4 단계 수행 후 잔류하는 폴리실리콘 파티클을 제거하는 제5 단계를 포함하여 이루어진다.According to an aspect of the present invention, there is provided a method for forming a polysilicon plug of a semiconductor device, the method including: forming an interlayer insulating oxide film on a semiconductor substrate on which a predetermined lower layer is formed; Forming a contact hole by selectively etching the interlayer dielectric oxide film; A third step of forming a polysilicon film on the entire structure after performing the second step; Chemically and mechanically polishing the polysilicon film to the extent that the interlayer insulating oxide film is exposed using a polysilicon polishing slurry; And a fifth step of removing polysilicon particles remaining after performing the fourth step by chemically and mechanically polishing a part of the thickness of the interlayer insulating oxide film exposed using the oxide film polishing slurry.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 3a 및 도 3b는 본 발명의 일 실시예에 따른 폴리실리콘 플러그 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.3A and 3B illustrate a polysilicon plug forming process according to an embodiment of the present invention, which will be described with reference to the following.
본 실시예에 따른 폴리실리콘 플러그 형성 공정은, 우선 도 3a에 도시된 바와 같이 워드라인(21)이 형성된 실리콘 기판(20) 상에 평탄화된 층간절연 산화막(22)을 형성하고, 사진 및 식각 공정을 통해 콘택홀을 패터닝한 다음, 전체구조 상에 폴리실리콘막(23)을 증착한다. 층간절연 산화막(22)으로는 고밀도 플라즈마 화학기상증착(HDP-CVD) 산화막, O3-TEOS 산화막, USG(undoped silicate glass) 등이 사용될 수 있다. 이어서, 폴리실리콘 연마용 슬러리를 사용하여 층간절연 산화막(22)이 노출될 정도로 폴리실리콘막(23)의 CMP를 실시한다. 여기서, CMP 공정의 상세 조건은, 연마용 슬러리는 그 주성분이 SiO2, CeO2이고 층간절연 산화막(22)에 대한 폴리실리콘막(23)의 선택비가 30:1 이상이며, 연마 패드의 압력을 1.5∼9psi, 연마 패드의 회전 속도를 20∼80rpm으로 하며, 연마 시간을 50∼140초로 한다. 이때, 종래에 문제가 되었던 폴리실리콘 파티클(24), 층간절연 산화막(22)의 침식 현상(25) 및 콘택에서의 디싱 현상(26)이 나타난다.In the process of forming a polysilicon plug according to the present embodiment, first, as shown in FIG. 3A, a planarized interlayer insulating oxide film 22 is formed on a silicon substrate 20 on which a word line 21 is formed, and a photo and etching process is performed. After patterning the contact hole through, the polysilicon film 23 is deposited on the entire structure. As the interlayer insulating oxide film 22, a high density plasma chemical vapor deposition (HDP-CVD) oxide film, an O 3 -TEOS oxide film, an undoped silicate glass (USG), or the like may be used. Next, CMP of the polysilicon film 23 is performed using the polysilicon polishing slurry so that the interlayer dielectric oxide film 22 is exposed. Here, in the detailed conditions of the CMP process, the polishing slurry has a main component of SiO 2 , CeO 2, and a selectivity ratio of the polysilicon film 23 to the interlayer insulating oxide film 22 is 30: 1 or more, and the pressure of the polishing pad is increased. The rotating speed of 1.5 to 9 psi and the polishing pad is set to 20 to 80 rpm, and the polishing time is set to 50 to 140 seconds. At this time, the polysilicon particle 24, the erosion phenomenon 25 of the interlayer insulating oxide film 22, and the dishing phenomenon 26 at the contact, which have been a problem in the past, appear.
다음으로, 도 3b에 도시된 바와 같이 폴리실리콘막(23)과 층간절연 산화막(22)의 연마 선택비가 낮은 산화막 연마용 슬러리를 사용하여 추가적인 CMP 공정을 수행한다. 여기서, CMP 공정의 상세 조건은, 주성분이 SiO2, CeO2, A12O3이고 폴리실리콘막(23)에 대한 층간절연 산화막(22)의 연마 선택비가 5:1 이하인 슬러리를 사용하며, 연마 패드 압력을 5∼9psi, 연마 패드의 회전 속도를 20∼80rpm으로 하며, 연마 시간을 5∼20초로 한다.Next, as illustrated in FIG. 3B, an additional CMP process is performed using an oxide polishing slurry having a low polishing selectivity between the polysilicon film 23 and the interlayer insulating oxide film 22. Here, the detailed conditions of the CMP process are slurry using a slurry whose main components are SiO 2 , CeO 2 , A1 2 O 3, and the polishing selectivity of the interlayer insulating oxide film 22 to the polysilicon film 23 is 5: 1 or less. The pad pressure is 5 to 9 psi, the rotation speed of the polishing pad is 20 to 80 rpm, and the polishing time is 5 to 20 seconds.
이상과 같은 공정을 실시하면, 층간절연 산화막(22)이 연마되면서 그 표면의 폴리실리콘 파티클(24)이 제거되며, 연마 균일도가 향상되어 층간절연 산화막(22)의 침식 현상(25) 및 콘택에서의 디싱 현상(26)을 최소화할 수 있다.By performing the above process, the polysilicon particles 24 on the surface of the interlayer insulating oxide film 22 are removed while the interlayer insulating oxide film 22 is polished, and the polishing uniformity is improved, so that the erosion phenomenon 25 and the contact of the interlayer insulating oxide film 22 are improved. The dishing phenomenon 26 can be minimized.
첨부된 도면 도 4a 및 도 4b는 각각 본 발명의 일 실시예에 따라 산화막용 슬러리를 사용한 CMP까지 진행한 후의 파티클 측정맵 및 그 SEM 사진을 도시한 것으로, 상기 도 2a 및 도 2b와 비교할 때, 파티클이 거의 발견되지 않음을 확인할 수 있다.4A and 4B show particle measurement maps and SEM images thereof after advancing to CMP using the slurry for oxide films according to one embodiment of the present invention, respectively, when compared with FIGS. 2A and 2B, You can see that very few particles are found.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
본 발명은 CMP 공정을 통한 폴리실리콘 플러그 형성 공정시 폴리실리콘 파티클을 효과적으로 제거할 수 있으며, 층간절연막의 침식 및 콘택에서의 디싱 현상을 최소화하여 전·후속 공정의 마진을 확보할 수 있으며, 이로 인하여 반도체 소자의 수율 및 신뢰도를 향상시키는 효과가 있다.The present invention can effectively remove the polysilicon particles during the polysilicon plug forming process through the CMP process, minimize the erosion of the interlayer insulating film and dishing in the contact to secure the margin of the front and rear processes, thereby There is an effect of improving the yield and reliability of the semiconductor device.
Claims (6)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980061129A KR20000044630A (en) | 1998-12-30 | 1998-12-30 | Forming method of polysilicon plug for semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980061129A KR20000044630A (en) | 1998-12-30 | 1998-12-30 | Forming method of polysilicon plug for semiconductor device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030057181A (en) * | 2001-12-28 | 2003-07-04 | 동부전자 주식회사 | Method Removing Particles by CMP |
| KR100492897B1 (en) * | 2000-12-22 | 2005-06-02 | 주식회사 하이닉스반도체 | Method for fabricating polysilicon plug using polysilicon slurry |
| KR100618711B1 (en) * | 2005-08-18 | 2006-09-06 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
| KR100732309B1 (en) * | 2001-06-22 | 2007-06-25 | 주식회사 하이닉스반도체 | Manufacturing method for semiconductor device |
| KR100732308B1 (en) * | 2001-06-22 | 2007-06-25 | 주식회사 하이닉스반도체 | Method for chemical mechanical polishing of semiconductor device |
-
1998
- 1998-12-30 KR KR1019980061129A patent/KR20000044630A/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100492897B1 (en) * | 2000-12-22 | 2005-06-02 | 주식회사 하이닉스반도체 | Method for fabricating polysilicon plug using polysilicon slurry |
| KR100732309B1 (en) * | 2001-06-22 | 2007-06-25 | 주식회사 하이닉스반도체 | Manufacturing method for semiconductor device |
| KR100732308B1 (en) * | 2001-06-22 | 2007-06-25 | 주식회사 하이닉스반도체 | Method for chemical mechanical polishing of semiconductor device |
| KR20030057181A (en) * | 2001-12-28 | 2003-07-04 | 동부전자 주식회사 | Method Removing Particles by CMP |
| KR100618711B1 (en) * | 2005-08-18 | 2006-09-06 | 주식회사 하이닉스반도체 | Method of manufacturing semiconductor device |
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