KR20020048643A - Method for chemical mechanical polishing of semiconductor device - Google Patents
Method for chemical mechanical polishing of semiconductor device Download PDFInfo
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- KR20020048643A KR20020048643A KR1020000077855A KR20000077855A KR20020048643A KR 20020048643 A KR20020048643 A KR 20020048643A KR 1020000077855 A KR1020000077855 A KR 1020000077855A KR 20000077855 A KR20000077855 A KR 20000077855A KR 20020048643 A KR20020048643 A KR 20020048643A
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- chemical mechanical
- mechanical polishing
- plug
- polishing
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- 238000005498 polishing Methods 0.000 title claims abstract description 72
- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000000126 substance Substances 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 239000002002 slurry Substances 0.000 claims abstract description 39
- 239000010410 layer Substances 0.000 claims abstract description 38
- 239000011229 interlayer Substances 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 229920005591 polysilicon Polymers 0.000 claims abstract description 18
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000010703 silicon Substances 0.000 claims description 27
- 150000004767 nitrides Chemical class 0.000 claims description 16
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 229910020203 CeO Inorganic materials 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 239000000460 chlorine Substances 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims 1
- -1 Cl 2 Chemical compound 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 125000006850 spacer group Chemical group 0.000 abstract description 5
- 238000000151 deposition Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 26
- 239000012535 impurity Substances 0.000 description 7
- 239000000356 contaminant Substances 0.000 description 4
- 238000007517 polishing process Methods 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 239000003082 abrasive agent Substances 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000010979 pH adjustment Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 고연마선택비 슬러리를 이용한 반도체소자의 화학적기계적연마 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a chemical mechanical polishing method of a semiconductor device using a high polishing selectivity slurry.
최근에, 반도체 소자의 집적도가 증가하면서 다층 배선 공정이 실용화됨에 따라, 포토리소그래피(Photolithography) 공정의 마진을 확보하고 배선 길이를 최소화하기 위하여 평탄화(Planarization) 기술이 요구되고 있다. 현재, 하부 구조물을 평탄화시키기 위한 방법으로는 BPSG(Boro-Phospho-Silicate Glass; BPSG)의 리플로우(Reflow), 알루미늄(Al)의 플로우(Flow), SOG(Spin-On Glass; SOG)의 에치백 (Etch-back), 화학적기계적연마(Chemical Mechanical Polishing; CMP) 공정 등이 사용되고 있다.In recent years, as the integration degree of semiconductor devices has been increased, a planarization technique is required in order to secure a margin of a photolithography process and to minimize wiring length. Currently, methods for planarizing the lower structure include reflowing of Boro-Phospho-Silicate Glass (BPSG), flow of aluminum (Al), and spin-on glass (SOG). Etch-back and chemical mechanical polishing (CMP) processes are used.
이 중에서, 화학적기계적연마(CMP) 공정은 웨이퍼를 연마하기 위한 연마제인 슬러리(Slurry) 용액 내의 화학적 성분 및 웨이퍼를 연마하는 패드(Pad)와 연마제의 물리적 성분에 의하여 웨이퍼의 표면을 화학적기계적으로 연마하여 평탄화를 실시하는 방법으로서, 리플로우공정이나 에치백 공정으로 달성할 수 없는 넓은 공간 영역의 평탄화 및 저온 평탄화를 달성할 수 있다는 장점 때문에 차세대 반도체 소자에서 유력한 평탄화 기술로 대두되고 있다. 그러나, 슬러리 용액에는 H2O2, pH 조절을 위한 각종 산 또는 염기 등이 포함되어 있으며, 연마제의 주성분은 Al2O3, 실리카(Silica) 등이기 때문에 연마 과정에서 금속이온, 연마제 입자 등의 오염 물질이 흡착될 뿐 아니라 심각하게 손상을 입는 층이 발생되기도 한다. 이와 같이 중금속 오염 입자를 포함하는 오염 물질층과 손상 막질을 제거하기 위해서 CMP 공정 후 세정 공정을 필히 진행하고 있다.Among them, the chemical mechanical polishing (CMP) process chemically polishes the surface of the wafer by chemical components in a slurry solution, which is an abrasive for polishing the wafer, and a pad and a physical component of the abrasive. As a method of planarization, a planarization technique has emerged as a prominent planarization technique in next-generation semiconductor devices because of the advantages of achieving planarization and low-temperature planarization of a large space area which cannot be achieved by a reflow process or an etch back process. However, the slurry solution contains H 2 O 2 , various acids or bases for pH adjustment, and the main components of the abrasive are Al 2 O 3 , silica, and the like. In addition to the adsorption of contaminants, seriously damaging layers are created. As such, in order to remove the pollutant layer containing the heavy metal contaminant particles and the damaged film quality, the cleaning process is required after the CMP process.
이는 웨이퍼 표면에 오염물질 오염입자가 존재할 경우, 후속 공정시 패턴불량 또는 브릿지 등을 유발시켜 반도체 소자의 수율을 저하시키기 때문이다.This is because when contaminant contaminants are present on the wafer surface, pattern defects or bridges are caused in subsequent processes, thereby lowering the yield of semiconductor devices.
도 1a 내지 도 1b는 종래기술에 따른 반도체소자의 화학적기계적연마 방법을 도시한 공정 단면도이다.1A to 1B are cross-sectional views illustrating a method of chemical mechanical polishing of a semiconductor device according to the related art.
도 1a에 도시된 바와 같이, 반도체기판(11)상에 워드라인 또는 비트라인 등의 다수의 도전층패턴(12), 하드마스크(Hardmask)(13)의 적층구조로 이루어진 패턴을 형성한 후, 도전층패턴(12) 및 하드마스크(13)의 적층구조로 이루어진 패턴의 양측벽에 스페이서(14)를 형성한다. 여기서, 도전층패턴(12)은 텅스텐을 포함한다.As shown in FIG. 1A, after forming a pattern having a stacked structure of a plurality of conductive layer patterns 12, such as a word line or a bit line, and a hard mask 13 on a semiconductor substrate 11, The spacers 14 are formed on both sidewalls of the pattern having the laminated structure of the conductive layer pattern 12 and the hard mask 13. Here, the conductive layer pattern 12 includes tungsten.
계속해서, 도전층패턴(12) 사이의 반도체기판(11)에 불순물접합층(15)을 형성하는데, 불순물접합층(15)은 LDD(Lightly Doped Drain) 구조일 수 있다. 그리고, 하드마스크(13)는 질화막(Nitride) 또는 산화막(Oxide)일 수 있다.Subsequently, an impurity bonding layer 15 is formed on the semiconductor substrate 11 between the conductive layer patterns 12, and the impurity bonding layer 15 may have a lightly doped drain (LDD) structure. The hard mask 13 may be a nitride film or an oxide film.
도전층패턴(12)을 포함한 전면에 폴리실리콘을 증착하고, 자기정렬콘택(Self Aligned Contact; SAC)영역의 폴리실리콘만을 잔류시키기 위해 자기정렬콘택영역을 제외한 영역의 폴리실리콘을 식각하여 불순물접합층(15)에 접하는 폴리실리콘플러그(16)를 형성한다.In order to deposit polysilicon on the entire surface including the conductive layer pattern 12 and to leave only polysilicon in the self-aligned contact (SAC) region, the polysilicon in the region except the self-aligned contact region is etched to form an impurity bonding layer. A polysilicon plug 16 in contact with (15) is formed.
도 1b에 도시된 바와 같이, 전면에 층간절연막(17)을 증착한 후 하드마스크(13)를 연마정지막으로 하여 화학적기계적연마하여 인접한 폴리실리콘플러그(16)을 분리시킨다.As shown in FIG. 1B, after the interlayer insulating layer 17 is deposited on the entire surface, the adjacent polysilicon plug 16 is separated by chemical mechanical polishing using the hard mask 13 as a polishing stop film.
이 때, 층간절연막(17)은 산화막을 주로 이용하는데, 이러한 산화막과 폴리실리콘을 화학적기계적연마할 때, 도전층패턴(12) 상부에 사용되는 하드마스크(13)까지 연마하게 되는데, 장비구조상 발생하는 웨이퍼내 불균일도에 의해서 도전층패턴(12)으로 사용되는 텅스텐(W)이 드러나게 되는 가능성이 크다. 이럴 경우, 연마후 하드마스크(13)로 사용된 질화막 또는 산화막 두께의 과다한 손실(C)로 인해 후속 상부에 형성되는 비트라인콘택(Bitline contact)과의 브릿지(Bridge)를 유발하여 전기적 특성을 떨어뜨리며 수율의 저하를 야기시킬 수 있다.At this time, the interlayer insulating film 17 mainly uses an oxide film. When chemical mechanical polishing of the oxide film and polysilicon is carried out, the hard mask 13 used on the conductive layer pattern 12 is polished. The tungsten (W) used as the conductive layer pattern 12 is likely to be revealed due to the nonuniformity in the wafer. In this case, due to excessive loss (C) of the nitride film or oxide film used as the hard mask 13 after polishing, a bridge with a bitline contact formed on a subsequent upper part may cause deterioration of electrical characteristics. It can lower the yield.
또한, 화학적기계적연마(CMP) 장비의 특성상 연마후 웨이퍼 모서리 지역이 빨리 연마되는 특성이 있는데, 이 때 게이트 또는 비트라인에 사용된 텅스텐이 과도하게 노출될 수 있으며, 이로 인해 파티클 소스(Particle source)뿐만 아니라 이동하는 이온에 의한 금속불순물 오염의 문제가 있다.In addition, due to the characteristics of chemical mechanical polishing (CMP) equipment, the edge of the wafer is polished quickly after polishing, and the tungsten used in the gate or bit line may be excessively exposed, thereby causing a particle source. In addition, there is a problem of contamination of metal impurities by moving ions.
그리고, 연마시 웨이퍼내 완전한 분리를 위해서 어느 정도 과도연마를 하게 되는데, 이 때 폴리실리콘의 디싱(Dishing) 현상(A)이나 층간절연막 디싱 현상(B)에 의한 문제를 노출시켜 공정 마진이 줄어들며 반도체 수율 저하의 주요인으로 작용하는 문제점이 있다.And during polishing, it is over-polishing to some extent in order to completely separate in the wafer. At this time, the process margin is reduced by exposing the problems caused by dishing (A) or interlayer insulating film dishing (B) of polysilicon. There is a problem that acts as a major factor in yield reduction.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 고연마 선택비 슬러리를 사용하여 화학적기계적연마하므로써 웨이퍼내 전면 평탄화가 가능한 반도체소자의 화학적기계적연마 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object thereof is to provide a chemical mechanical polishing method of a semiconductor device capable of flattening the entire surface of a wafer by chemical mechanical polishing using a high polishing selectivity slurry.
도 1a 내지 도 1b는 종래기술에 따른 화학적기계적연마 방법을 도시한 도면,1a to 1b is a view showing a chemical mechanical polishing method according to the prior art,
도 2a 내지 도 2b는 본 발명의 실시예에 따른 화학적기계적연마 방법을 도시한 도면.2a to 2b are views showing a chemical mechanical polishing method according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 도전층패턴21 semiconductor substrate 22 conductive layer pattern
23 : 스페이서 24 : 스페이서23: spacer 24: spacer
25 : 불순물접합층 26 : 플러그용 실리콘25 impurity bonding layer 26 plug silicon
28 : 층간절연막28: interlayer insulating film
상기의 목적을 달성하기 위한 본 발명의 반도체소자의 화학적기계적연마 방법은 반도체기판상에 최상층에 마스크질화막을 포함하는 적층구조의 도전층패턴을 형성하는 단계, 상기 도전층패턴을 포함한 반도체기판상에 플러그용 도전막을 형성하는 단계, 상기 마스크질화막과 상기 플러그용 도전막간의 연마선택비가 우수한 슬러리를 이용하여 상기 플러그용 도전막을 화학적기계적연마하는 단계, 상기 연마된 플러그용 도전막을 선택적으로 제거하여 자기정렬콘택된 플러그를 형성하는 단계, 상기 플러그가 형성된 반도체기판상에 층간절연막을 형성하는 단계, 및 상기 마스크질화막이 드러날때까지 세리아계 슬러리를 이용하여 상기 층간절연막을 화학적기계적연마하는 단계를 포함하여 이루어짐을 특징으로 한다.In the chemical mechanical polishing method of the semiconductor device of the present invention for achieving the above object, forming a conductive layer pattern of a laminated structure including a mask nitride film on the uppermost layer on the semiconductor substrate, on the semiconductor substrate including the conductive layer pattern Forming a plug conductive film, chemically and mechanically polishing the plug conductive film using a slurry having an excellent polishing selectivity between the mask nitride film and the plug conductive film, and selectively removing the polished plug conductive film to self-align Forming a contacted plug, forming an interlayer insulating film on the semiconductor substrate on which the plug is formed, and chemically mechanically polishing the interlayer insulating film using a ceria-based slurry until the mask nitride film is exposed. It is characterized by.
바람직하게, 상기 플러그용 도전막을 화학적기계적연마하는 단계는, 상기 슬러리의 연마제로서 100㎚∼500㎚ 크기의 SiO2, Al2O3또는 CeO2중 어느 하나를 이용하되, 1psi∼10psi의 연마압력과 10rpm∼100rpm의 연마테이블 속도로 이루어지며, 상기 슬러리 연마제의 농도를 1wt%∼20wt%로 조절하고 pH를 2∼13으로 유지하여 이루어지는 것을 특징으로 한다.Preferably, the chemical mechanical polishing of the plug conductive film may be performed using any one of SiO 2 , Al 2 O 3, or CeO 2 having a size of 100 nm to 500 nm as an abrasive of the slurry, and a polishing pressure of 1 psi to 10 psi. And 10rpm to 100rpm polishing table speed, characterized in that the slurry is adjusted to 1wt% to 20wt% and the pH is maintained at 2 to 13.
바람직하게, 상기 세리아계 슬러리를 이용하여 화학적기계적연마하는 단계는, 상기 세리아계 슬러리의 연마제로서 100㎚∼500㎚ 크기의 CeO2를 이용하되, 1psi∼10psi의 연마압력과 10rpm∼100rpm의 연마테이블 속도로 이루어지며, 상기 슬러리 연마제의 농도를 1wt%∼20wt%로 조절하고 pH를 2∼13으로 유지하면서 이루어지는 것을 특징으로 한다.Preferably, the chemical mechanical polishing step using the ceria-based slurry, using CeO 2 having a size of 100 nm to 500 nm as the abrasive of the ceria-based slurry, a polishing pressure of 1psi to 10psi and a polishing table of 10rpm to 100rpm It is made at a rate, it is characterized in that the slurry is adjusted while the concentration of 1wt% to 20wt% and the pH is maintained at 2 to 13.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2c는 본 발명의 실시예에 따른 화학적기계적연마 방법을 도시한 도면으로서 폴리실리콘플러그를 형성하기 위한 자기정렬콘택식각 공정을 도시하고 있다.2A to 2C illustrate a chemical mechanical polishing method according to an embodiment of the present invention, which illustrates a self-aligned contact etching process for forming a polysilicon plug.
도 2a에 도시된 바와 같이, 반도체기판(21)상에 게이트 또는 비트라인 등의 다수의 도전층패턴(22)을 형성하고, 도전층패턴(22)상에 하드마스크(23)를 형성한다. 이 때, 도전층패턴(22)과 하드마스크(23)의 적층구조의 양측벽에 스페이서(24)를 형성하며, 적층구조 하부의 반도체기판(21)에는 트랜지스터의 소스/드레인으로 작용하는 불순물접합층(25)을 형성하되, 불순물접합층(25)은 LDD구조일 수 있다. 그리고, 도전층패턴(22)은 텅스텐(W)을 포함하고, 하드마스크(23)는 질화막 또는 산화막을 이용한다.As shown in FIG. 2A, a plurality of conductive layer patterns 22, such as a gate or a bit line, are formed on the semiconductor substrate 21, and a hard mask 23 is formed on the conductive layer pattern 22. In this case, spacers 24 are formed on both sidewalls of the stacked structure of the conductive layer pattern 22 and the hard mask 23, and the impurity junction acting as a source / drain of the transistor is formed on the semiconductor substrate 21 under the stacked structure. The layer 25 is formed, but the impurity bonding layer 25 may have an LDD structure. The conductive layer pattern 22 includes tungsten (W), and the hard mask 23 uses a nitride film or an oxide film.
한편, 하드마스크(23)로서 질화막(SixNy)을 이용할 경우, 질화막은 저압화학기상증착법(Low Pressure Chemical Vapor Deposition; LPCVD) 또는 플라즈마화학기상증착법(Plasma Enhanced CVD; PECVD) 중 어느 한 방법을 이용하여 400℃∼800℃에서 300Å∼3000Å의 두께로 증착된다.On the other hand, when using a nitride film (Si x N y ) as the hard mask 23, the nitride film is any one of Low Pressure Chemical Vapor Deposition (LPCVD) or Plasma Enhanced CVD (PECVD) It deposits in thickness of 300 kPa-3000 kPa at 400 degreeC-800 degreeC using this.
계속해서, 전면에 자기정렬콘택(SAC)으로 사용될 플러그용 실리콘(26)을 증착한 다. 이 때, 플러그용 실리콘(26)은 도핑실리콘, 비정질실리콘 또는 폴리실리콘 중 어느 하나이며, 400℃∼1200℃에서 500Å∼5000Å의 두께로 증착된다.Subsequently, a plugging silicon 26 to be used as a self-aligning contact (SAC) is deposited on the entire surface. At this time, the plug silicon 26 is any one of doped silicon, amorphous silicon or polysilicon, and is deposited at a thickness of 500 kPa to 5000 kPa at 400 to 1200 캜.
도 2b에 도시된 바와 같이, 실리콘 연마용 슬러리를 이용하여 도전층패턴(22) 상부에 과도 증착된 플러그용 실리콘(26)을 화학적기계적연마하여 평탄화하여 평탄화된 플러그용 폴리실리콘(27)을 형성한다. 이 때, 실리콘 연마용 슬러리의 경우, 연마시 플러그용 실리콘(26)과 하드마스크(23), 특히 질화막간의 연마속도 차이가 커서 연마후 플러그용 실리콘(26)을 완전 제거할 수 있는 반면 도전층패턴(22) 상부에 하드마스크(23)로 사용된 질화막의 경우는 연마가 일어나지 않아 연마 공정이 정지된다. 한편, 실리콘 연마용 슬러리는, 연마시 슬러리내에 포함된 연마제에 의한 기계적연마보다는 실리콘 연마용 슬러리 자체의 화학적성분에 의한 영향 때문에 플러그용 실리콘(26)과 하드마스크(23)간의 연마속도 차이가 발생하는 특성이 있다.As shown in FIG. 2B, a planarized plug polysilicon 27 is formed by chemical mechanical polishing of the plug silicon 26 overdeposited on the conductive layer pattern 22 using a silicon polishing slurry to planarize it. do. At this time, in the case of the silicon polishing slurry, the difference in the polishing rate between the plug silicon 26 and the hard mask 23, in particular, the nitride film during polishing is great so that the plug silicon 26 can be completely removed after polishing. In the case of the nitride film used as the hard mask 23 on the pattern 22, polishing does not occur and the polishing process is stopped. On the other hand, the silicon polishing slurry, due to the influence of the chemical composition of the silicon polishing slurry itself, rather than the mechanical polishing by the abrasive contained in the slurry during polishing, the polishing rate difference between the plug silicon 26 and the hard mask 23 occurs. There is a characteristic.
상술한 플러그용 실리콘(26)의 화학적기계적연마 공정은, 1psi∼10psi의 연마압력과 10rpm∼100rpm의 연마테이블 속도로 이루어지며, 실리콘 슬러리 연마제의 농도를 1wt%∼20wt%로 조절하고 슬러리의 pH를 2∼13으로 유지한다. 또한, 슬러리 연마제는 100㎚∼500㎚ 크기의 콜로이달(Colloidal) 형태 또는 퓸드(Fumed) 형태의 연마제, 예컨대 SiO2, Al2O3또는 CeO2중 어느 하나를 이용한다.The above-described chemical mechanical polishing process of the plug silicon 26 is carried out at a polishing pressure of 1 psi to 10 psi and a polishing table speed of 10 rpm to 100 rpm, and the concentration of the silicon slurry abrasive is adjusted to 1 wt% to 20 wt% and the pH of the slurry is adjusted. Is maintained at 2 to 13. In addition, the slurry abrasive may be any one of colloidal or fumed abrasives having a size of 100 nm to 500 nm, such as SiO 2 , Al 2 O 3, or CeO 2 .
도 2c에 도시된 바와 같이, 플러그용 실리콘(26)의 화학적기계적연마후 자기정렬콘택으로 사용되지 않은 지역의 플러그용 실리콘(27)을 제거하는데, 이 때 감광막을 이용한 마스크를 사용하여 플러그용 실리콘(27)을 제거한다. 여기서, 플러그용 실리콘(27)의 제거 공정은, 0.3㎛∼3㎛ 두께의 감광막을 도포하고 노광 및 현상으로 감광막을 패터닝하여 마스크를 형성한 후, 마스크를 이용하여 플러그용 폴리실리콘을 CF4, SF6등의 플루오린계 가스와 Cl2, CCl4등의 클로라인계 가스를 이용하여 식각한다.As shown in Fig. 2C, after the chemical mechanical polishing of the plug-in silicon 26, the plug-in silicon 27 in the unused region is removed. The plug-in silicon is used by using a mask using a photoresist film. Remove (27). Here, in the removal step of the plug silicon 27, a photosensitive film having a thickness of 0.3 μm to 3 μm is applied, the photosensitive film is patterned by exposure and development to form a mask, and then the plug polysilicon is replaced with CF 4 , using a mask. Etching is performed using fluorine-based gases such as SF 6 and chlorine-based gases such as Cl 2 and CCl 4 .
이러한 자기정렬콘택으로 사용되지 않은 플러그용 실리콘(27) 제거시, 플러그용 실리콘(27)과 하드마스크(23)로 이용된 질화막간의 식각 선택비에 의해서 플러그용 실리콘(27)은 완전 제거되지만, 하드마스크(23)인 질화막은 손실없이 잔류한다.When the plug silicon 27 not used as the self-aligned contact is removed, the plug silicon 27 is completely removed by the etching selectivity between the plug silicon 27 and the nitride film used as the hard mask 23. The nitride film, which is the hard mask 23, remains without loss.
도 2d에 도시된 바와 같이, 자기정렬콘택(SAC)으로 사용되지 않은 지역의 플러그용 실리콘(26)을 제거한 다음, 갭필(Gapfill) 특성이 우수한 산화막 즉, 층간절연막(28)을 3000Å∼10000Å의 두께로 증착하여 플러그용 실리콘(27)이 제거된 부분을 충분히 매립시킨다.As shown in FIG. 2D, the plug silicon 26 in the region not used as the self-aligned contact (SAC) is removed, and then an oxide film having excellent gapfill characteristics, that is, an interlayer insulating film 28, is removed. The thickness is deposited to sufficiently fill the portion where the plug silicon 27 is removed.
계속해서, 층간절연막(28)을 증착한 후, 웨이퍼상에 발생된 국부적인 단차를 제거하고 완전 평탄화를 구현하기 위해서 과도 증착된 층간절연막(28)을 세리아계 슬러리, 즉 CeO2를 사용하여 도전층패턴(22) 상부의 하드마스크(23)이 드러날때까지 화학적기계적연마하여 평탄화된 층간절연막(28a)을 형성한다.Subsequently, after the interlayer insulating film 28 is deposited, the overdeposited interlayer insulating film 28 is electrically conductive using a ceria-based slurry, that is, CeO 2 , in order to remove a local step generated on the wafer and to realize a perfect planarization. Chemical mechanical polishing is performed until the hard mask 23 on the layer pattern 22 is exposed to form a planarized interlayer insulating film 28a.
이러한, 세리아계 슬러리를 이용한 화학적기계적연마 공정은, 1psi∼10psi의 연마압력과 10rpm∼100rpm의 연마테이블 속도로 이루어지며, 실리콘 슬러리 연마제의 농도를 1wt%∼20wt%로 조절하고 슬러리의 pH를 2∼13으로 유지한다. 또한, 슬러리 연마제는 100㎚∼500㎚ 크기의 콜로이달(Colloidal) 형태 또는 퓸드(Fumed) 형태의 연마제, 예컨대 CeO2를 이용한다.The chemical mechanical polishing process using the ceria-based slurry is composed of a polishing pressure of 1 psi to 10 psi and a polishing table speed of 10 rpm to 100 rpm, and adjusts the concentration of the silicon slurry abrasive to 1 wt% to 20 wt% and the pH of the slurry is 2. Keep at -13. In addition, the slurry abrasive uses a colloidal or fumed abrasive such as CeO 2 having a size of 100 nm to 500 nm.
상술한 세리아계 슬러리는 슬러리 자체에 포함된 첨가제(Additive)에 의해서 층간절연막(28)과 하드마스크(23) 또는 층간절연막(28)과 플러그용 실리콘(27)간의 연마선택비가 존재하여 도전층패턴(22) 상부까지 과도 연마를 해도 자기정렬콘택지역의 플러그용 실리콘(27)의 디싱이 일어나지 않으며, 또한 도전층패턴(22) 상부에 형성된 하드마스크(23)의 손실도 발생되지 않는다. 또한 세리아계 슬러리는, 연마제의 크기가 통상의 실리카계 슬러리보다 2∼3배 정도 커서 연마시 층간절연막(28)의 디싱 현상을 방지한다.The ceria-based slurry has a polishing selectivity between the interlayer insulating film 28 and the hard mask 23 or the interlayer insulating film 28 and the plug silicon 27 due to additives contained in the slurry itself. (22) Even when excessively polished to the upper part, dishing of the plug-in silicon 27 in the self-aligned contact region does not occur, and no loss of the hard mask 23 formed on the conductive layer pattern 22 occurs. In addition, the ceria-based slurry is about 2 to 3 times larger in size than the conventional silica slurry to prevent dishing of the interlayer insulating film 28 during polishing.
이와 같이, 세리아계 슬러리를 사용하여 층간절연막(28)을 화학적기계적연마하여 평탄화하는 경우, 평탄도가 우수하며, 도전층패턴(22) 상부의 하드마스크(23)와 자기정렬콘택지역의 폴리실리콘(27)에 의해서 연마공정이 정지되므로 공정마진이 극대화되어 웨이퍼내 균일도를 향상시킬 수 있다.As such, when the interlayer insulating layer 28 is planarized by chemical mechanical polishing using a ceria-based slurry, the flatness is excellent, and the hard mask 23 on the conductive layer pattern 22 and the polysilicon of the self-aligned contact region are excellent. By 27, the polishing process is stopped, so that the process margin is maximized to improve the uniformity in the wafer.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 반도체소자의 화학적기계적연마 방법은 고연마선택비 슬러리를 이용하므로써 공정마진이 극대화되며, 연마후 평탄도가 우수하고연마균일도를 향상시켜 반도체소자의 수율을 증대시킬 수 있는 효과가 있다.In the chemical mechanical polishing method of the semiconductor device of the present invention as described above, the process margin is maximized by using a high polishing selectivity slurry, and after polishing, the flatness is excellent and the polishing uniformity can be improved to increase the yield of the semiconductor device. It works.
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100881837B1 (en) * | 2002-12-30 | 2009-02-03 | 주식회사 하이닉스반도체 | Method for forming storage node contact in semiconductor |
CN111599677A (en) * | 2019-02-21 | 2020-08-28 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
CN111599677B (en) * | 2019-02-21 | 2023-08-01 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
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