KR20010061560A - A method for forming isolation layer utilizing Selective Epitaxial Growth technology - Google Patents
A method for forming isolation layer utilizing Selective Epitaxial Growth technology Download PDFInfo
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- KR20010061560A KR20010061560A KR1019990064056A KR19990064056A KR20010061560A KR 20010061560 A KR20010061560 A KR 20010061560A KR 1019990064056 A KR1019990064056 A KR 1019990064056A KR 19990064056 A KR19990064056 A KR 19990064056A KR 20010061560 A KR20010061560 A KR 20010061560A
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 238000002955 isolation Methods 0.000 title claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 28
- 239000010703 silicon Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 150000004767 nitrides Chemical class 0.000 claims abstract description 11
- 125000006850 spacer group Chemical group 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 9
- 238000000059 patterning Methods 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract 1
- 238000004140 cleaning Methods 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 208000012868 Overgrowth Diseases 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76262—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using selective deposition of single crystal silicon, i.e. SEG techniques
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
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Abstract
Description
본 발명은 반도체 기술분야에 관한 것으로, 특히 반도체 제조 공정 중 소자간의 전기적 격리를 위한 소자 분리 공정에 관한 것이며, 더 자세히는 선택적 에피택셜 성장(Selective Epitaxial Growth, SEG) 기술을 이용한 소자 분리막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor technology, and more particularly, to a device isolation process for electrical isolation between devices in a semiconductor manufacturing process, and more particularly, to a method of forming a device isolation layer using selective epitaxial growth (SEG) technology. It is about.
트렌치 소자 분리 공정은 통상적인 LOCOS(LOCal Oxidation of Silicon) 공정에서 유발되는 버즈 비크(Bird's Beak) 문제와, STI(Shallow Trench Isolation) 공정에서 유발되는 작은 공간에서의 갭-필링(gap-filling) 문제를 해결할 수 있어 향후 1G DRAM 또는 4G DRAM급 이상의 초고집적 반도체 장치 제조 공정에의 적용이 유망한 기술이다. 그러나, 이러한 트렌치 소자 분리 공정은 절연물의 매립 특성을 확보하기 어려운 단점이 있다.The trench isolation process is the problem of Bird's Beak in the LOCOS process and gap-filling in the small space caused by the Shallow Trench Isolation process. This technology is expected to be applied to the manufacturing process of ultra-high density semiconductor devices of 1G DRAM or 4G DRAM level in the future. However, such a trench isolation process has a disadvantage in that it is difficult to secure the buried property of the insulator.
최근, 이러한 종래의 트렌치 소자분리 공정시의 문제를 해결하기 위하여 SEG 기술을 적용한 기술이 제시되고 있다.Recently, in order to solve such a problem in the conventional trench device isolation process, a technique using SEG technology has been proposed.
첨부된 도면 도1a 내지 도1e는 종래기술에 따른 SEG 기술을 이용한 소자 분리막 형성 공정을 도시한 것으로, 이하 이를 참조하여 그 공정을 설명한다.1A to 1E illustrate a process of forming an isolation layer using SEG technology according to the related art, and the process will be described below with reference to the drawing.
우선, 도 1a에 도시된 바와 같이 실리콘 기판(10)에 소자 분리 영역 형성을 위한 산화막(11)을 전면 증착한다.First, as shown in FIG. 1A, an oxide film 11 for forming an isolation region is deposited on the silicon substrate 10.
다음으로, 도1b에 도시된 바와 같이 산화막(11) 상부에 감광막 패턴(12)을 형성한다. 이때, 감광막 패턴(12)은 소자 분이 영역에 오버랩 되도록 형성한다.Next, as shown in FIG. 1B, a photosensitive film pattern 12 is formed on the oxide film 11. At this time, the photosensitive film pattern 12 is formed so that the elements overlap the region.
계속하여, 도1c에 도시된 바와 같이 감광막 패턴(12)을 식각 마스크로 하여 실리콘 기판(10)이 노출되도록 산화막(11)을 선택식각한 후 감광막 패턴(12)을 제거한다.Subsequently, as illustrated in FIG. 1C, the oxide film 11 is selectively etched to expose the silicon substrate 10 using the photoresist pattern 12 as an etch mask, and then the photoresist pattern 12 is removed.
다음으로, 도1d에 도시된 바와 같이 노출된 실리콘 기판(10) 상에 SEG 실리콘층(13)을 성장시킨다.Next, the SEG silicon layer 13 is grown on the exposed silicon substrate 10 as shown in FIG. 1D.
마지막으로, 도1e에 도시된 바와 같이 HF 또는 BOE용액을 사용한 통상의 게이트 산화막 성장 전 세정공정(Pre-cleaning)을 실시한다. 이때, 산화막(11)이 어느정도 손실되는데, 전 단계의 SEG 실리콘층(13) 성장 시 홀 내부를 완전히 매립하기 위해서는 도면과 같이 산화막(11) 위까지 과성장될 수 밖에 없고, 이 때문에 과성장된 SEG 실리콘층(13) 하부에 언더컷(undercut) 영역(A)이 형성된다.(확대도 참조)Finally, as shown in FIG. 1E, a conventional pre-cleaning process is performed before growth of a gate oxide film using HF or BOE solution. At this time, the oxide film 11 is lost to some extent, in order to completely fill the inside of the hole when the SEG silicon layer 13 is grown in the previous step, the oxide film 11 has to be overgrown to the oxide film 11 as shown in the drawing. An undercut region A is formed under the SEG silicon layer 13 (see enlarged view).
이러한 SEG 실리콘층(13)의 언더컷 영역(A)에서는 그 열악한 프로파일에 의해 후속 게이트 산화막 성장 시 씨닝(thinning)현상이 유발되며, 후속 게이트 패터닝 시 게이트 전극 물질이 완전히 제거되지 않고 레지듀(residue)로 잔류하게 되어 소자의 신뢰도를 저하시키는 문제점이 있다.In the undercut region A of the SEG silicon layer 13, the poor profile causes thinning during subsequent gate oxide film growth, and the gate electrode material is not completely removed during subsequent gate patterning. There remains a problem of remaining in the device to lower the reliability of the device.
본 발명은 SEG 실리콘의 과성장에 의해 유발되는 게이트 산화막 씨닝 현상 및 게이트 전극 물질의 레지듀 발생을 방지하는 선택적 에피택셜 실리콘 성장 기술을 이용한 소자 분리막 형성방법을 제공하는데 그 목적이 있다.It is an object of the present invention to provide a method of forming a device isolation layer using a selective epitaxial silicon growth technique that prevents gate oxide thinning phenomenon caused by overgrowth of SEG silicon and residue generation of a gate electrode material.
도1a 내지 도1e는 종래기술에 따른 SEG 기술을 이용한 소자 분리막 형성 공정을 도시한 도면.1A to 1E are views illustrating a device isolation film forming process using SEG technology according to the prior art.
도2a 내지 도2f는 본 발명의 일 실시예에 따른 SEG 기술을 이용한 소자 분리막 형성 공정을 도시한 도면.2A to 2F illustrate a process of forming an isolation layer using SEG technology according to an embodiment of the present invention.
*도면의 주요부분에 대한 부호의 간단한 설명* Brief description of symbols for the main parts of the drawings
20 : 실리콘 기판 21 : 산화막20 silicon substrate 21 oxide film
23a : 질화막 스페이서 24 : SEG 실리콘층23a: nitride film spacer 24: SEG silicon layer
상기 목적을 달성하기 위한 본 발명은, 반도체 장치의 소자 분리막 형성방법에 있어서, 실리콘 기판 상에 제1절연층을 형성하는 제1 단계; 상기 제1절연층을선택식각하는 제2 단계; 상기 제1절연층의 측벽에 상기 제1절연층과 식각선택비를 갖지는 제2절연층을 사용하여 스페이서를 형성하는 제3 단계; 및 상기 제3 단계 수행 후 노출된 상기 실리콘 기판 상에 선택적 에피택셜 실리콘층을 형성하여 상기 제1절연층 및 상기 스페이서에 의해 정의된 홀을 매립하는 제4 단계를 포함하여 이루어진다.According to an aspect of the present invention, there is provided a device isolation film forming method of a semiconductor device, comprising: a first step of forming a first insulating layer on a silicon substrate; A second step of selectively etching the first insulating layer; Forming a spacer on a sidewall of the first insulating layer by using a second insulating layer having an etch selectivity with the first insulating layer; And a fourth step of forming a selective epitaxial silicon layer on the exposed silicon substrate after performing the third step to fill a hole defined by the first insulating layer and the spacer.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
첨부된 도면 도2a 내지 도2f는 본 발명의 일 실시예에 따른 SEG 기술을 이용한 소자 분리막 형성 공정을 도시한 것으로, 이하 이를 참조하여 그 공정을 설명한다.2A to 2F illustrate a process of forming a device isolation layer using SEG technology according to an embodiment of the present invention, which will be described below with reference to the drawing.
우선, 도2a에 도시된 바와 같이 실리콘 기판(20) 상에 절연지역 형성을 위한 산화막(21)을 전면 증착한다.First, as illustrated in FIG. 2A, an oxide film 21 for forming an insulating region is deposited on the silicon substrate 20.
다음으로, 도2b에 도시된 바와 같이 산화막(21) 상부에 감광막 패턴(22)을 형성하여 패터닝한다. 이때, 감광막 패턴(22)은 소자 분리 영역에 오버랩 되도록 형성한다.Next, as shown in FIG. 2B, a photosensitive film pattern 22 is formed on the oxide film 21 and patterned. At this time, the photoresist pattern 22 is formed to overlap the device isolation region.
계속하여, 도2c에 도시된 바와 같이 감광막 패턴(22)을 식각 마스크로 하여 실리콘 기판(20)이 노출되도록 산화막(21)을 선택식각한 후 감광막 패턴(22)을 제거한다.Subsequently, as shown in FIG. 2C, the oxide film 21 is selectively etched to expose the silicon substrate 20 using the photoresist pattern 22 as an etch mask, and then the photoresist pattern 22 is removed.
이어서, 도2d에 도시된 바와 같이 전체구조 표면을 따라 질화막(23)을 증착하고, 도2e에 도시된 바와 같이 질화막(23)을 전면 식각하여 패터닝된 산화막(21) 측벽에 질화막 스페이서(23a)를 형성한다.Next, as shown in FIG. 2D, the nitride film 23 is deposited along the entire structure surface, and as shown in FIG. 2E, the nitride film 23 is etched by etching the entire surface of the nitride film 23. To form.
다음으로, 도2e에 도시된 바와 같이 노출된 실리콘 기판(20) 상에 SEG 실리콘층(24)을 성장시켜 산화막(21)에 의해 정의된 홀을 매립한다. 이때, 질화막 스페이서(23a)의 프로파일에 의해 SEG 실리콘층(24)의 과성장 현상이 없어지고, 종래와 같이 산화막(21) 상부를 덮는 영역이 나타나지 않기 때문에 후속 게이트 산화막 성장 전 세정공정을 실시하여 산화막(21)의 손실이 발생하더라도 언더컷에 의한 SEG 실리콘층(23)의 에지부분에서의 프로파일 열화가 발생하지 않게된다. 따라서, 게이트 산화막 씨닝 현상 및 게이트 전극 물질의 레지듀 발생을 방지할 수가 있다.Next, as shown in FIG. 2E, the SEG silicon layer 24 is grown on the exposed silicon substrate 20 to fill the holes defined by the oxide film 21. At this time, the overgrowth phenomenon of the SEG silicon layer 24 is eliminated by the profile of the nitride film spacer 23a, and the region covering the upper portion of the oxide film 21 does not appear as in the prior art. Even if a loss of the oxide film 21 occurs, profile degradation at the edge portion of the SEG silicon layer 23 due to undercut does not occur. Thus, it is possible to prevent the gate oxide film thinning phenomenon and the residue generation of the gate electrode material.
한편, 질화막 스페이서(23a)가 게이트 산화막 성장 전 세정공정 시 베리어 역할을 수행함으로써, 충분한 세정공정을 실시할 수 있게 된다.On the other hand, since the nitride film spacer 23a plays a barrier role in the cleaning process before the gate oxide film growth, a sufficient cleaning process can be performed.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
예컨대, 전술한 실시예에서는 질화막 스페이서를 사용하는 경우를 일례로 들어 설명하였으나, 본 발명은 산화막과 식각 선택비를 가지는 다른 절연막을 대신하여 사용하는 경우에도 적용될 수 있다.For example, in the above-described embodiment, the case of using the nitride film spacer has been described as an example. However, the present invention may be applied to the case of using an oxide film and another insulating film having an etching selectivity.
본 발명은 씨닝 및 레지듀 발생을 억제하는 효과가 있으며, 이로 인하여 반도체 장치의 동작 특성 및 신뢰도를 개선할 수 있는 효과가 있다.The present invention has the effect of suppressing thinning and residue generation, thereby improving the operating characteristics and reliability of the semiconductor device.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020002640A (en) * | 2000-06-30 | 2002-01-10 | 박종섭 | A method for a field oxide of semiconductor device |
| US7081390B2 (en) | 2002-12-27 | 2006-07-25 | Hynix Semiconductor Inc. | Semiconductor device and a method of manufacturing the same |
| KR100909806B1 (en) * | 2006-09-14 | 2009-07-28 | 주식회사 하이닉스반도체 | Device Separation Method of Semiconductor Devices |
-
1999
- 1999-12-28 KR KR1019990064056A patent/KR20010061560A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020002640A (en) * | 2000-06-30 | 2002-01-10 | 박종섭 | A method for a field oxide of semiconductor device |
| US7081390B2 (en) | 2002-12-27 | 2006-07-25 | Hynix Semiconductor Inc. | Semiconductor device and a method of manufacturing the same |
| KR100909806B1 (en) * | 2006-09-14 | 2009-07-28 | 주식회사 하이닉스반도체 | Device Separation Method of Semiconductor Devices |
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