KR20010061268A - A structure of liquid crystal display panel - Google Patents

Abstract

PURPOSE: A liquid crystal display(LCD) panel structure is to prevent an occurrence of flicker phenomenon by a potential difference of the common electrode and decrease an interconnection line for applying the common electrode voltage. CONSTITUTION: The first interconnection line(180) is formed on the first substrate and allows the first common electrode voltage to be applied to the first common electrode shorting point(161,162) near a gate pad(152). The second interconnection line(190) is formed on the first substrate and allows the second common electrode voltage greater than the first common electrode voltage to a plurality of second common electrode shorting point(163,164) distant from the gate pad. A common electrode is formed on the second substrate. The second interconnection line(190) includes the third interconnection line electrically connected to the second common electrode contact point and the fourth interconnection line connected to a data dummy pad and the first point on the third interconnection line.

Description

Liquid crystal display panel structure {A STRUCTURE OF LIQUID CRYSTAL DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (LCD), and more particularly, to a common electrode and a wiring formed in a thin film transistor liquid crystal display panel to which a common voltage of an equipotential is applied.

1 is an equivalent circuit for a unit pixel in a typical TFT-LCD. As shown in Fig. 1, the gate electrode g, the source electrode s, and the drain electrode d of the TFT 10 are connected to the gate line Gn, the data line Dm, and the pixel electrode P, respectively. The liquid crystal material is formed between the pixel electrode P and the common electrode Com, which is equivalently represented as the liquid crystal capacitor Clc. The storage capacitor Cst is formed between the pixel electrode and the front gate line Gn-1, and the parasitic capacitance Cgd is generated between the gate electrode and the drain electrode due to misalignment. The liquid crystal capacitor Ccl and the storage capacitor Cst act as loads that the TFT-LCD should drive.

The operation of the TFT-LCD will be described as follows.

First, the TFT 10 is conducted by applying a gate-on voltage to the gate electrode connected to the gate line Gn to be displayed, and then a data voltage representing an image signal is applied to the source electrode s to drain the data voltage. It is applied to the electrode (d). Then, the data voltage is applied to the liquid crystal capacitor Clc and the storage capacitor Cst through the pixel electrode P, respectively, and an electric field is formed by the voltage difference between the pixel electrode Cp and the common electrode Com. At this time, since the liquid crystal deteriorates when an electric field in the same direction is continuously applied to the liquid crystal material, the LCD panel drives the image signal to be repeated positively and negatively with respect to the common electrode in order to prevent deterioration of the liquid crystal. This is called an inversion driving method.

On the other hand, when the TFT is turned on, the voltage applied to the liquid crystal capacitor Clc and the storage capacitor Cst must continue to be maintained even after the TFT is turned off, but the parasitic capacitance Cgd between the gate electrode and the drain electrode is maintained. Due to this, the voltage applied to the pixel electrode causes distortion. The distorted voltage is called a kickback voltage, and the kickback voltage ΔV is obtained by the following equation.

Here, Vg denotes a change amount of the gate voltage, that is, a difference between the gate on voltage Von and the gate off voltage Voff.

This voltage distortion always acts in the direction of lowering the voltage of the pixel electrode regardless of the polarity of the data voltage, which is shown in FIG.

In Fig. 2, Vg, Vd, and Vp represent the gate voltage, the data voltage, and the voltage of the pixel electrode, respectively, and Vcom and ΔV represent the common electrode voltage (common voltage) and kickback voltage, respectively. As shown by the dotted line in Fig. 2, in the ideal TFT-LCD, when the gate voltage Vg is on, the data voltage Vd is applied to the pixel electrode, and the data voltage is maintained even when the gate voltage is turned off. In the LCD, as shown by the solid line of FIG. 2, in the portion where the gate voltage is changed, the pixel voltage Vp is lowered by the kickback voltage under the influence of the kickback voltage ΔV.

On the other hand, the effective value of the voltage applied to the liquid crystal is determined by the area between the pixel voltage Vp and the common voltage Vcom. When the liquid crystal display is driven in an inverted driving method, the area of the pixel voltage centered on the common voltage is used. It is necessary to adjust the common voltage level so as to be symmetrical. For this purpose, a constant common voltage in which the area of the pixel voltage is symmetric is applied to the common electrode.

When the area of the pixel voltage Vp centered on the common voltage Vcom is not symmetrical, the amount of pixel voltage charged in each pixel is different from frame to frame, and the screen flickers when the pixel voltage is reversed. This is because flicker occurs. However, even when a constant common voltage is applied to the common electrode in order to prevent the flicker phenomenon, the flicker phenomenon still occurs for the following reason.

On the other hand, in general, the gate line has a resistance component and a parasitic capacitance component, and as a result, there is a delay of the gate voltage by the time constant determined by the product of these two values. This signal delay becomes larger as the size of the liquid crystal panel increases.

Further, the farther the gate voltage is from the input terminal, that is, the larger the delay of the gate signal is, the smaller the change amount ΔVg of the gate voltage is. As a result, the kickback voltage ΔV becomes smaller.

Therefore, when the common voltage is constantly applied, since the voltage is not maintained as the center value of the pixel voltage, the flicker phenomenon occurs because the value of the voltage charged in the pixel on a frame basis is changed. This phenomenon becomes even more problematic as the screen of the liquid crystal display becomes larger and the gate lines become longer.

Accordingly, the present invention is to prevent the flicker phenomenon caused by the potential difference of the common voltage. In addition, the present invention is to reduce the resistance of the wiring for applying a common voltage.

1 is a diagram illustrating an equivalent circuit for a unit pixel of a general thin film transistor liquid crystal display.

2 is a diagram illustrating voltage distortion caused by a kickback voltage.

3 is a simplified structural diagram of a liquid crystal display panel according to a first embodiment of the present invention.

4 is a simplified structural diagram of a liquid crystal display panel according to a second exemplary embodiment of the present invention.

5 is a schematic structural diagram of a liquid crystal display panel according to a third exemplary embodiment of the present invention.

FIG. 6 is a detailed view of a portion A shown in FIGS. 3, 4, and 5;

According to an exemplary embodiment of the present invention, a liquid crystal display panel structure includes a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors connected to the gate lines and data lines, and a pixel electrode connected to the thin film transistors. And a first wiring for applying a first common voltage to a first common electrode contact point close to the gate pad, and a second common voltage greater than the first common voltage to a plurality of second common electrode contact points far from the gate pad. A first substrate on which second wirings are to be applied; And a second substrate having a common electrode facing the pixel electrode, wherein the second wiring is a third wiring electrically connecting the second common electrode contact point, and is connected to a data dummy pad and is formed on the third wiring. And a fourth wire electrically connected to a point A so that a predetermined voltage is formed at the plurality of second common electrode contact points, and a center portion of the third wire connected to the fourth wire is one side of the third wire. The resistance value from the end to the center of the third wiring and the resistance value from the other end of the third wiring to the center of the third wiring are preferably approximated.

In addition, the third wiring line has a thin and short line width of the upper portion centered on the center portion, a line width of the lower portion is thick and long, and the resistance value of the upper portion and the lower portion is the same.

Hereinafter, embodiments of the present invention will be described in detail so that those skilled in the art can easily implement the present invention.

3 is a simplified structural diagram of a liquid crystal display panel according to a first embodiment of the present invention. As shown in FIG. 3, the TFT-LCD panel according to the first embodiment of the present invention is composed of a first substrate 110 and a second substrate 120 facing the first substrate.

Here, typically, the first substrate 110 includes a thin film transistor and a pixel electrode, which is also called a thin film transistor substrate. In addition, the second substrate 120 includes a color filter and a common electrode, and is called an opposing substrate.

In the center of the two substrates 110 and 120, there is a display area 130 composed of a plurality of pixels for displaying an image signal, and a seal 131 for confining liquid crystal is formed. The seal 131 is formed to surround the display area 130 when viewed from above the second substrate 120.

An upper portion of the exposed first substrate 110 is connected to a plurality of data lines (not shown), and the data pads 140 transferring data voltages from the outside are clustered. In addition, the left side of the exposed first substrate is connected to a plurality of gate lines (not shown), and gate pads 150 for transferring the gate voltage from the outside are clustered. The data pad 140 and the gate pad 150 are formed with gate out lead bond (OLB) pads 142 and 152, respectively. Meanwhile, connection portions 141 and 151 connecting the gate lines and the data lines and the respective pads 140 and 150 are formed between the display area 130 and the pads 140 and 150, respectively.

In addition, two common electrode contact points 161 and 162 are formed at two corners near the gate pad 150 among four corners of the first substrate 110, and two far from the gate pad 150. Two common electrode contact points 163 and 164 are formed at the corners, and two common electrode contact points 165 and 166 are formed at predetermined points between the two contact points 163 and 164.

The contact points 161 to 166 receive the common voltages Vcom1 and Vcom2 from the outside through the dummy pads 171, 172 and 173 that are redundantly formed next to the pads 140 and 150.

At this time, the contact points 161 and 162 receive the common voltage Vcom1 directly from the dummy pads 171 and 172 without connecting the wires, and the contact points 163 to 166 are the first wire 180 and the second wire 190. The common voltage Vcom2 is applied through a specific pattern of wiring.

Hereinafter, the wiring structure of the contact points 163 to 166 and the data dummy pad 173 will be described.

The four contact points 163 to 166 are electrically connected by the first wiring 180, and the first wiring 180 uses thin film wiring.

One end of the second wire 190 is connected to the data dummy pad 173, and the other end thereof is connected to a point A which is an intermediate point of the first wire 190. Here, the point A is preferably a point at which the resistance value from the point A to each end of the first wire 180 is 40 ohm if the resistance value of the first wiring 180 is 80 ohm. However, the point A may be located exactly at the middle point of the first wiring 180 and may not be located at the center of the resistance value. However, the resistance value from the point A to each end of the wiring 180 may not have too much difference. do.

Here, the second wiring 190 is insulated and overlapped on the first wiring 180.

As described above, in the liquid crystal display panel structure according to the first embodiment of the present invention, the conventional technique of applying the common voltage Vcom2 through the contact point 163 located at the upper end of the first wiring has a contact point 163 by the wiring resistance. It is possible to prevent the potential difference between the voltage at) and the voltage at the contact point 164 to prevent flicker between the top and bottom of the panel.

Hereinafter, a structure of a liquid crystal display panel according to a second exemplary embodiment of the present invention will be described with reference to FIG. 4.

4 is a simplified structural diagram of a liquid crystal display panel according to a second exemplary embodiment of the present invention. FIG. 4 is a simplified view of FIG. 3, in which the gate pad 150, the data pad 140, and the connections 141 and 151 connected to the pads 140 and 150 are covered by the second substrate 120. It is a state.

In the second embodiment of the present invention, the formation pattern of the first wiring and the second wiring is different from that of the first embodiment, and the overall structure is the same. Therefore, below, only the connection pattern of a 1st wiring and a 2nd wiring is demonstrated.

First, the first wiring 180 electrically connects the contact points 163 to 166 as in the first embodiment, and the second wiring 190 is the A of the data dummy pad 171 and the first wiring 180. It is connected to the branch.

However, the first wiring 180 and the second wiring 190 are made of low-resistance metal having low resistance, and the second wiring 190 has a wire 131 up to a point connected to the point A. ) And the inside of the seal 131, and the width of the wiring so that the resistance is lower than in the first embodiment.

Accordingly, the second embodiment of the present invention enables the voltage drop of the common voltage Vcom2 to be small and maximizes the space between the display area 130 and the end of the second substrate 120.

Hereinafter, a structure of a liquid crystal display panel according to a third exemplary embodiment of the present invention will be described with reference to FIG. 5.

5 is a schematic structural diagram of a liquid crystal display panel according to a third exemplary embodiment of the present invention. In the third embodiment of the present invention with reference to Fig. 5, only the formation patterns of the first wiring and the second wiring are different from those of the first and second embodiments, and the overall structure is the same. Therefore, below, only the connection pattern of a 1st wiring and a 2nd wiring is demonstrated.

As shown in FIG. 5, the first wiring 180 electrically connects the contact points 163 to 166 as in the first and second embodiments, and is centered on a point connected to the second wiring (called an E point). The line width is different between the upper side and the lower side. In other words, the line width from the point E to the upper end does not touch the thread 131, while the line width from the point E to the lower end is thick enough to be located between the thread 131 and the display area 130.

Therefore, according to the law of resistance, the resistance value is thinner and the longer the length, the larger the value, the thicker and the longer the length, the smaller the value, the point E is the same as the first and second embodiments of the present invention of the first wiring 180 If it is located in the middle point, a resistance difference occurs between the upper and lower wirings.

Therefore, the point E is located at a point close to the upper end, more precisely, the point where the resistance value from the point E to the upper end is equal to the resistance value from the point E to the lower end.

As a result, the voltage drop at the contact point 163 and the contact point 164 is equal to the common voltage Vcom2 applied to the point E due to the same resistance value.

Here, as in the third embodiment of the present invention, when the line width of the lower portion of the first wiring 180 is made thick, absolute wiring resistance is reduced as shown in Tables 1 and 2.

Here, Table 1 refers to FIG. 6A and Table 2 refers to FIG. 6B.

6A and 6B, A and A 'are second wirings 190, B and B' are wirings from the point where they are connected to the second wiring 190 to the upper end, and C and C 'are the second wirings. It is the wiring from the point connected with the wiring 190 to the lower end.

Wiring Line width (mm) Length (mm) Resistance (Ω) Total resistance (Ω) A 0.3 40 80 120 B One 40 40 C One 40 40

Wiring Line width (mm) Length (mm) Resistance (Ω) Total resistance (Ω) A ' 0.5 30 60 90 B ' One 30 30 C ' 1.7 50 30

As shown in Table 1 and Table 2 above, the thicker the line width of the predetermined portion of the first wiring, the lower the total resistance of the wiring.

As mentioned above, although the Example of this invention was described, this invention is not limited to the said Example, Of course, many other changes and a deformation | transformation are possible.

As described above, according to the present invention, when different common voltages are applied to both ends of the gate line, flicker generation between the upper and lower panels due to the wiring resistance is prevented. In addition, the total resistance of the wiring is lowered to prevent the voltage drop of the common voltage.

Claims (4)

A plurality of gate lines, a plurality of data lines, a plurality of thin film transistors connected to the gate lines and the data lines, and a pixel electrode connected to the thin film transistors to form pixel electrodes, and a first common voltage at a first common electrode contact point close to the gate pad. A first substrate having a first wiring to be applied and a second wiring to allow a second common voltage greater than the first common voltage to be applied to a plurality of second common electrode contact points away from the gate pad; And A second substrate having a common electrode opposed to the pixel electrode; The second wiring may include a third wiring electrically connecting the second common electrode contact point, and a fourth wiring connected to a data dummy pad and electrically connected to a first point on the third wiring. 2. A liquid crystal display panel structure according to claim 2, wherein a predetermined voltage is formed at a common electrode contact point. In claim 1, And the fourth wiring is connected to be connected to the first point through a chamber formed in the second substrate and a liquid crystal display area. In claim 1, The first point of the third wiring is a point at which the resistance value from one end of the third wiring to the first point and the resistance value from the other end of the third wiring to the first point are approximated. Liquid crystal display panel structure. In claim 2, And a wiring width from one end of the third wiring to the first point is thinner than a wiring width from the other end of the third wiring to the first point.