JP3558934B2 - Active matrix type liquid crystal display - Google Patents

Active matrix type liquid crystal display Download PDF

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JP3558934B2
JP3558934B2 JP29296799A JP29296799A JP3558934B2 JP 3558934 B2 JP3558934 B2 JP 3558934B2 JP 29296799 A JP29296799 A JP 29296799A JP 29296799 A JP29296799 A JP 29296799A JP 3558934 B2 JP3558934 B2 JP 3558934B2
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display area
liquid crystal
pixel
voltage
electrode
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JP2001117072A (en
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陽 仲野
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Alps Alpine Co Ltd
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Alps Electric Co Ltd
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Priority to JP29296799A priority Critical patent/JP3558934B2/en
Priority to EP00306528A priority patent/EP1093009A3/en
Priority to KR10-2000-0059694A priority patent/KR100371757B1/en
Priority to CN00129680A priority patent/CN1129028C/en
Priority to US09/687,633 priority patent/US6529257B1/en
Publication of JP2001117072A publication Critical patent/JP2001117072A/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3666—Control of matrices with row and column drivers using an active matrix with the matrix divided into sections
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133391—Constructional arrangement for sub-divided displays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects

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  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
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  • Geometry (AREA)
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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、アクティブマトリクス型液晶表示装置に関する。より詳細には、互いに画素領域の大きさが異なる主表示エリアと副表示エリアを具備するアクティブマトリクス型液晶表示装置の対向電極構造に関する。
【０００２】
【従来の技術】
従来、アクティブマトリクス方式の液晶表示装置としては、図６に示すものが知られている。図６は薄膜トランジスタ（ Ｔｈｉｎ Ｆｉｌｍ Ｔｒａｎｓｉｓｔｏｒ： 以下、ＴＦＴと略記する）アレイ基板１４０の平面図である。
従来のアクティブマトリクス装置のＴＦＴアレイ基板１４０には、画素を構成する画素領城１３２がマトリクス状に配列された表示エリア１３０、この表示エリア１３０の走査線１０１から外付けのゲートドライバＩＣに接続するための走査線の引き出し配線１３４と走査線端子１３６、表示エリア１３０の信号線１１９から外付けのソースドライバＩＣに接続するための信号線の引き出し配線１３５と信号線端子１３７がそれぞれ形成されている。
【０００３】
従来のアクティブマトリクス型液晶表示装置に対して新たな機能を付加できるとの観点から、図１に示すように、表示エリア３０（以後、主表示エリアと言う）のほかに、例えば文字情報を表示させることを目的とした他の表示エリア３１（以後、副表示エリアと言う）を設ける必要性が唱えられている。
この場合、主表示エリア３０には精細度の高い表示が要求されるために画素領域３２を小さくするが、副表示エリア３１ではその表示目的から、必ずしも画素領域３３の大きさを主表示エリアのそれと一致させる必要はない。むしろ、例えば文字は大きく表示させて見やすくしたいとの要求から、副表示エリア３１の画素領域３３の大きさは、主表示エリア３０の画素領域３２の大きさに比べて大きく設計する。
また、従来の副表示エリアを有する液晶表示装置では、対向電極は図７に示すように対向基板４１の全面に共通した１個の対向電極１３が形成されていた。
【０００４】
ー方、アクティブマトリクス型液晶表示装置では、対向配置された一対の基板の間に液晶層を狭持してこれを表示媒体として用いており、液晶層の焼き付きを防止するために液晶層には直流電圧が重畳しない交流電圧を印加し、これを表示電圧として用いる。この交流電圧は、信号線から画素領域を主として成す画素電極へ、走査線からのゲート電圧でオン状態となったＴＦＴを介して印加される。この画素電極と液晶層を介して対向する対向電極には、ー定の直流電圧を印加する。これにより、液晶層に電界を与えてその屈折率を変化させることにより、液晶層は表示媒体として使用可能となる。
【０００５】
ところが、液晶の誘電率が電界強度に応じて変化すること、ＴＦＴのゲート電極とドレイン電極との間に寄生容量を有すること、および走査線と画素電極との間に寄生容量を有することなどに起因して、ＴＦＴをオフ状態にすベくゲート電圧を変化させたときに、画素電極の電位Ｖｐに動的な電圧降下が生ずる。
図５は液晶表示装置の駆動電圧を示す概略図である。図５（ａ）はＴＦＴのゲート電極に印加する電圧Ｖｇを、図５（ｂ）はＴＦＴのソース電極に印加する電圧Ｖｓを、図５（ｃ）はＴＦＴのドレイン電極、すなわち、画素電極の電圧Ｖｐ を示している。図５（ｃ）のＶｓｃはソース電極に印加する交流電圧の中心電圧を、図５（ｃ）のＶｃｏｍ は対向電極に印加される電圧をそれぞれ示している。対向電極と画素電極にそれぞれ電圧Ｖｃｏｍ とＶｐ を印加することにより、液晶層に実効的な電位が与えられ表示媒体として作動するようになる。図５の横軸には時間をとり、Ｖｇ、Ｖｓ、Ｖｐ のタイミングを示している。図５（ａ）に示す電圧の高電位がＴＦＴをオン状態にする期間、低電位がＴＦＴをオフ状態にする期間をそれぞれ示している。
【０００６】
ＴＦＴをオフ状態にすべくゲート電圧Ｖｇを変化させたときに、図５（ｃ）に示すように画素電極の電位Ｖｐに動的な電圧降下△Ｖｐが生ずる。これは、ＴＦＴをオフ状態にすべくゲート電圧Ｖｇを変化させたときに、一対の基板間の液晶層による容量、走査線とその上のゲート絶縁膜及び容量電極とからなる蓄積容量および上記寄生容量との間で電荷の分配が生じて、画素電極の電位Ｖｐ に電圧降下△Ｖｐが生ずるものである。
【０００７】
画素電極１１の電位の電圧降下△Ｖｐは次式（１）で示される。

Figure 0003558934
ここで、
△Ｖｐ ： 画素電極の電位の電圧降下
Ｖｇｈ ： ゲート電圧のハイ電位
Ｃｇｄｏｎ ： ＴＦＴオン時の寄生容量
Ｃｇｐ ： 走査線と画素電極の間の寄生容量
Ｖｇｌ ： ゲート電圧ロウ電位
Ｃｇｄｏｆｆ ： ＴＦＴオフ時の寄生容量
Ｖｓ ： 信号電圧の電位
Ｃｓ ： 蓄積容量
Ｃｌｃ ： 液晶層の容量
（１）式で示されるように、画素電極の電位の電圧降下△Ｖｐ を発生させる因子としては、液晶層の容量Ｃｌｃ、薄膜トランジスタの寄生容量Ｃｇｄ、蓄積容量Ｃｓ 等を含んでいる。
【０００８】
前記電圧降下△Ｖｐを発生させる一方の要因である液晶の誘電率が電界強度に応じて変化することは、液晶の物性に関わるもので避けられないものである。また、他方の要因である、ＴＦＴのゲート電極とドレイン電極との間の寄生容量及び走査線と画素電極との間の寄生容量の２つの寄生容量のうち、ＴＦＴのゲート電極とドレイン電極の間に寄生容量を有することは、前記電極間に形成したゲート絶縁膜が容量を形成してしまうことから、現在のアクティブマトリクス型液晶表示装置では構造的に避けられないものである。
【０００９】
このように画素電極の電位Ｖｐ に電圧降下△Ｖｐ が生じると、画素電極の電位Ｖｐ の正と負の電圧振幅に差が生じてしまう。電圧の極性によらず同じ電圧が印加されれば、液晶は同じ透過率特性を有するので、例えば電圧を印加しない状態で透過率の高いノーマリホワイト型のアクティブマトリクス型液晶表示装置においては、電圧振幅が大きい極性では透過率がより低く、電圧振幅が小さい極性では透過率がより高くなる。このため、透過率に応じた明暗の繰り返しが生じ、これがフリッカとして視認されてしまうことになる。
また、正と負の極性に対して電圧の振幅が非対称であると、いずれかの画素電極に交流電圧に重畳して直流的な電圧が常に印加されることになり、表示が残存するいわゆる焼き付き現象が発生する。
そこで従来は、液晶を駆動する交流電圧の正と負の電圧振幅が等しくなるように対向電極の電位を適正に調整すること、および、蓄積容量を液晶層による容量に対して並列に形成することにより、前記フリッカや焼き付きの解消をはかっていた。
【００１０】
【発明が解決しようとする課題】
ところが、主表示エリアのほかに画素領域の大きさの異なる副表示エリアを設ける場合、前記液晶容量や前記寄生容量の値が画素領域の大きさに応じて異なるので、主表示エリアと副表示エリアとで、それぞれの画素電極の電圧降下△Ｖｐに差が生じてくる。その結果、主表示エリアと副表示エリアで対向電極に印加する最適な電位が異なるにもかかわらず、従来例のように共通の対向電極を用いた場合には、どちらかの対向電極には適正電圧が印加されなくなるので、主表示エリアもしくは副表示エリアのいずれか一方にフリッカが生ずるといった問題があった。また、主表示エリアもしくは副表示エリアのいずれか一方に焼き付き現象が生ずるといった問題もあった。
【００１１】
【課題を解決するための手段】
本発明は上記の課題を解決するためになされたもので、画素領域の大きさが異なる主表示エリアと副表示エリアとを有するアクティブマトリクス型液晶表示装置において、主表示エリアと副表示エリアとで対向電極を分割することにより、それぞれの対向電極に最適な電圧を印加することを可能とし、フリッカや焼き付の発生を防止する手段を採用したものである。
すなわち、図５（ｃ）において、主表示エリアと副表示エリアとで異なる電圧降下△Ｖｐが発生する場合に、それぞれの対向電極に適正な対向電極電圧Ｖｃｏｍ を印加して、それぞれの表示エリアで正と負の極性による電圧振幅が等しくなるようにしたものである。
【００１２】
本発明に係わるアクティブマトリクス型液晶表示装置装置は、対向配置された一対の基板の間に液晶層が狭持され、前記一方の基板の表面には複数の走査線および複数の信号線がマトリクス状に交差して形成され、複数の走査線と信号線とが形成する交差部の近傍に、前記走査線に接続するゲート電極を有する薄膜トランジスタと、該薄膜トランジスタに接続する画素電極と、前記走査線と蓄積容量を形成する容量電極とがそれぞれ形成されている。前記走査線と信号線で囲まれた画素領域の大きさは互いに異なっており、主表示エリアと副表示エリアとを構成している。一方、前記他方の対向基板の液晶層側表面には対向電極が形成されておリ、主表示エリアに対向する対向電極と副表示エリアに対向する対向電極とが、分割して構成してある。
さらに、主表示エリアと副表示エリアとの画素領域の大きさが異なる場合に、すれぞれに対向する対向電極に画素領域の大きさに応じて異なった電圧を印加するように、電圧印加手段も分割して設けたものである。
かかる液晶表示装置とすることにより、主表示エリアと副表示エリアの対向電極に、それぞれの画素電極の大きさに応じた最適な電位を印加するようにした。
【００１３】
たとえば、主表示エリアは画像等を表示するためのもので高精度が要求され、副表示エリアは文字等を表示するためのもので精度はあまり問題にならない場合、主表示エリアの画素領域の大きさを副表示エリアの画素領域の大きさよりも小さく構成し、各対向電極に印加する電圧は、主表示エリアに対向する対向電極に印加する電圧の方を低くする。
すなわち式（１）において、副表示エリアの方が画素領域の大きさが大きく、液晶層の容量Ｃｌｃが大きくなり、電圧降下△Ｖｐは小さくなる。したがって図５（ｃ）において正と負の極性による電圧振幅を等しくするには、対向電極に印加する電圧は副表示エリアに対向する電極に印加する電圧の方を高くすればよい。これにより各対向電極に画素領域の大きさに見合った最適な電圧を印加することができるので、フリッカや焼き付きを防止することが可能となる。
各対向電極に異なった電圧を印加するには、電圧印加手段もそれぞれに分割して持つようにして行なう。
【００１４】
【発明の実施の形態】
以下、本発明の一実施の形態を図面に従って説明する。
図１に、本発明の一実施の形態に係わるアクティブマトリクス型液晶表示装置におけるＴＦＴアレイ基板４０の平面図を示す。
本発明においては、ＴＦＴアレイ基板４０には主表示エリア３０と副表示エリア３１にそれぞれ多数の画素領域３２及び３３がマトリクス状に配列されている。ここで画素領域とは走査線１と信号線１９で囲まれた領域であり、主表示エリア３０と副表示エリア３１にある画素領域とではその大きさを異にしている。
より具体的には、主表示エリア３０の画素領域３２の大きさは横幅４０μｍ×縦長１２０μｍ、副表示エリア３１の画素領域３３の大きさは横幅４０μｍ×縦長４００μｍである。
本実施の形態では、主表示エリア３０の画素領域３２の大きさに比ベて大きい画素領域３３から成る副表示エリア３１が、走査線方向で画素領域の幅が一致するように主表示エリア３０の上部に形成されている。
【００１５】
また、これらの画素領域を走査する走査線１と、信号を供給する信号線１９とは格子状に形成されている。信号線１９は画素領域の大きさが異なる主表示エリア３０と副表示エリア３１で途切れることなく連続して配線されている。
そしてＴＦＴアレイ基板４０に対向する対向基板４１には、図４に示すように主表示エリア３０と副表示エリア３１のそれぞれに対向する対向電極１３ａと１３ｂが配置され、それぞれ異なった電圧を印加するようにしてある。
【００１６】
主表示エリア３０および副表示エリア３１の周辺には、各表示エリア３０、３１の走査線１から外付けのゲートドライバＩＣに接続するために、走査線の端子３６まで引き出された走査線の引出し配線３４と、各表示エリア３０、３１の信号線１９から外部のソースドライバＩＣに接続するために、信号線の端子３７まで引き出された信号線の引出し配線３５とがそれぞれ形成されている。なお、本実施の形態とは異なる場合として、同一ＴＦＴアレイ基板上に駆動回路が内蔵されている場合があるが、この場合には、走査線の引出し配線と前記信号線の引出し配線がこの駆動回路の出力に引き出されていても構わない。
【００１７】
次に、図２に本実施の形態の液晶表示装置の副表示エリア３１の一画素領域３３を取り出して拡大した平面図を示す。また、図３に図２中のＴＦＴ２１、コンタクトホール１８ａ及び容量電極９を貫くＡ−Ａ’線に沿った断面図を示す。なお、主表示エリア３０の画素領域３２もその大きさが異なるのみで、構造は副表示エリア３１の画素領域３３と同様である。
図２に示すとおり、この副表示エリア３１の画素領域３３は走査線１と信号線１９とに囲まれており、紙面の左下にＴＦＴ２１が、又紙面上方に蓄積容量２２が形成されている。紙面中央部には画素電極１１が配置されている。
【００１８】
立体的に見ると図３に示すように、このＴＦＴアレイ基板４０を用いた液晶表示装置は、液晶層２０を介してＴＦＴアレイ基板４０と対向して配置された対向基板４１がある。対向基板４１には、遮光用のブラックマトリクス１５、カラーフィルタ１４、及び画素電極１１と同様なインジウムとスズの酸化物（ Ｉｎｄｉｕｍ Ｔｉｎ Ｏｘｉｄｅ ：以下、ＩＴＯと略記する）からなる透明な対向電極１３を設けてある。液晶と接する面には配向膜１２が形成されている。従って、画素電極１１と対向電極１３との間に電圧を印加すると、液晶層２０に電界が印加され、液晶分子の配向制御ができるようになっている。また、この構造は画素電極１１と対向電極１３をそれぞれ電極に持ち、その間に誘電体である液晶層２０を有することから、容量と見なすことができる（以下、これを液晶容量と呼ぶ）。
【００１９】
ＴＦＴは、図２及び図３に示すように、走査線１から引き出して設けられたゲート電極２を設け、その上にチッ化珪素からなるゲート絶縁膜３を設け、その上にアモルファスシリコンからなる半導体膜４を設け、更にその上にはアモルファシリコンにリンを添加したｎ＋型アモルファスシリコンからなるオーミックコンタクト膜５を設け、その上に導電体からなるドレイン電極７とソース電極８とを設けて形成されている。このうちソース電極８は信号線１９から引き出して設けられている。そして更にドレイン電極７とソース電極８の上には、これらを覆うようにチッ化珪素からなるパッシベーション膜１０を設け、ドレイン電極７上のパッシベーション膜１０にはコンタクトホール１８ａが形成されている。そしてドレイン電極７とＩＴＯからなる透明な画素電極１１とがコンタクトホール１８ａを介して接続されている。
【００２０】
蓄積容量２２は、走査線１を一方の電極とし、その上のゲート絶縁膜３を誘電体として形成し、更にその上に他方の電極となる容量電極９を形成してある。容量電極９はドレイン電極７やソース電極８と同一の導電体により形成してある。容量電極９の上にはＴＦＴ２１と同様、パッシベーション膜１０が形成され、このパッシベーション膜１０にはコンタクトホール１８ｂを形成して、ＩＴＯからなる画素電極１１を容量電極９の上に引き出して設けて、容量電極９と画素電極１１とをコンタクトホール１８ｂを介して接続してある。なお、蓄積容量２２は先に述べた液晶容量と並列接続の関係にあり、ともにＴＦＴ２１の負荷容量となる。
【００２１】
本実施の形態では、それぞれ横幅４０μｍ×縦長ｌ２０μｍの大きさの画素領域を有する主表示エリア３０と、横幅４０μｍ×縦長４００μｍの大きさの画素領域を有する副表示エリア３１の２つが同一のＴＦＴアレイ基板４０上に形成されいる。これらに対向する対向電極１３ａ及び１３ｂは、図４に示すように一つの対向基板４１上に各表示エリア毎に分割して配置してある。
対向電極１３ａ、１３ｂも画素電極１１と同一のＩＴＯ膜で形成する。
各対向電極１３の大きさ（面積）は、主表示エリア３０と副表示エリア３１の面積にほぼ等しく構成する。
【００２２】
この分割した各対向電極に最適な電圧を印加するには、電圧印加手段として直流電圧を発生するためのＤＣ／ＤＣコンバーター（図示省略）を２系列に分けて準備する。各ＤＣ／ＤＣコンバーターにつきそれぞれの対向電極に最適な電圧に変換して、それぞれの対向電極に印加すればよい。
【００２３】
本実施の形態では、主表示エリア３０の画素領域３２の大きさが副表示エリア３１の画素領域３３の大きさよりも小さいので、主表示エリア３０の対向電極１３ａに印加する電圧は、副表示エリア３１の対向電極１３ｂに印加する電圧よりも低くする。例えば本実施の形態では、主表示エリア３０の対向電極１３ａに印加する電圧は３．７Ｖ、副表示エリア３１の対向電極１３ｂに印加する電圧は４．０Ｖとする。
【００２４】
以上説明したとおり、本発明では画素領域の大きさの異なる二つの表示エリアにある二つの対向電極に異なる電圧を印加してある。つまり図５（ｃ）において表示エリアの画素領域の大きさに応じてＶｃｏｍ の値を変化させ、その結果正と負の極性による電圧振幅の差を解消させるようにした。
【００２５】
【発明の効果】
本発明に係わるアクティブマトリクス型液晶表示装置は、対向電極を分割することにより、それぞれの画素領域の大きさに応じて最適な電圧を印加することが可能となり、その結果フリッカや焼き付きを防止することができる。
【図面の簡単な説明】
【図１】本発明の一実施の形態に使用するＴＦＴアレイ基板の平面図である。
【図２】図１に示したＴＦＴアレイ基板の副表示エリアの一画素領域近傍を拡大して示す平面図である。
【図３】図２のＡ−Ａ’線に沿った断面図である。
【図４】本発明の対向電極を示す平面図である。
【図５】液晶表示装置の駆動電圧を説明する図である。
【図６】従来のＴＦＴアレイ基板を示す平面図である。
【図７】従来の対向電極を示す平面図である。
【符号の説明】
１・・・・・走査線、２・・・・・ゲート電極、３・・・・・ゲート絶縁膜、４・・・・・半導体膜、５・・・・・オーミックコンタクト膜、７・・・・・ドレイン電極、８・・・・ソース電極、９・・・・・容量電極、１０・・・・・パッシベーション膜、１１・・・・・画素電極、１２・・・・・配向膜、１３・・・・・対向電極、１３ａ・・・・・主表示エリアの対向電極、１３ｂ・・・・・副表示エリアの対向電極、１４・・・・・カラーフィルタ、１５・・・・ブラックマトリクス、１６、１７・・・・・透明基板、１８ａ，１８ｂ・・・・コンタクトホール、１９・・・・信号線、２０・・・・・液晶層、２１・・・・・ＴＦＴ、２２・・・・・蓄積容量、３０・・・・・主表示エリア、３１・・・・・副表示エリア、３２・・・・・主表示エリアの画素領域、３３・・・・副表示エリアの画素領域、３４・・・・・走査線側引出し線、３５・・・・・信号線側引出し線、３６・・・・・走査線側端子、３７・・・・・信号線側端子、４０・・・・ＴＦＴアレイ基板、４１・・・・・対向基板、１０１・・・・・走査線、１１９・・・・・信号線、 １３０・・・・・表示エリア、１３２・・・・・画素領域、１３４・・・・走査線側引出し線、１３５・・・・・信号線側引出し線、１３６・・・・・走査線側端子、１３７・・・・信号線側端子、１４０・・・・・ＴＦＴアレイ基板[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an active matrix type liquid crystal display device. More specifically, the present invention relates to a counter electrode structure of an active matrix type liquid crystal display device having a main display area and a sub display area having different pixel regions.
[0002]
[Prior art]
Conventionally, as an active matrix type liquid crystal display device, the one shown in FIG. 6 is known. FIG. 6 is a plan view of a thin film transistor (hereinafter, abbreviated as TFT) array substrate 140.
On a TFT array substrate 140 of a conventional active matrix device, a display area 130 in which pixel regions 132 constituting pixels are arranged in a matrix is connected to an external gate driver IC from a scanning line 101 of the display area 130. And a signal line terminal 137 for connecting a signal line 119 of the display area 130 to an external source driver IC from the signal line 119 of the display area 130, respectively. .
[0003]
From the viewpoint that a new function can be added to the conventional active matrix type liquid crystal display device, for example, character information is displayed in addition to the display area 30 (hereinafter referred to as a main display area) as shown in FIG. The necessity of providing another display area 31 (hereinafter, referred to as a sub display area) for the purpose of being called is suggested.
In this case, the pixel area 32 is made smaller because the main display area 30 is required to have a high definition display, but the size of the pixel area 33 is not necessarily made smaller in the sub display area 31 for the purpose of display. There is no need to match it. Rather, for example, the size of the pixel region 33 of the sub-display area 31 is designed to be larger than the size of the pixel region 32 of the main display area 30 because of the requirement that the characters be displayed large and easy to see.
Further, in the conventional liquid crystal display device having a sub-display area, one common counter electrode 13 is formed on the entire surface of the common substrate 41 as the common electrode as shown in FIG.
[0004]
On the other hand, in an active matrix type liquid crystal display device, a liquid crystal layer is sandwiched between a pair of substrates arranged opposite to each other and is used as a display medium. An AC voltage on which no DC voltage is superimposed is applied and used as a display voltage. This AC voltage is applied from a signal line to a pixel electrode mainly forming a pixel region via a TFT turned on by a gate voltage from a scanning line. A constant DC voltage is applied to a counter electrode facing the pixel electrode via the liquid crystal layer. Thus, by applying an electric field to the liquid crystal layer to change its refractive index, the liquid crystal layer can be used as a display medium.
[0005]
However, the dielectric constant of the liquid crystal changes in accordance with the electric field strength, a parasitic capacitance exists between the gate electrode and the drain electrode of the TFT, and a parasitic capacitance exists between the scanning line and the pixel electrode. For this reason, when the gate voltage is changed to turn off the TFT, a dynamic voltage drop occurs in the potential Vp of the pixel electrode.
FIG. 5 is a schematic diagram showing a driving voltage of the liquid crystal display device. 5A shows the voltage Vg applied to the gate electrode of the TFT, FIG. 5B shows the voltage Vs applied to the source electrode of the TFT, and FIG. 5C shows the drain electrode of the TFT, that is, the pixel electrode. The voltage Vp is shown. Vsc in FIG. 5C indicates the center voltage of the AC voltage applied to the source electrode, and Vcom in FIG. 5C indicates the voltage applied to the counter electrode. By applying the voltages Vcom and Vp to the counter electrode and the pixel electrode, respectively, an effective potential is given to the liquid crystal layer, and the liquid crystal layer operates as a display medium. The horizontal axis in FIG. 5 shows time and shows the timings of Vg, Vs, and Vp. A high potential of the voltage shown in FIG. 5A indicates a period in which the TFT is turned on, and a low potential indicates a period in which the TFT is turned off.
[0006]
When the gate voltage Vg is changed to turn off the TFT, a dynamic voltage drop ΔVp occurs in the potential Vp of the pixel electrode as shown in FIG. This is because, when the gate voltage Vg is changed to turn off the TFT, the capacitance due to the liquid crystal layer between the pair of substrates, the storage capacitance composed of the scanning line and the gate insulating film and the capacitance electrode thereon, and the parasitic capacitance The distribution of charge between the capacitor and the capacitor occurs, causing a voltage drop ΔVp in the potential Vp of the pixel electrode.
[0007]
The voltage drop ΔVp of the potential of the pixel electrode 11 is expressed by the following equation (1).
Figure 0003558934
here,
ΔVp: voltage drop of the potential of the pixel electrode Vgh: high potential of the gate voltage Cgdon: parasitic capacitance when the TFT is on Cgp: parasitic capacitance between the scanning line and the pixel electrode Vgl: gate voltage low potential Cgdoff: parasitic when the TFT is off Capacitance Vs: potential of signal voltage Cs: storage capacitance Clc: capacitance of liquid crystal layer As shown in the equation (1), factors that generate the voltage drop ΔVp of the potential of the pixel electrode include the capacitance Clc of the liquid crystal layer and the thin film transistor , The parasitic capacitance Cgd, the storage capacitance Cs, and the like.
[0008]
It is inevitable that the dielectric constant of the liquid crystal, which is one of the factors that cause the voltage drop ΔVp, changes according to the electric field strength because it relates to the physical properties of the liquid crystal. Also, of the two other parasitic capacitances, the parasitic capacitance between the gate electrode and the drain electrode of the TFT and the parasitic capacitance between the scanning line and the pixel electrode, between the gate electrode and the drain electrode of the TFT. Having a parasitic capacitance is inevitable structurally in the current active matrix type liquid crystal display device because the gate insulating film formed between the electrodes forms a capacitance.
[0009]
As described above, when the voltage drop ΔVp occurs in the potential Vp of the pixel electrode, a difference occurs between the positive and negative voltage amplitudes of the potential Vp of the pixel electrode. If the same voltage is applied irrespective of the polarity of the voltage, the liquid crystal has the same transmittance characteristics. For example, in a normally white type active matrix liquid crystal display device having a high transmittance in a state where no voltage is applied, the voltage is high. Polarity having a large amplitude has a lower transmittance, and polarity having a small voltage amplitude has a higher transmittance. For this reason, light / dark repetition occurs according to the transmittance, and this is visually recognized as flicker.
If the amplitude of the voltage is asymmetric with respect to the positive and negative polarities, a DC voltage is always applied to any one of the pixel electrodes, superimposed on the AC voltage. The phenomenon occurs.
Therefore, conventionally, the potential of the counter electrode is appropriately adjusted so that the positive and negative voltage amplitudes of the AC voltage for driving the liquid crystal become equal, and the storage capacitor is formed in parallel with the capacitance of the liquid crystal layer. Thus, the flicker and image sticking are eliminated.
[0010]
[Problems to be solved by the invention]
However, when a sub-display area having a different pixel area size is provided in addition to the main display area, the values of the liquid crystal capacitance and the parasitic capacitance differ depending on the size of the pixel area. Thus, a difference occurs between the voltage drops ΔVp of the respective pixel electrodes. As a result, when a common counter electrode is used as in the conventional example, the optimum potential applied to the counter electrode is different between the main display area and the sub display area. Since no voltage is applied, flicker occurs in either the main display area or the sub display area. There is also a problem that a burn-in phenomenon occurs in one of the main display area and the sub-display area.
[0011]
[Means for Solving the Problems]
The present invention has been made to solve the above problems, and in an active matrix type liquid crystal display device having a main display area and a sub display area having different pixel regions, the main display area and the sub display area have different sizes. By dividing the opposing electrodes, it is possible to apply an optimal voltage to each opposing electrode, and to adopt a means for preventing the occurrence of flicker and image sticking.
That is, in FIG. 5C, when a different voltage drop ΔVp occurs between the main display area and the sub-display area, an appropriate common electrode voltage Vcom is applied to each common electrode, and each of the display areas is applied. The voltage amplitudes for the positive and negative polarities are made equal.
[0012]
In an active matrix type liquid crystal display device according to the present invention, a liquid crystal layer is sandwiched between a pair of substrates arranged opposite to each other, and a plurality of scanning lines and a plurality of signal lines are arranged in a matrix on the surface of the one substrate. A thin film transistor having a gate electrode connected to the scanning line in the vicinity of an intersection formed by a plurality of scanning lines and signal lines, a pixel electrode connected to the thin film transistor, and the scanning line. And a capacitor electrode forming a storage capacitor. The pixel regions surrounded by the scanning lines and the signal lines have different sizes, and constitute a main display area and a sub display area. On the other hand, a counter electrode is formed on the liquid crystal layer side surface of the other counter substrate, and a counter electrode facing the main display area and a counter electrode facing the sub display area are configured separately. .
Further, when the size of the pixel area in the main display area and the size of the pixel area in the sub-display area are different, voltage applying means is configured to apply different voltages to the counter electrodes facing each other according to the size of the pixel area. Are also provided separately.
With such a liquid crystal display device, an optimal potential according to the size of each pixel electrode is applied to the opposing electrodes in the main display area and the sub display area.
[0013]
For example, if the main display area is for displaying an image or the like and high accuracy is required, and the sub-display area is for displaying characters or the like and the accuracy is not so important, the size of the pixel area of the main display area may be large. The sub-display area is configured to be smaller than the size of the pixel area, and the voltage applied to each counter electrode is lower than the voltage applied to the counter electrode facing the main display area.
That is, in the formula (1), the size of the pixel region is larger in the sub display area, the capacitance Clc of the liquid crystal layer is larger, and the voltage drop ΔVp is smaller. Therefore, in order to make the voltage amplitudes due to the positive and negative polarities equal in FIG. 5C, the voltage applied to the counter electrode should be higher than the voltage applied to the electrode facing the sub display area. Thus, an optimal voltage corresponding to the size of the pixel region can be applied to each counter electrode, so that flicker and image sticking can be prevented.
In order to apply different voltages to the respective counter electrodes, voltage applying means is separately provided.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 shows a plan view of a TFT array substrate 40 in an active matrix type liquid crystal display device according to one embodiment of the present invention.
In the present invention, on the TFT array substrate 40, a large number of pixel regions 32 and 33 are arranged in a matrix in the main display area 30 and the sub display area 31, respectively. Here, the pixel area is an area surrounded by the scanning line 1 and the signal line 19, and the size of the pixel area in the main display area 30 is different from that of the pixel area in the sub display area 31.
More specifically, the size of the pixel area 32 in the main display area 30 is 40 μm in width × 120 μm in height, and the size of the pixel area 33 in the sub display area 31 is 40 μm in width × 400 μm in height.
In the present embodiment, the sub-display area 31 composed of the pixel area 33 which is larger than the size of the pixel area 32 of the main display area 30 is arranged such that the width of the pixel area is the same in the scanning line direction. Is formed at the top.
[0015]
The scanning lines 1 for scanning these pixel regions and the signal lines 19 for supplying signals are formed in a grid. The signal line 19 is continuously wired without interruption in the main display area 30 and the sub display area 31 having different pixel area sizes.
Then, on a counter substrate 41 facing the TFT array substrate 40, counter electrodes 13a and 13b facing the main display area 30 and the sub display area 31, respectively, are arranged as shown in FIG. It is like that.
[0016]
In the vicinity of the main display area 30 and the sub display area 31, the scanning lines are drawn out to the scanning line terminals 36 in order to connect the scanning lines 1 of the display areas 30 and 31 to the external gate driver IC. In order to connect the wiring 34 and the signal line 19 in each of the display areas 30 and 31 to an external source driver IC, a wiring 35 for a signal line extending to a terminal 37 of the signal line is formed. Note that as a case different from the present embodiment, there is a case where a drive circuit is built in on the same TFT array substrate. In this case, the lead wiring of the scanning line and the lead wiring of the signal line are driven by the driving circuit. It may be drawn to the output of the circuit.
[0017]
Next, FIG. 2 shows a plan view in which one pixel region 33 of the sub display area 31 of the liquid crystal display device of the present embodiment is taken out and enlarged. FIG. 3 is a sectional view taken along the line AA 'penetrating the TFT 21, the contact hole 18a, and the capacitor electrode 9 in FIG. The structure of the pixel region 32 of the main display area 30 is the same as that of the pixel region 33 of the sub-display area 31 except for the size.
As shown in FIG. 2, the pixel area 33 of the sub-display area 31 is surrounded by the scanning lines 1 and the signal lines 19, and the TFT 21 is formed at the lower left of the paper and the storage capacitor 22 is formed at the upper part of the paper. The pixel electrode 11 is disposed in the center of the paper.
[0018]
When viewed three-dimensionally, as shown in FIG. 3, the liquid crystal display device using the TFT array substrate 40 has an opposing substrate 41 arranged to face the TFT array substrate 40 with the liquid crystal layer 20 interposed therebetween. On the counter substrate 41, a black matrix 15 for light shielding, a color filter 14, and a transparent counter electrode 13 made of indium and tin oxide (Indium Tin Oxide: hereinafter abbreviated as ITO) similar to the pixel electrode 11 are provided. It is provided. An alignment film 12 is formed on a surface in contact with the liquid crystal. Therefore, when a voltage is applied between the pixel electrode 11 and the counter electrode 13, an electric field is applied to the liquid crystal layer 20, and the alignment of the liquid crystal molecules can be controlled. In addition, since this structure has the pixel electrode 11 and the counter electrode 13 as electrodes, and has the liquid crystal layer 20 as a dielectric between them, it can be regarded as a capacitance (hereinafter, this is referred to as a liquid crystal capacitance).
[0019]
As shown in FIGS. 2 and 3, the TFT is provided with a gate electrode 2 extending from the scanning line 1, a gate insulating film 3 made of silicon nitride provided thereon, and an amorphous silicon formed thereon. A semiconductor film 4 is provided, an ohmic contact film 5 made of n + type amorphous silicon obtained by adding phosphorus to amorphous silicon is provided thereon, and a drain electrode 7 and a source electrode 8 made of a conductor are provided thereon. Have been. The source electrode 8 is provided to extend from the signal line 19. Further, a passivation film 10 made of silicon nitride is provided on the drain electrode 7 and the source electrode 8 so as to cover them, and a contact hole 18a is formed in the passivation film 10 on the drain electrode 7. The drain electrode 7 and the transparent pixel electrode 11 made of ITO are connected via the contact hole 18a.
[0020]
The storage capacitor 22 has the scanning line 1 as one electrode, the gate insulating film 3 thereon as a dielectric, and the capacitor electrode 9 as the other electrode thereon. The capacitance electrode 9 is formed of the same conductor as the drain electrode 7 and the source electrode 8. A passivation film 10 is formed on the capacitor electrode 9 in the same manner as the TFT 21. A contact hole 18 b is formed in the passivation film 10, and the pixel electrode 11 made of ITO is drawn out and provided on the capacitor electrode 9. The capacitor electrode 9 and the pixel electrode 11 are connected via a contact hole 18b. Note that the storage capacitor 22 is connected in parallel with the above-described liquid crystal capacitor, and both become the load capacitance of the TFT 21.
[0021]
In this embodiment, the same TFT array has two main display areas 30 each having a pixel area of 40 μm in width × 120 μm in height and a sub-display area 31 having a pixel area of 40 μm in width × 400 μm in length. It is formed on a substrate 40. The opposing electrodes 13a and 13b opposing these are arranged separately on a single opposing substrate 41 for each display area as shown in FIG.
The counter electrodes 13a and 13b are also formed of the same ITO film as the pixel electrode 11.
The size (area) of each counter electrode 13 is substantially equal to the area of the main display area 30 and the sub display area 31.
[0022]
In order to apply an optimum voltage to each of the divided counter electrodes, a DC / DC converter (not shown) for generating a DC voltage is prepared as a voltage application unit in two series. What is necessary is just to convert each DC / DC converter into a voltage optimal for each counter electrode and apply it to each counter electrode.
[0023]
In the present embodiment, since the size of the pixel region 32 of the main display area 30 is smaller than the size of the pixel region 33 of the sub display area 31, the voltage applied to the counter electrode 13a of the main display area 30 is The voltage is lower than the voltage applied to the counter electrode 13b. For example, in the present embodiment, the voltage applied to the opposing electrode 13a in the main display area 30 is 3.7V, and the voltage applied to the opposing electrode 13b in the sub display area 31 is 4.0V.
[0024]
As described above, in the present invention, different voltages are applied to the two opposing electrodes in the two display areas having different sizes of the pixel regions. That is, in FIG. 5C, the value of Vcom is changed according to the size of the pixel area in the display area, and as a result, the difference between the voltage amplitudes due to the positive and negative polarities is eliminated.
[0025]
【The invention's effect】
In the active matrix type liquid crystal display device according to the present invention, it is possible to apply an optimal voltage according to the size of each pixel region by dividing the counter electrode, thereby preventing flicker and image sticking. Can be.
[Brief description of the drawings]
FIG. 1 is a plan view of a TFT array substrate used in an embodiment of the present invention.
FIG. 2 is an enlarged plan view showing the vicinity of one pixel area of a sub display area of the TFT array substrate shown in FIG.
FIG. 3 is a sectional view taken along the line AA ′ of FIG. 2;
FIG. 4 is a plan view showing a counter electrode of the present invention.
FIG. 5 is a diagram illustrating a driving voltage of a liquid crystal display device.
FIG. 6 is a plan view showing a conventional TFT array substrate.
FIG. 7 is a plan view showing a conventional counter electrode.
[Explanation of symbols]
1 scanning line, 2 gate electrode, 3 gate insulating film, 4 semiconductor film, 5 ohmic contact film, 7 ... Drain electrode, 8 ... Source electrode, 9 ... Capacitance electrode, 10 ... Passivation film, 11 ... Pixel electrode, 12 ... Alignment film, 13 ······································································································································· Black 15 Matrix, 16, 17,..., Transparent substrate, 18a, 18b, contact hole, 19, signal line, 20,... Liquid crystal layer, 21,. ····· Storage capacity, 30 ···· Main display area, 31 ····· Sub display area, 32 ··· ..Pixel region in main display area, 33 ... Pixel region in sub-display area, 34 ... Readout line on scanning line side, 35 ... Readout line on signal line side, 36 ... ... Scanning line side terminal, 37... Signal line side terminal, 40... TFT array substrate, 41... Counter substrate, 101... Scanning line, 119. Signal line, 130, display area, 132, pixel area, 134, scanning line side lead line 135, signal line side lead line, 136 ... Scanning line side terminal, 137... Signal line side terminal, 140... TFT array substrate

Claims (4)

対向配置された一対の基板の間に液晶層が狭持され、前記一方の基板の表面には複数の走査線および複数の信号線がマトリクス状に交差して形成され、複数の走査線と信号線とが形成する交差部の近傍に、前記走査線に接続するゲート電極を有する薄膜トランジスタと、該薄膜トランジスタに接続する画素電極と蓄積容量とがそれぞれ形成されており、走査線と信号線で囲まれた画素領域の大きさが互い異なる主表示エリアと副表示エリアとを具備し、前記他方の対向基板の液晶層側表面には対向電極が形成されており、前記主表示エリアに対向する対向電極と前記副表示エリアに対向する対向電極とが分割して構成されていることを特徴とするアクティブマトリクス型液晶表示装置。A liquid crystal layer is sandwiched between a pair of substrates arranged opposite to each other, and a plurality of scanning lines and a plurality of signal lines are formed on a surface of the one substrate so as to intersect in a matrix, and a plurality of scanning lines and signal lines are formed. A thin film transistor having a gate electrode connected to the scanning line, a pixel electrode connected to the thin film transistor, and a storage capacitor are formed in the vicinity of the intersection formed by the scanning line and the signal line. A main display area and a sub display area having different sizes of pixel regions, and a counter electrode is formed on a liquid crystal layer side surface of the other counter substrate, and a counter electrode facing the main display area is provided. And an opposing electrode opposing the sub-display area. 前記主表示エリアの画素領域の大きさが、前記副表示エリアの画素領域の大きさよりも小さいことを特徴とする請求項１に記載のアクティブマトリクス型液晶表示装置。2. The active matrix type liquid crystal display device according to claim 1, wherein the size of the pixel area in the main display area is smaller than the size of the pixel area in the sub display area. 前記主表示エリアに対向する対向電極と前記副表示エリアに対向する対向電極とに、異なる電圧を印加するような電圧印加手段を備えたことを特徴とする請求項１に記載のアクティブマトリクス型液晶表示装置。2. The active matrix type liquid crystal according to claim 1, further comprising voltage applying means for applying different voltages to a counter electrode facing the main display area and a counter electrode facing the sub display area. Display device. 前記主表示エリアの画素領域の大きさが、前記副表示エリアの画素領域の大きさよりも小さく、かつ前記主表示エリアに対向する対向電極に印加する電圧が、前記副表示エリアに対向する対向電極に印加する電圧よりも低くなるような電圧印加手段を備えたことを特徴とする請求項３に記載のアクティブマトリクス型液晶表示装置。The size of the pixel area of the main display area is smaller than the size of the pixel area of the sub-display area, and the voltage applied to the counter electrode facing the main display area is the voltage of the counter electrode facing the sub-display area. 4. The active matrix type liquid crystal display device according to claim 3, further comprising a voltage applying means which is lower than a voltage applied to the liquid crystal display device.
JP29296799A 1999-10-14 1999-10-14 Active matrix type liquid crystal display Expired - Fee Related JP3558934B2 (en)

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JP29296799A JP3558934B2 (en) 1999-10-14 1999-10-14 Active matrix type liquid crystal display
EP00306528A EP1093009A3 (en) 1999-10-14 2000-07-31 Active-matrix liquid-crystal display apparatus which prevents flicker
KR10-2000-0059694A KR100371757B1 (en) 1999-10-14 2000-10-11 Active matrix type liquid crystal display
CN00129680A CN1129028C (en) 1999-10-14 2000-10-12 Active matrix type liquid crystal display device
US09/687,633 US6529257B1 (en) 1999-10-14 2000-10-12 Active-matrix liquid-crystal display apparatus which prevents flicker and image sticking in main display area and sub display area

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