CN219590639U - Array substrate, display panel and display device - Google Patents

Abstract

The utility model discloses an array substrate, a display panel and a display device, wherein the array substrate comprises a plurality of sub-pixels arranged in an array, each sub-pixel comprises a main area pixel and a sub-area pixel, and the array substrate further comprises: the pixel electrode of the secondary region is connected with the pixel electrode of the primary region through a first connecting wire; the main region pixel electrode is arranged in the region of the main region pixel and is connected with the source electrode of the thin film transistor through a via hole; the sub-region pixel electrode is arranged in the region of the sub-region pixel; and the sub-region capacitor electrode and the sub-region pixel electrode are arranged on different layers and are connected with the sub-region pixel electrode through a via hole, and the sub-region capacitor electrode and the source electrode extension line form a compensation capacitor. By the scheme, the aperture opening ratio of the display panel in the eight-domain design of the DRD design and the pixel is improved.

Description

Array substrate, display panel and display device

Technical Field

The present utility model relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a display device.

Background

When the liquid crystal display (Thin Film Transistor Liquid Crystal Display, TFT-LCD) is driven, the driving mode is Line-by-Line (progressive scanning), when the scanning signal is high level, the corresponding Line thin film transistor (Thin Film Transistor, TFT) is turned on, the data signal is written in the column direction through the data Line to realize the charging of the pixel unit, each pixel unit comprises a liquid crystal capacitor Clc and a storage capacitor Cst, the input end of the pixel unit is connected to the output end of the corresponding thin film transistor (Thin Film Transistor, TFT), the control end of the TFT is connected to the scanning Line responsible for transmitting the switching signal, the input end of the TFT is connected to the data Line responsible for transmitting the data signal, one end of Cst and Clc is a pixel electrode, and the other end is a common Line (VCOM). Generally, in the lcd, the DRD (Double Row Driving) design is increasingly applied, because the design can save COF (Chip On Film) and reduce the cost.

However, when the DRD design is adopted, the aperture ratio is reduced compared with the conventional product due to the limitation of the pixel structure, and in general, the pixel adopts a four-domain design. And because of the limitation of the aperture ratio, the pixel design generally does not use eight-domain design so as to ensure a certain aperture ratio. How to realize a pixel eight-domain design in a DRD design, and ensuring a higher aperture ratio becomes a technical problem to be solved by those skilled in the art.

Disclosure of Invention

The utility model aims to provide an array substrate, a display panel and a display device, which are used for improving the aperture opening ratio of the display panel in a DRD design and an eight-domain design of pixels.

The utility model discloses an array substrate, which comprises a plurality of sub-pixels arranged in an array, wherein each sub-pixel comprises a main area pixel and a sub-area pixel, and the area of the array substrate corresponding to each sub-pixel further comprises: the pixel electrode comprises a thin film transistor, a main area pixel electrode, a sub area pixel electrode and a sub area capacitance electrode, wherein a source electrode extension line is arranged on one side of the thin film transistor and extends from a source electrode of the thin film transistor to an area of the sub area pixel; the main region pixel electrode is arranged in the region of the main region pixel and is connected with the source electrode of the thin film transistor through a via hole; the sub-region pixel electrode is arranged in the region of the sub-region pixel; the secondary region capacitor electrode and the secondary region pixel electrode are arranged on different layers and are connected with each other through a via hole, and the secondary region capacitor electrode and the source electrode extension line form a compensation capacitor.

Optionally, the array substrate includes a substrate, a first metal layer, a second metal layer and a transparent conductive layer, which are stacked, wherein the first metal layer and the second metal layer are arranged in an insulating manner, and the second metal layer and the transparent conductive layer are arranged in an insulating manner; the main area pixel electrode and the secondary area pixel electrode are formed on the transparent conductive layer in the same layer; the source electrode extension line is formed on the second metal layer, the secondary region capacitance electrode is formed on the first metal layer, and the secondary region capacitance electrode is overlapped with the source electrode extension line on the projection of the substrate.

Optionally, the secondary area capacitor electrode is disposed in an area of the secondary area pixel and extends to an area of the primary area pixel; the source electrode extension line is arranged across the area of the main area pixel and extends to the area of the secondary area pixel; the area of the main area pixel is smaller than or equal to the area of the secondary area pixel.

Optionally, the widths of the secondary region capacitor electrode and the source electrode extension line are equal, and the secondary region capacitor electrode and the source electrode extension line completely coincide on the projection of the substrate.

Optionally, the array substrate includes a plurality of scan lines and a plurality of data lines; the sub-region pixel electrodes and the main region pixel electrodes are arranged along the data line direction, and the source electrode extension line is disposed on a central axis of a side of the sub-region pixel electrode in the extending direction of the scanning line on the substrate projection.

Optionally, the array substrate includes a plurality of scan lines and a plurality of data lines; two scanning lines are arranged between two adjacent rows of the sub-pixels in the extending direction of the data lines, and two columns of the sub-pixels are arranged between two adjacent data lines in the extending direction of the scanning lines; in the same row of the sub-pixels, the thin film transistors corresponding to the adjacent sub-pixels are respectively connected to different scanning lines; in the same row of the sub-pixels, two sub-pixels between two adjacent data lines are respectively of eight-domain pixel structures, and only two thin film transistors are correspondingly connected with the two sub-pixels respectively.

Optionally, the array substrate further includes a common electrode line, where the common electrode line is formed on the first metal layer and is disposed around the secondary area capacitor electrode, a main storage capacitor is formed between the main area pixel electrode and the common electrode line, and a secondary area storage capacitor is formed between the secondary area pixel electrode and the common electrode line; the gray scale of the main area pixel is higher than that of the secondary area pixel.

Optionally, the array substrate includes a plurality of scan lines and a plurality of data lines; the secondary region pixel electrodes and the primary region pixel electrodes are arranged along the data line direction, and the source electrode extension line is arranged close to the data line on the substrate projection.

The utility model also discloses a display panel which comprises the opposite substrate and the array substrate, wherein the opposite substrate and the array substrate are arranged in a box-to-box manner.

The utility model also discloses a display device which comprises the backlight module and the display panel.

According to the utility model, the main area pixels and the secondary area pixels are charged simultaneously when the thin film transistors are turned on in a mode of sharing the thin film transistors by the main area pixels and the secondary area pixels. The main region pixel electrode of the main region pixel is connected to the source of the thin film transistor through a via hole. The sub-region pixel electrode of the sub-region pixel is connected with the sub-region capacitor electrode and forms a compensation capacitor with the source electrode extension line on the thin film transistor, and the gray scale voltages of the main region pixel and the sub-region pixel are different under the condition that the main region pixel and the sub-region pixel are input with the same data signal at the same time through the effect of the compensation capacitor, so that different gray scales are displayed. In the scheme, in one sub-pixel region, although the main region pixel electrode and the secondary region pixel electrode are arranged, the two pixel electrodes can be driven by one thin film transistor, so that the number of the thin film transistors is further saved. Particularly, for the scheme that the main area pixels and the secondary area pixels are respectively charged by using the thin film transistors, the number of the thin film transistors is greatly reduced, and then the aperture opening ratio of the display panel is improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of embodiments of the utility model and are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description serve to explain the principles of the utility model. It is evident that the figures in the following description are only some embodiments of the utility model, from which other figures can be obtained without inventive effort for a person skilled in the art. In the drawings:

FIG. 1 is a schematic diagram of a display panel according to the present utility model;

FIG. 2 is a schematic diagram of an array substrate according to the present utility model;

FIG. 3 is a schematic diagram of a pixel structure of an array substrate according to the present utility model;

FIG. 4 is a schematic cross-sectional view of an array substrate of the present utility model;

fig. 5 is an equivalent circuit diagram of the pixel driving circuit of the present utility model;

fig. 6 is a schematic diagram of a display device of the present utility model.

1, a display panel; 2. a display device; 3. a backlight module; 4. an array substrate; 5. an opposite substrate; 10. a substrate; 11. a first metal layer; 12. a second metal layer; 13. a transparent conductive layer; 100. a sub-pixel; 110. a main region pixel; 111. a main region pixel electrode; 120. sub-region pixels; 121. a sub-region pixel electrode; 122. a sub-region capacitance electrode; 130. a thin film transistor; 131. a source extension line; 132. a via hole; 133. a common electrode line; 200. a data line; 300. scanning lines.

Detailed Description

It is to be understood that the terminology used herein, the specific structural and functional details disclosed are merely representative for the purpose of describing particular embodiments, but that the utility model may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

In the description of the present utility model, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or implicitly indicating the number of technical features indicated. Thus, unless otherwise indicated, features defining "first", "second" may include one or more such features either explicitly or implicitly; the meaning of "plurality" is two or more. In addition, terms of the azimuth or positional relationship indicated by "upper", "lower", "left", "right", "vertical", "horizontal", etc., are described based on the azimuth or relative positional relationship shown in the drawings, and are merely for convenience of description of the present utility model, and do not indicate that the apparatus or element referred to must have a specific azimuth, be constructed and operated in a specific azimuth, and thus should not be construed as limiting the present utility model. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.

The utility model is described in detail below with reference to the attached drawings and alternative embodiments.

Fig. 1 is a schematic view of a display panel according to the present utility model, and referring to fig. 1, the present utility model discloses a display panel, wherein the display panel 1 includes an array substrate 4 and a counter substrate 5 (not shown in the figure), the counter substrate and the array substrate are disposed in a box-to-box manner, and a liquid crystal layer is disposed between the array substrate 4 and the counter substrate, and the display panel according to the present utility model is a liquid crystal display panel.

Fig. 2 is a schematic diagram of an array substrate according to the present utility model, the array substrate 4 includes a plurality of sub-pixels 100 arranged in an array, each sub-pixel 100 includes a main area pixel 110 and a sub-area pixel 120, and the area of the display panel 1 corresponding to each sub-pixel 100 further includes: a thin film transistor 130, a main region pixel electrode 111, a sub region pixel electrode 121, and a sub region capacitance electrode 122, wherein a source extension line 131 is disposed on one side of the thin film transistor 130, and the source extension line 131 extends from a source of the thin film transistor 130 to a region of the sub region pixel 120; the main region pixel electrode 111 is disposed in the region of the main region pixel 110 and is connected to the source of the thin film transistor 130 through a via 132; the sub-region pixel electrode 121 is disposed in the region of the sub-pixel; and the sub-region capacitor electrode 122 and the sub-region pixel electrode 121 are arranged in different layers, and are connected with the sub-region pixel electrode 121 through a via hole 132, and the sub-region capacitor electrode 122 and the source extension line 131 form a compensation capacitor.

In the present utility model, the main area pixel 110 and the sub area pixel 120 are charged simultaneously when the thin film transistor 130 is turned on by sharing the thin film transistor 130 with the main area pixel 110 and the sub area pixel 120. The main region pixel electrode 111 of the main region pixel 110 is connected to the source of the thin film transistor 130 through a via 132. The sub-pixel electrode 121 of the sub-pixel 120 is connected to the sub-capacitor electrode 122 and forms a compensation capacitor with the source extension line 131 on the thin film transistor 130, and the gray scale voltages of the main pixel 110 and the sub-pixel 120 are different and different gray scales are displayed under the condition that the main pixel 110 and the sub-pixel 120 input the same data signal at the same time by the compensation capacitor. In this embodiment, in one sub-pixel 100 region, although the main region pixel electrode 111 and the sub-region pixel electrode 121 are disposed, the two pixel electrodes can be driven by one thin film transistor 130, thereby saving the number of thin film transistors 130. Particularly, for the scheme that the main and sub area pixels 120 are respectively charged by using the thin film transistors, the number of the thin film transistors 130 is greatly reduced, and the aperture ratio of the display panel 1 is further improved.

The main area pixels 110 and the sub area pixels 120 are located in the same sub pixel 100, and may be arranged horizontally or vertically. The main area pixel 110 and the sub area pixel 120 in the same sub pixel 100 area have the same color, the sub pixel 100 includes a red sub pixel 100, a green sub pixel 100, a blue sub pixel 100, and the like, and a plurality of sub pixels 100 of the basic color form a pixel unit.

Referring to fig. 3, fig. 3 is a schematic view of a pixel structure of the array substrate of the present utility model, and the array substrate 4 includes a plurality of scan lines 300 and a plurality of data lines 200; two scanning lines 300 are disposed between two adjacent rows of the sub-pixels 100 in the extending direction of the data lines 200, and two columns of the sub-pixels 100 are disposed between two adjacent data lines 200 in the extending direction of the scanning lines 300; in the same row of the sub-pixels 100, the thin film transistors 130 corresponding to adjacent sub-pixels 100 are respectively connected to different scan lines 300; in the same row of the sub-pixels 100, two sub-pixels 100 between two adjacent data lines 200 are respectively in an eight-domain pixel structure, and only two thin film transistors 130 are respectively and correspondingly connected with two sub-pixels 100.

For the display panel 1 of the present embodiment, a display panel 1 of a DRD design is provided, in which the number of data lines 200 is halved and the number of scan lines 300 is doubled. In the case of halving the data line 200, and the two rows of sub-pixels 100 on the left and right sides of one data line 200 need to share one data line 200, the sub-pixels 100 on the left and right sides of one data line 200 are respectively connected to different scan lines 300, and are turned on in different scan periods, so as to receive different data signals. The main area pixel 110 and the sub area pixel 120 and the common thin film transistor 130 of the present utility model are suitable for use in the display panel 1 of the DRD design, and of course, the present utility model includes, but is not limited to, the display panel 1 of the DRD design.

The eight domains refer to the design of the pixel electrode, but the sub-pixel 100 of the sub-pixel electrode 121 is not designed, but the main pixel electrode 111 of the sub-pixel 100 is designed as four domains (4 domains). In this embodiment, after the sub-area pixel electrode 121 is added, the sub-area pixel electrode 121 is also set to four domains, so that the sub-pixel 100 electrically formed by the sub-area pixel electrode 121 and the main area pixel 110 is an eight-domain pixel structure. It can be understood that the conventional DRD design display panel 1 has the advantages of low cost and high transmittance (about 10% higher than 1G1D product), but poor viewing angle, and low acceptance by high-end customers; for the display panel 1 of the DRD design, when the eight Domain scheme is adopted, after 4 domains are changed into 8 domains, the number of TFTs is increased by 2 times, and although the viewing angle is effectively improved, the transmittance loss is about 15% compared with the 1G1D product, so that the transmittance cannot reach the standard. The 8Domain DRD and the compensation capacitor in the scheme are equivalent to 1G1D products in transmittance under the premise of improving the visual angle, so that the method has obvious advantages and high feasibility.

Referring to fig. 4, fig. 4 is a schematic cross-sectional view of an array substrate according to the present utility model, and referring to fig. 1 to 3, the array substrate 4 includes a substrate 10, a first metal layer 11, a second metal layer 12, and a transparent conductive layer 13 stacked, where the first metal layer 11 and the second metal layer 12 are insulated from each other, and the second metal layer 12 and the transparent conductive layer 13 are insulated from each other; the main region pixel electrode 111 and the sub region pixel electrode 121 are formed on the transparent conductive layer 13 in the same layer; the source extension line 131 is formed on the second metal layer 12, the sub-region capacitance electrode 122 is formed on the first metal layer 11, and the sub-region capacitance electrode 122 coincides with the source extension line 131 on the projection of the substrate 10.

The substrate 10 in this embodiment is a glass substrate, which is commonly used as a color film substrate and an array substrate in the display panel 1, the first metal layer 11 is generally used as a layer of metal layer on the bottom of the glass substrate, the gate electrode of the thin film transistor 130, the scan line 300, the common electrode line 133, other signal lines, etc. are formed on the first metal layer 11, the second metal layer 12 is located above the first metal layer 11 and is generally isolated from the first metal layer 11 by a gate insulating layer or a first insulating layer, the source drain electrode of the thin film transistor 130, the data line 200, etc. are generally formed on the second metal layer 12, and the source extension line 131 in this embodiment is formed on the second metal layer 12. The transparent conductive layer 13 is generally formed over the second metal layer 12, and the main region pixel electrode 111, the sub region pixel electrode 121, and the like are generally formed on the transparent conductive layer 13. The transparent conductive layer 13 is typically formed of an indium tin oxide material.

The array substrate 4 further includes a common electrode line 133, the common electrode line 133 is formed on the first metal layer 11 and is disposed around the sub-area capacitor electrode 122, a main storage capacitor is formed between the main area pixel electrode 111 and the common electrode line 133, and a sub-area storage capacitor is formed between the sub-area pixel electrode 121 and the common electrode line 133. The common electrode line 133 is also generally formed on the first metal layer 11 of the array substrate 4.

The secondary region capacitor electrode 122 of the present utility model may be disposed on the first metal layer 11 or the second metal layer 12, and it is understood that the secondary region capacitor electrode 122 is a suspended wiring, and is not similar to the common electrode line 133 or the data line 200, which needs to be connected to a signal.

Specifically, in this embodiment, taking the case that the sub-area capacitor electrode 122 is disposed on the first metal layer 11, the sub-area capacitor electrode 122 is disposed in the area of the sub-area pixel 120 and extends to the area of the main area pixel 110; the source extension line 131 is disposed across the region of the main region pixel 110 and extends to the region of the sub region pixel 120. It should be understood that the length of the sub-region capacitor electrode 122 overlapping the source extension line 131 is related to the magnitude of the compensation capacitor.

Specifically, the widths of the sub-region capacitance electrode 122 and the source extension line 131 are equal, and the sub-region capacitance electrode 122 and the source extension line 131 completely overlap on the projection of the substrate 10. The sub-region capacitor electrode 122 and the source electrode extension line 131 are formed by adopting different metal layers, so that the sub-region capacitor electrode 122 and the source electrode extension line 131 are arranged opposite to each other and have equal widths, and shading treatment is also facilitated for the sub-region capacitor electrode 122 and the source electrode extension line 131.

Specifically, the area of the main area pixel 110 is less than or equal to the area of the sub area pixel 120. In a particular design of the present embodiment, the area of the main area pixel 110 is smaller than the area of the sub area pixel 120, so as to form a display effect with a larger viewing angle.

In an embodiment, the sub-region pixel electrode 121 and the main region pixel electrode 111 are arranged along the direction of the data line 200, and the source extension line 131 is disposed on a central axis of an edge of the sub-region pixel electrode 121 in the extending direction of the scan line 300 on the projection of the substrate 10. In this embodiment, the source extension line 131 is disposed on the central axis of the sub-region pixel electrode 121, and the light shielding layer is not required for shielding light.

In another embodiment, the sub-region pixel electrode 121 and the main region pixel electrode 111 are arranged along the direction of the data line 200, and the source extension line 131 is disposed close to the data line 200 on the projection of the substrate 10. In this embodiment, the source extension line 131 is disposed near the data line 200, so that the light shielding of the source extension line 131 can be achieved by widening the light shielding layer above the data line 200.

Referring to fig. 5, fig. 5 is an equivalent circuit diagram of a pixel driving circuit according to the present utility model, in which Data is a Data line 200, gate is a scan line 300, tft is a thin film transistor 130, main is a main area pixel 110, sub is a sub area pixel 120, clc1 is a main area pixel 110 capacitance formed between a main area pixel electrode 111 and a common electrode, cst is a main area storage capacitance formed between the main area pixel electrode 111 and the common line, CC is a compensation capacitance, clc2 is a sub area pixel 120 capacitance formed between a sub area pixel electrode 121 and the common electrode. According to the voltage division law, the voltage of the main region pixel electrode 111 is Va, the voltage of the sub region pixel electrode 121 is Vb, and vb=va [ CC/(cc+clc2+cst) ], the ratio of Va to Vb can be further adjusted by adjusting the capacitance of CC. Specifically, the gray level of the main area pixel 110 is higher than the gray level of the sub area pixel 120.

Referring to fig. 6, fig. 6 is a schematic diagram of a display device according to the present utility model, and the present utility model also discloses a display device 2, where the display device 2 includes a backlight module 3 and the display panel 1 described above.

It should be noted that, the inventive concept of the present utility model can form a very large number of embodiments, but the application documents are limited in space and cannot be listed one by one, so that on the premise of no conflict, the above-described embodiments or technical features can be arbitrarily combined to form new embodiments, and after the embodiments or technical features are combined, the original technical effects will be enhanced.

The above description of the utility model in connection with specific alternative embodiments is further detailed and it is not intended that the utility model be limited to the specific embodiments disclosed. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the utility model, and these should be considered to be within the scope of the utility model.

Claims (10)

1. The array substrate comprises a plurality of sub-pixels arranged in an array, wherein each sub-pixel comprises a main area pixel and a sub-area pixel, and the array substrate is characterized in that the area corresponding to each sub-pixel further comprises:

a thin film transistor, one side of which is provided with a source extension line extending from a source of the thin film transistor to a region of the sub-region pixel;

a main region pixel electrode arranged in the region of the main region pixel and connected with the source electrode of the thin film transistor through a via hole;

a sub-region pixel electrode disposed within a region of the sub-region pixel; and

the secondary region capacitor electrode is arranged on a layer different from the secondary region pixel electrode and is connected with the secondary region pixel electrode through a via hole, and the secondary region capacitor electrode and the source electrode extension line form a compensation capacitor.

2. The array substrate according to claim 1, wherein the array substrate comprises a substrate, a first metal layer, a second metal layer and a transparent conductive layer which are stacked, wherein the first metal layer and the second metal layer are arranged in an insulating manner, and the second metal layer and the transparent conductive layer are arranged in an insulating manner;

the main area pixel electrode and the secondary area pixel electrode are formed on the transparent conductive layer in the same layer;

the source electrode extension line is formed on the second metal layer, the secondary region capacitance electrode is formed on the first metal layer, and the secondary region capacitance electrode is overlapped with the source electrode extension line on the projection of the substrate.

3. The array substrate of claim 2, wherein the secondary region capacitor electrode is disposed in a region of the secondary region pixel and extends to a region of the primary region pixel;

the source electrode extension line is arranged across the area of the main area pixel and extends to the area of the secondary area pixel;

the area of the main area pixel is smaller than or equal to the area of the secondary area pixel.

4. The array substrate of claim 3, wherein the sub-region capacitor electrode and the source extension line have the same width, and the sub-region capacitor electrode and the source extension line completely overlap each other in a projection of the substrate.

5. The array substrate of claim 3, wherein the array substrate comprises a plurality of scan lines and a plurality of data lines;

the sub-region pixel electrodes and the main region pixel electrodes are arranged along the data line direction,

on the substrate projection, the source extension line is disposed on a central axis of an edge of the sub-region pixel electrode in the extending direction of the scanning line.

6. The array substrate of claim 1, wherein the array substrate comprises a plurality of scan lines and a plurality of data lines; two scanning lines are arranged between two adjacent rows of the sub-pixels in the extending direction of the data lines, and two columns of the sub-pixels are arranged between two adjacent data lines in the extending direction of the scanning lines;

in the same row of the sub-pixels, the thin film transistors corresponding to the adjacent sub-pixels are respectively connected to different scanning lines;

in the same row of the sub-pixels, two sub-pixels between two adjacent data lines are respectively of eight-domain pixel structures, and only two thin film transistors are correspondingly connected with the two sub-pixels respectively.

7. The array substrate of claim 2, further comprising a common electrode line formed on the first metal layer and disposed around the sub-region capacitor electrode, wherein a main storage capacitor is formed between the main region pixel electrode and the common electrode line, and a sub-region storage capacitor is formed between the sub-region pixel electrode and the common electrode line;

the gray scale of the main area pixel is higher than that of the secondary area pixel.

8. The array substrate of claim 3, wherein the array substrate comprises a plurality of scan lines and a plurality of data lines;

the secondary region pixel electrodes and the primary region pixel electrodes are arranged along the data line direction, and the source electrode extension line is arranged close to the data line on the substrate projection.

9. A display panel comprising a counter substrate and an array substrate according to any one of claims 1 to 8, the counter substrate and the array substrate being arranged in a pair.

10. A display device comprising a backlight module and the display panel of claim 9.