KR100675925B1 - Liquid crystal display for diminishing flicker from controlling delay of gate signal - Google Patents

Abstract

The present invention relates to a liquid crystal display device which can reduce flicker by adjusting a delay of a gate driving signal using capacitance of a gate line and a liquid crystal panel.

The liquid crystal display of the present invention includes a gate driving circuit for applying a driving signal to a thin film transistor for driving each pixel electrode through a plurality of gate lines, and a source driving for applying a data signal to the thin film transistor through a plurality of data lines. In driving a liquid crystal display including a circuit, the gate drive signal of the input terminal applied to the unit pixel region is delayed in advance by the storage capacitance formed by the pixel region and the gate line, thereby preventing flicker due to the delay variation of the left and right sides of the panel. Decrease.

Description

LIQUID CRYSTAL DISPLAY FOR DIMINISHING FLICKER FROM CONTROLLING DELAY OF GATE SIGNAL

1 is a schematic diagram showing a liquid crystal panel and a driving circuit of a liquid crystal display device;

2 is an electrical equivalent circuit diagram of a pixel of a thin film transistor liquid crystal display device;

3 is a waveform diagram showing a relationship between a gate driving signal, a data signal, and a gate-on control signal;

4 is a waveform diagram of a gate driving signal and a data signal for a conventional method of driving a liquid crystal display;

5 is a waveform diagram of a gate driving signal and a data signal in a method of driving a liquid crystal display according to an exemplary embodiment of the present invention;

6A and 6B are a planar structural diagram of a liquid crystal panel in a conventional liquid crystal display device;

7A and 7B illustrate a planar structure diagram of a liquid crystal panel in the liquid crystal display according to the exemplary embodiment of the present invention;

8A and 8B illustrate a planar structure diagram of a liquid crystal panel in a liquid crystal display according to another exemplary embodiment of the present invention;

9A is a schematic cross-sectional view of the plan view of FIG. 7B;

FIG. 9B is a schematic cross-sectional view of the plan view of FIG. 8B;

FIG. 10 is a cross-sectional view of a liquid crystal display when delaying a gate driving signal by a storage capacitance between a first gate line and a pixel electrode according to an exemplary embodiment of the present invention; FIG.

FIG. 11 is a cross-sectional view of a liquid crystal display when delaying a gate driving signal by a storage capacitance between a second gate line and a second gate line and a pixel electrode according to another exemplary embodiment of the present disclosure; FIG.

(Name of the code for the main part of the drawing)

Von11: Gate driving signal at input terminal Von12: Gate driving signal at output terminal

Vdata11: data signal of input terminal Vdata12: gate drive signal of output terminal

Vk11: Kickback Voltage at Input Vk12: Kickback Voltage at Output

211, 212, ...: gate pads 221, 222, ...: data pads

210: input terminal 220: output terminal

231 and 233: gate line pixel region portion 232 and 234: gate line transistor portion

241 and 242 repair area 340 and 350 defective area

90: connection portion of the gate line pixel region portion and the gate line transistor portion

Cst1, Cst2: Storage Capacitance Gn-1, Gn, ...: Gate Pad

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor liquid crystal display (TFT-LCD). More particularly, the present invention relates to a flicker phenomenon by delaying a gate signal at an input terminal using a capacitance inside a liquid crystal panel. The present invention relates to a liquid crystal display device which can reduce and improve screen characteristics.

Cathode Ray Tube (CRT) cathode ray tube (CRT), which is the most widely used display device, has been spotlighted as a display device including TV and computer monitor because of its easy color and fast operation speed. However, the cathode ray tube has a disadvantage in that the portability is not only thick because of the structural characteristic of securing a certain distance between the electron gun and the screen, but also because the power consumption is large and the weight is considerably heavy.

In order to overcome the disadvantages of the cathode ray tube as described above, various various display devices have been devised. Among them, the most practical device is a liquid crystal display (LCD).

Although the LCD is darker in screen and somewhat slower in operation than the cathode ray tube, each pixel may be operated according to a signal scanned on a plane without having an electron gun. It can be used as a very thin display device such as a wall-mounted TV. In addition, since the liquid crystal display device is light in weight and consumes considerably less power than the cathode ray tube, it is recognized that the liquid crystal display device is most suitable as a portable display device such as being used as a display of a battery operated notebook computer.

As described above, a liquid crystal display that is in the spotlight as a next generation display device is briefly shown in FIG. 1. Referring to FIG. 1, the liquid crystal display includes a liquid crystal panel 10, a gate driving circuit 15 and a source driving circuit 14 capable of driving the liquid crystal panel 10. The liquid crystal panel 10 includes a plurality of gate lines 12 and a plurality of data lines 11 intersecting in a matrix form on a substrate, and thin film transistors (TFTs) 13 at the intersections thereof. ) And pixels are arranged. In addition, the gate driving circuit 15 sequentially applies a gate signal for turning on the thin film transistor 13 to the gate line 12, and the source driving circuit 14 The data signal is applied to the data line 11 to transmit the data signal to the pixel through the thin film transistor driven by the scan signal.

In the liquid crystal display as described above, all the thin film transistors connected to the gate line 12 are turned on by a gate signal sequentially applied to the gate line 12 of the liquid crystal panel 10 in the gate driving circuit 15. When turned on, the data signal applied to the data line 11 of the liquid crystal panel 10 operates on the principle that the data signal is transferred to the pixel through the source and the drain of the turned-on thin film transistor.

FIG. 2 is an electrical equivalent circuit diagram of a pixel of the thin film transistor liquid crystal display (TFT-LCD) as described above. Referring to FIG. 2, in the thin film transistor liquid crystal display, individual pixels are divided into gate lines Gn-1 and Gn and data lines Dn and Dn-1, and applied to the drain electrodes of the thin film transistor TFT through the data lines. The data signal is charged in the pixel electrode and the storage capacitor (Cst) when the gate signal through the gate line is applied to the gate electrode of the thin film transistor. In the above, the pixel electrode is represented by the liquid crystal capacitor Clc, and the common electrode voltage is represented by Vcom. The voltage of the data signal charged in the pixel electrode is lowered by the parasitic capacitance Cgd between the gate electrode and the drain electrode of the thin film transistor TFT, which is referred to as a kick back (Vk) voltage.

The thin film transistors connected to the respective pixel electrodes on the liquid crystal panel are not turned on or off independently, but all the thin film transistors connected to one gate line are turned on or off at the same time so that the data signal is applied to the pixel electrodes. Control what is applied. As described above, a data signal is applied to each gate line. This period is referred to as a horizontal line period, and a voltage in a saturation region must be applied to the gate line to turn on the thin film transistor. The gate signal becomes the turn-on voltage of the thin film transistor, and has a value of about 16 volts or more, and is generally referred to as a gate driving signal Von.

The gate driving signal as described above is distorted by the self-resistance and parasitic capacitance of the gate line, thereby distorting the data signal charged in the pixel electrode. Thus, a gate on enable signal (OE) controlling the application of the gate driving signal (OE) ) To reduce the width of the gate driving voltage and apply it to the pixel electrode.

3 is a waveform diagram illustrating a relationship between the gate driving voltage Von, the data voltage Vdata, and the gate-on control signal OE for one pixel. 2 and 3, when the gate driving voltage Von is applied, the thin film transistor TFT is turned on so that the data voltage is applied to the liquid crystal capacitor Clc, the storage capacitor Cst, and the parasitic capacitor Cgd. Is charged. The gate driving voltage Von is turned off by the gate on control signal OE and remains on-state only for a period shorter than the horizontal line period 1H. At this time, when the gate driving voltage Von is turned off, the applied data voltage is maintained at the pixel electrode at a value distorted by the kickback voltage due to the parasitic capacitor Cgd.

In order to prevent deterioration of the liquid crystal, the data signal applied to the pixel electrode is alternately applied with the positive and negative voltages with respect to the common electrode voltage Vcom. Therefore, the voltage charged in each pixel is applied with the polarity changed every frame. At this time, the effective value of the voltage actually applied to the liquid crystal is determined by the area between the data voltage and the common electrode voltage Vcom. Therefore, a constant voltage can be applied to the pixel electrode only when the area around the common voltage is symmetrical. have. However, since the kickback voltage Vk always acts in the direction of pulling down the data signal regardless of the polarity of the data signal, the positive data signal and the negative data signal have different values. This eventually causes the flicker to flicker.

The above-mentioned flicker phenomenon has various causes, among which flicker occurs at the left and right sides of the panel according to the delay of the gate driving signal applied to the gate line at the input terminal and the output terminal, and the leakage current of the thin film transistor. ) Can be classified into a flicker phenomenon occurring in the entire panel and a flicker phenomenon occurring in the entire panel due to leakage of liquid crystal.

In particular, in order to solve the above-described flicker phenomenon on the left and right of the panel, the pixel electrode is reduced by adjusting the common electrode voltage level so that the positive data signal and the negative data signal are symmetric, thereby reducing the flicker caused by the kickback voltage. Since the dielectric constant of the liquid crystal to be changed according to the applied voltage has a disadvantage that it is difficult to accurately compensate the kickback voltage.

As another method, there is a conventional method of improving the flicker phenomenon by delaying the input terminal of the gate driving signal in advance. In this method, the gate driving signal, which is already made at the module part, is applied to the liquid crystal panel in order to delay the input terminal in advance. do.

However, since the above method requires a separate circuit for generating the gate drive signal in order to delay the input terminal of the gate drive signal, it may not coincide with the operation inside the panel. Has the disadvantage of increasing cost.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a liquid crystal display that can reduce flicker by forming a storage capacitance between the gate line and the pixel electrode and giving a delay at an input terminal of the gate driving signal in advance. There is this.

In order to achieve the above object, the liquid crystal display device driving method of the present invention is a gate driving circuit for driving a plurality of thin film transistors through a plurality of gate lines, and applying a data signal to the thin film transistor through a plurality of data lines. In driving a liquid crystal display including a source driving circuit, the gate driving signal of the input terminal is delayed and applied in advance to reduce flicker due to left and right variations of the panel and to improve screen quality.

In addition, the liquid crystal display of the present invention includes a gate driving circuit for driving a plurality of thin film transistors through a plurality of gate lines, and a source driving circuit for applying a data signal to the thin film transistor through a plurality of data lines. An apparatus comprising: a gate line pixel region portion passing through a unit pixel region arranged in a row from a gate pad to which a gate signal is applied, and a gate line connected to a gate electrode of a thin film transistor at an end of the gate line pixel region portion opposite the gate pad; The gate line pixel region and the gate line transistor are connected to each other at opposite sides of the gate pad.

The plurality of gate pads may be provided on the left side or the right side of the liquid crystal panel.

The gate line pixel region may be configured to form a storage capacitance between the pixel electrode and the pixel electrode in order to delay the gate driving signal at an input terminal.

The gate line pixel region portion and the gate line transistor portion may be configured such that storage capacitances are respectively formed between the pixel electrode and the pixel electrode in order to delay the gate driving signal at an input terminal.

The gate line pixel region portion and the gate line transistor portion may include a repair region capable of shorting the gate line pixel region portion and the gate line transistor portion so as to repair defective gate lines and data lines.

The repair region may be configured such that an end portion of the gate line transistor portion overlaps the gate line pixel region portion in an area adjacent to the gate pad.

 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention causes the gate driving signal to be delayed from the input terminal, thereby reducing the flicker phenomenon caused by the left and right deviation of the liquid crystal panel.

4 is a waveform diagram of a gate driving signal and a data signal of a conventional method of driving a liquid crystal display, and FIG. 5 is a gate driving signal and data of a driving method of a liquid crystal display according to an exemplary embodiment of the present invention. The waveform diagram of the signal is shown.

First, referring to FIG. 4, a conventional driving method of the liquid crystal display device is applied as a pulse signal having a horizontal line period 1H. The gate driving signal Von1 is applied to the low level Vgl in the off state and the on state. It has a high level (Vgh).

After the gate driving signal Von1 transitions from the low level Vgl to the high level Vgh and the thin film transistor is turned on, after the GOE time for the data signal Vdata1 to be applied, the data signal Vdata1 Is applied through the data line.

When the data signal Vdata1 is applied, the liquid crystal capacitor, the storage capacitor, and the parasitic capacitor are charged. In order to prevent distortion of the data signal Vdata1, the time t1 for charging the liquid crystal capacitor, the storage capacitor, and the parasitic capacitor is increased. After that, the gate driving signal Von1 is turned off to the low level Vgl.

At this time, due to the parasitic capacitance between the gate electrode and the drain electrode of the thin film transistor, the kickback voltages Vk1 and Vk2 are distorted and retained in the pixel electrode, and the kickback voltage Vk1 of the first gate close to the gate driving circuit, In the gate driving circuit, the kickback voltage Vk2 at the far end of the gate appears different. That is, the data signal Vdata1 of the input terminal and the data signal Vdata2 of the output terminal are different from each other due to the delay difference between the gate driving signal Von1 appearing in the input terminal and the gate driving signal Von2 appearing in the output terminal.

However, the flicker phenomenon that the screen shakes is larger as the difference between the kickback voltage Vk1 of the gate input terminal and the kickback voltage Vk2 of the gate output terminal and the greater the absolute value of each kickback voltage Vk1 and Vk2.

In addition, in the driving method of FIG. 4, the actual charging time is performed for a time t1 excluding the GOE time in the horizontal line period 1H.

On the other hand, the driving method of the liquid crystal display of the present invention illustrated in FIG. 5 will be described with reference to FIG. 4. In FIG. 5, a case in which the horizontal display period 1H is the same as the conventional driving method illustrated in FIG. 4 will be described as an example.

When the gate driving signal Von11 is transitioned from the low level Vgl to the high level Vgh, the thin film transistor is turned on, and after the GOE time, the data signals Vdata11 and Vdata12 are applied through the data line. At this time, Vdata11 is a waveform of the data signal appearing at the gate input terminal, and Vdata12 is a waveform of the data signal appearing at the gate output terminal.

At this time, the gate driving signal Von11 is delayed and applied from the gate input terminal, thereby reducing flicker by reducing the deviation between the input terminal and the output terminal in the liquid crystal panel.

That is, in the case of applying the gate driving signal close to the square wave without delay at the input terminal, if the delay degree of the gate driving signal appearing at the output terminal is 10, the input terminal delays about 5 and applies the gate driving signal in advance. The gate driving signal is delayed more than 10, but about 11 to 13, less than the delay at the input stage. Accordingly, as shown in FIG. 5, when the gate driving signal Von11 delayed at the input terminal is applied, the deviation occurring between the gate driving signal Von12 at the output terminal is reduced, thereby reducing the flicker phenomenon. .

As a result, the delay level of the gate driving signal Von11 and the output gate driving signal Von12 delayed at the input terminal decreases, so that the magnitudes of the kickback voltages Vk11 and Vk12 appearing at the data signals Vdata11 and Vdata12 at the input terminal and the output terminal are reduced. Is reduced. In particular, the flicker phenomenon is proportional to the difference between the kickback voltages Vk11 and Vk12 between the first and the gate ends of the gate. Since the absolute value of the kickback voltages Vk11 and Vk12 decreases, the flicker voltage and the kickback voltage Vk11 of the first gate are eventually reduced. The difference in the kickback voltage Vk12 at the gate end also becomes small, thereby reducing the flicker phenomenon.

6A and 6B show a structural diagram of a conventional liquid crystal panel using a single gate line to drive thin film transistors arranged in a line. First, referring to FIG. 6A, the conventional liquid crystal panel 100 applies a plurality of gate pads 111, 112,..., For applying a gate driving signal through a gate line, and a data signal through a data line. Data pads 121, 122, ..., and a display area for displaying a screen according to a data signal.

As shown in FIG. 6B, the liquid crystal panel 100 includes a plurality of thin film transistors and a unit pixel region to receive gate driving signals from a plurality of gate pads Gn, Gn + 1,... At this time, the delay of the gate driving signal hardly occurs at the input terminal 110 adjacent to the gate pad in the unit pixel area, and the gate driving signal is delayed a lot during the gate line at the output terminal 120 opposite to the gate pad. In this case, a deviation occurs between the input terminal 110 and the output terminal 120, and thus the left and right flickering of the panel appears.

7A and 7B illustrate a planar structure diagram of a liquid crystal panel in the liquid crystal display according to the exemplary embodiment of the present invention. As shown in FIG. 6A, the liquid crystal panel 200 of FIG. 7A illustrates a case in which gate pads 211, 212,... Are formed on the left side of the panel.

Referring to FIG. 7B, the liquid crystal display of the present invention may include gate line pixel region portions 231, 233,... Which extend from the input terminal 210 of the gate driving signal to the opposite output terminal 220 so as to overlap with the unit pixel region arranged in a row. And gate line transistor portions 232, 234 connected to gate electrodes of the plurality of thin film transistors at ends of the gate line pixel region portions 231, 233,... ...) In this case, the gate line pixel region portions 231, 233, ..., and the gate line transistor portions 232, 234, ... are connected to each other at the output terminal 220 with respect to the unit pixel region formed in a line, respectively. .

The ends of the gate line transistors 232, 234,..., And the gate line pixel region parts 231, 233, ...) are formed at the gate pads Gn-1, Gn,. The regions 241, 242,..., Which are overlapped with each other, are parts for performing a repair when a failure occurs in the gate line and the data line, respectively.

As described above, the reason for forming two rows of gate lines in a unit pixel area of a row is that a storage capacitance is generated between the pixel electrode and the gate line pixel area part, thereby delaying the gate driving signal from the input terminal 210. For sake.

FIG. 9A is a schematic cross-sectional view of the plan view of FIG. 7B. Referring to FIG. 9A, a gate line pixel region 92 extends from a gate pad to an opposite output terminal through an input terminal, and the gate line transistor 93 is again connected at the end of the gate line pixel region 92. The gate pads extend through the gate electrodes 91 of the thin film transistors. The storage capacitance is generated between the gate line pixel region 92 and the pixel electrode, and is thus delayed and transferred.

8A and 8B illustrate a planar structure diagram of a liquid crystal panel when the gate pad is provided on the right side of the screen in the liquid crystal display according to another exemplary embodiment of the present invention. Referring to FIG. 8A, the liquid crystal panel 300 includes a plurality of gate pads 311, 312,..., And a plurality of data pads 321, 322,..., As shown in FIG. 7A. And a display area, only gate pads 311, 312, ... are provided on the right side of the panel.

Therefore, the plan view shown in FIG. 8B has the same configuration as that of FIG. 7B. Since only the gate pads Gn-1, Gn, ... are located at the right side, the gate driving signals are each unit pixel region. An input terminal 320 is applied to the right side of the panel and the output terminal 310 is formed on the left side of the panel.

In this case as well, the gate line pixel region portion is formed from the input end to the output end so as to overlap each unit pixel electrode, and the gate line transistor portion is connected to each gate electrode of the thin film transistor from the end of the gate line pixel region portion, and then to the input end again. Is formed. When a failure occurs when the gate line is opened 340 or the gate line and the data line are shorted 350, the gate line transistor unit overlaps with the gate line pixel region in the vicinity of the gate pad to repair the defect. Form a repair area.

Therefore, when the failure occurs in the gate line or the data line, the repair region may be shortened to repair the defective pixel.

8B is a cross-sectional view of the plane structure shown in FIG. 9B. Referring to FIG. 9B, the gate line pixel region portion 95 extends from the gate pad to the opposite side, and the gate line transistor portion 96 is connected to the end portion 90 of the gate line pixel region portion 95. It is connected to the gate electrode 94 of and back to the vicinity of the gate pad.

Therefore, when the gate driving signal is applied through the gate pad, the gate driving signal of the input terminal is delayed by the storage capacitance between the gate line pixel region 95 and the pixel electrode, and thus appears between the gate driving signal of the output terminal. Deviation is reduced to reduce flicker.

10 and 11 illustrate a case where a storage capacitance is formed between the gate line pixel region part and the pixel electrode according to the exemplary embodiment of the present invention.

First, referring to FIG. 10, since the gate line pixel region portion 101 is formed to overlap the pixel electrode, and the gate line transistor portion 102 is formed so as not to overlap the pixel electrode, the gate line pixel region portion ( The gate driving signal is delayed by the storage capacitance Cst1 formed between the 101 and the pixel electrode.

On the other hand, as shown in Fig. 11, the gate line pixel region 103 and the gate line transistor 104 are both overlapped with the pixel electrode, so that the gate line pixel region 103 and the gate line transistor 103, 104 and Both storage capacitances Cst1 and Cst2 are generated between the pixel electrodes, thereby increasing the degree to which the gate driving signal is delayed.

As described above in detail, according to the liquid crystal display of the present invention, by delaying the gate driving signal at the input terminal, the delay deviation between the input terminal and the output terminal is reduced, thereby reducing the kickback voltage of the data signal, thereby reducing the left and right sides of the liquid crystal panel. Flicker can be reduced. Therefore, it is possible to improve the screen quality of a liquid crystal display device.

Further, according to the liquid crystal display of the present invention, the gate line pixel region portion and the gate line transistor portion are formed so as to overlap the pixel electrode, and the gate driving signal is delayed at the input terminal, so that the left and right sides of the liquid crystal panel are not generated without a separate gate driving signal generation circuit. It is possible to reduce the flicker phenomenon and improve the quality of the screen.

In addition, when a defect occurs in the gate line or the data line, it can be easily repaired, and since the storage capacitance is formed in a portion that causes a delay of the gate driving signal, uniformity of the entire panel can be ensured. have.

Hereinafter, the present invention can be carried out in various modifications without departing from the gist of the invention.

Claims (7)

delete A gate driving circuit applying a gate driving signal to each of the thin film transistors for driving the plurality of pixel electrodes through the plurality of gate lines, and a source driving circuit applying the data signal to the thin film transistor through the plurality of data lines; In the liquid crystal display device, The gate line is, A gate line pixel region portion passing through the unit pixel electrodes arranged in a row from the gate pad to which the gate driving signal is applied to the opposite side; And a gate line transistor portion extending from an end of the gate line pixel region portion opposite to the gate pad to the gate pad and connected to the gate electrode of each thin film transistor. The method of claim 2, wherein the plurality of gate pads The liquid crystal display device which is provided in the left part or the right part of a liquid crystal panel. The display device of claim 2, wherein the gate line pixel region is formed. And a pixel electrode overlapping the pixel electrode such that a storage capacitance is generated between the pixel electrodes. The gate line pixel region and gate line transistor of claim 2, And overlapping pixel electrodes so that storage capacitance is formed between the pixel electrodes, respectively. The gate line pixel region and gate line transistor of claim 2, And a repair region capable of shorting the gate line pixel region portion and the gate line transistor portion so as to repair defective gate lines and data lines. The method of claim 6, wherein the repair region And the end portion of the gate line transistor portion overlaps the gate line pixel region portion in an area adjacent to the gate pad.

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