KR101341781B1 - Liquid Crystal Display Device - Google Patents

Abstract

The present invention relates to a liquid crystal display device by dividing the storage electrode to reduce the load resistance, thereby reducing the variation of the common voltage supplied to the storage electrode according to the position of the display panel to increase the display quality.

The liquid crystal display according to the present invention defines a liquid crystal cell by crossing a plurality of gate lines and a plurality of data lines, and forming a common electrode constituting the liquid crystal cell together with a pixel electrode, and forming an equipotential with the common electrode. A liquid crystal display panel having a plurality of storage electrodes separated from each other to form a storage capacitor together with the pixel electrode; And an adjusting unit for independently adjusting each common voltage supplied to the separated storage electrodes.

Description

[0001] The present invention relates to a liquid crystal display device,

1 is a view showing a liquid crystal cell included in a conventional liquid crystal display panel.

2 is a block diagram of a liquid crystal display device according to an exemplary embodiment of the present invention.

FIG. 3 is an enlarged view of a portion “P” of the liquid crystal display panel of FIG. 2.

4 is a cross-sectional view taken along line II ′ of FIG. 3.

FIG. 5 is a cross-sectional view of FIG. 3 taken along II-II '.

6A and 6B are circuit diagrams illustrating the first and second adjustment units of FIG. 2, respectively.

       Description of the Related Art

10,140: TCP 20: liquid crystal display panel

60: data PCB 80: data driver IC

120: gate driver IC 150: power supply

160: first adjusting unit 170: second adjusting unit

180: timing control unit 200: LOG signal line

Es1: first storage electrode Es2: second storage electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device which divides the storage electrode to reduce the load resistance, thereby reducing the variation of the common voltage supplied to the storage electrode according to the position of the display panel to increase the display quality. .

In today's information society, display elements are more important than ever as visual information transfer media. Cathode Ray Tube (CRT) or cathode ray tube, which is currently mainstream, has a problem in weight and volume. Many types of flat panel displays capable of overcoming the limitations of the cathode ray tube have been developed.

The flat panel display device includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an electroluminescence (EL) Most of these are commercialized and commercially available.

Liquid crystal display devices can meet the trend of light and small size of electronic products and have improved mass productivity and are rapidly replacing cathode ray tubes in many applications.

In the liquid crystal display panel of the liquid crystal display device, as shown in FIG. 1, the gate line GL and the data line DL intersect each other, and the liquid crystal cell Clc is disposed at the intersection of the gate line GL and the data line GL. A thin film transistor (TFT) for driving is formed. The thin film transistor TFT supplies the data voltage Vd supplied through the data line to the pixel electrode Ep of the liquid crystal cell Clc in response to a scan signal supplied through the gate line GL. To this end, the gate electrode of the thin film transistor TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode is connected to the pixel electrode of the liquid crystal cell Clc. The liquid crystal cell Clc is charged with a potential difference between the data voltage Vd supplied to the pixel electrode Ep and the common voltage Vcom supplied to the common electrode Ec, and the liquid crystal molecules are charged by an electric field formed by the potential difference. As the arrangement changes, it controls the amount of light transmitted or blocks the light. The common electrode Ec is formed on the upper substrate or the lower substrate of the liquid crystal display according to a method of applying an electric field to the liquid crystal cell Clc, and the liquid crystal cell Clc is disposed between the storage electrode Es and the pixel electrode Ep. A storage capacitor Cst is formed to maintain the charging voltage of the battery. The storage electrode Es used as the lower electrode of the storage capacitor is formed separately and connected to the common electrode Ec. The storage electrodes Es are connected to one another on the lower substrate.

In order to prevent deterioration of the liquid crystal cell Clc, the liquid crystal display device is driven in an inversion method in which the polarity of the data voltage Vd is inverted at regular intervals based on the common voltage Vcom. Inversion methods include a dot inversion method, a line inversion method, a column inversion method, and a frame inversion method.

The effective value of the voltage applied to the liquid crystal cell Clc is determined by the degree of the data voltage (pixel voltage) applied to the pixel electrode and the common voltage applied to the common electrode. When the liquid crystal display device is driven in an inversion method, the common voltage is applied. It is necessary to adjust the level of the common voltage so that the pixel voltage around the symmetry is symmetrical. For this purpose, a constant common voltage in which the pixel voltage is symmetrical is applied to the common electrode. This is because when the pixel voltage applied to the pixel electrode centered on the common voltage is not symmetrical, the amount of pixel voltage charged in the liquid crystal cell varies from frame to frame and the screen flickers when the pixel voltage is reversed. This is because flicker occurs.

However, since the storage electrodes are connected to one lower substrate on the lower substrate, the load resistance of the storage electrodes varies according to the display positions of the liquid crystal display panel, thereby increasing the variation of the common voltage for each display position. Accordingly, in the conventional liquid crystal display device, the common voltage is not constantly supplied to the storage electrode of the liquid crystal display panel, thereby increasing the flicker, such as the screen shaking by the display position, thereby degrading the display quality.

Accordingly, an object of the present invention is to provide a liquid crystal display device by dividing the storage electrode to reduce the load resistance, thereby reducing the variation of the common voltage supplied to the storage electrode according to the position of the display panel to increase the display quality.

In order to achieve the above object, a liquid crystal display according to an exemplary embodiment of the present invention defines a liquid crystal cell by crossing a plurality of gate lines and a plurality of data lines, and a common electrode constituting the liquid crystal cell together with a pixel electrode. A liquid crystal display panel forming an equipotential with the common electrode and having a plurality of storage electrodes separated into two or more and constituting a storage capacitor together with the pixel electrode; And an adjusting unit for independently adjusting each common voltage supplied to the separated storage electrodes.

The storage electrode may include a first storage electrode on a left half of the liquid crystal display panel; And a second storage electrode separated from the first storage electrode and disposed on the right half of the liquid crystal display panel.

The adjusting unit may include a first adjusting unit for adjusting a first common voltage supplied to the first storage electrode; And a second adjuster configured to be independent of the first adjuster and to adjust a second common voltage supplied to the second storage electrode.

The liquid crystal display panel may include a first substrate on which the common electrode is formed; And a second substrate on which the storage electrode is formed.

The liquid crystal display panel further includes a conductive ball formed between the first substrate and the second substrate to electrically connect the common electrode and the storage electrode.

Each of the adjusting units includes a variable resistor.

The storage electrode is formed of the same metal as the gate line.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 to 6B.

2 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal display panel 20 in which liquid crystal cells Clc are arranged in a matrix, and data lines DL of the liquid crystal display panel 20. A data driver IC 80 for supplying an analog data voltage to the gate driver, a gate driver IC 120 for supplying a scan signal to the gate lines GL of the liquid crystal display panel 20, and a data driver IC 80. ) And a data PCB 60 to which the timing controller 180, the power supply unit 150, and the first and second adjustment units 160 and 170 are mounted.

The thin film transistor TFT for driving the liquid crystal cell Clc at the intersection of the gate line GL and the data line DL and crossing the gate line GL and the data line GL in the liquid crystal display panel 20. ) Is formed. The thin film transistor TFT supplies a data voltage supplied through the data line DL to the pixel electrode Ep of the liquid crystal cell Clc in response to a scan signal supplied through the gate line GL. To this end, the gate electrode of the thin film transistor TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode is connected to the pixel electrode of the liquid crystal cell Clc. The liquid crystal cell Clc is charged with a potential difference between the data voltage supplied to the pixel electrode Ep and the common voltage Vcom supplied to the common electrode Ec, and the arrangement of the liquid crystal molecules is changed by an electric field formed by the potential difference. The amount of light transmitted is controlled or the light is blocked. The common electrode Ec is formed on the upper substrate to apply a vertical electric field to the liquid crystal cell Clc and to maintain the charging voltage of the liquid crystal cell Clc between the storage electrodes Es1 and Es2 and the pixel electrode Ep. The storage capacitor Cst is formed. The storage electrodes Es1 and Es2 used as the lower electrodes of the storage capacitor are separately formed and connected to the common electrode Ec of the upper substrate through a conductive ball (not shown). The storage electrodes Es are electrically divided into two based on the dotted line “K” on the lower substrate. That is, the first storage electrode Es1 is formed to be electrically connected to an area “A”, which is the left side of the lower substrate, and the second storage electrode Es2 is electrically connected to an area “B”, which is the right side of the lower substrate. It is formed to be connected.

The data driver IC 80 is mounted on a tape carrier package 10 (TCP) and connected to the liquid crystal display panel 20 by a tape automated bonding (TAB) method. The data driver IC 80 is connected in series via signal lines mounted on the data PCB 60 to use data control signals from the timing controller 180 and digital video data and drive voltages from the power supply unit 150. The data voltage is supplied to the data line DL of the liquid crystal display panel 20.

The gate driver IC 120 is mounted on the TCP 140 and connected to the liquid crystal display panel 20 in a TAB manner. The gate driver IC 120 is connected in series through line on glass (LOG) signal lines 200 to receive the gate control signal from the timing controller 180 and the driving voltages from the power supply unit 150. The scan signal is supplied to the gate line GL of the liquid crystal display panel 20. The gate driver IC 120 may be mounted on the liquid crystal panel in a chip on glass (COG) manner.

The timing controller 180 rearranges input digital video data supplied from the outside to the liquid crystal display panel 20 and supplies the input digital video data to the data driver IC 80. Also, the timing controller 180 controls the operation timing of the gate control signal and the data driver IC 80 to control the operation timing of the gate driver IC 120 using the horizontal / vertical synchronization signal and the dot clock signal. Generates a data control signal. Here, the gate control signal includes a gate start pulse GSP and a gate output enable signal GOE, and the data control signal includes a source shift clock SSC, a source start pulse SSP, and a source output enable signal SOE) and the like.

The power supply unit 30 generates an IC digital driving voltage, an IC analog driving voltage, a gate-on voltage, a gate-off voltage, and the like using the input driving voltage. The power supply unit 30 converts the IC digital driving voltage to the timing control unit 180 and the data driver IC 80, the IC analog driving voltage to the data driver IC 80, and the gate-on voltage and gate-off voltage to the gate driver IC. Supply to 120. In addition, the power supply unit 30 generates a common voltage Vcom which is a reference when driving the liquid crystal cell Clc of the liquid crystal display panel 20 and supplies it to the common electrode Ec of the upper substrate.

The first and second adjusters 160 and 170 are used to adjust the level of the common voltage Vcom supplied to the common electrode Ec, and generally include a variable resistor. The user adjusts the level of the common voltage supplied to the first storage electrode Es1 connected to the common electrode Ec by adjusting the first adjuster 160. In addition, the user adjusts the second adjuster 170 to adjust the level of the common voltage supplied to the second storage electrode Es2 connected to the common electrode Ec. This will be described later with reference to FIGS. 6A and 6B.

The data PCB 60 is electrically connected to the data driver IC 80 in a TAB manner and mounts the timing controller 180, the power supply unit 150, and the first and second adjustment units 160 and 170.

FIG. 3 is an enlarged view of a portion "P" of the liquid crystal display panel of FIG. 2.

Referring to FIG. 3, a lower substrate of a liquid crystal display panel according to an exemplary embodiment of the present invention may include a thin film transistor TFT formed at an intersection of a gate line GL and a data line DL, and a thin film transistor TFT. The pixel electrode 28 connected to the drain electrode 26 and the first and second storage electrodes Es1 and Es2 partially overlapped with the pixel electrode 28 are provided.

The thin film transistor TFT is connected to the pixel electrode 28 through the gate electrode 22 connected to the gate line GL, the source electrode 24 connected to the data line DL, and the contact hole 27. A drain electrode 26 is provided. Between the gate electrode 22 and the source / drain electrodes 24 and 26, a gate insulating film 107 for insulation thereof and an active layer and an ohmic contact layer for forming a conductive channel according to a scan signal are interposed. The thin film transistor TFT selectively supplies the data voltage from the data line DL to the pixel electrode 28 in response to a scan signal from the gate line GL.

The pixel electrode 28 is positioned in a liquid crystal cell region partitioned by the gate line GL and the data line DL, and is made of a transparent conductive material having high light transmittance. The pixel electrode 28 is connected to the drain electrode 26 through the contact hole 27 to receive a data voltage supplied through the thin film transistor TFT to generate a common voltage and a potential difference applied to the upper substrate. Do it.

The first storage electrode Es1 is formed to overlap a portion of each pixel electrode 28, and is electrically connected to the first storage electrode Es1 in an area “A” on the left side of the lower substrate. The first storage electrode Es1 is connected to the common electrode of the upper substrate through a conductive ball to receive a common voltage. The first storage electrode Es1 becomes a lower electrode of the first storage capacitor. The first storage capacitor charges the data voltage during the scan period in which the scan signal is generated with the gate-on voltage using the pixel electrode 28 as the upper electrode, and the data during the non-scan period in which the scan signal is generated with the gate-off voltage. The discharge of the voltage serves to prevent the voltage variation of the pixel electrode 28.

The second storage electrode Es2 is formed to overlap a portion of each pixel electrode 28, and is electrically connected to each other in a region “B” on the left side of the lower substrate. The second storage electrode Es2 is connected to the common electrode of the upper substrate through a conductive ball to receive a common voltage. The second storage electrode Es2 becomes a lower electrode of the second storage capacitor. The second storage capacitor charges the data voltage during the scan period in which the scan signal is generated with the gate-on voltage and uses the pixel electrode 28 as the upper electrode, and the data during the non-scan period in which the scan signal is generated with the gate-off voltage. The discharge of the voltage serves to prevent the voltage variation of the pixel electrode 28.

FIG. 4 is a cross-sectional view of FIG. 3 taken along line II-II ', and FIG. 5 is a cross-sectional view of FIG. 3 taken along line II-II'.

As shown in FIGS. 4 and 5, the first and second storage electrodes Es1 and Es2 according to the embodiment of the present invention are electrically insulated based on the “K” line of FIG. Are formed on the left and right sides (A, B). This reduces the load resistance of the storage electrode by half compared to the conventional electrically connected storage electrodes, thereby facilitating adjustment of the common voltage and reducing the variation of the common voltage for each display position.

Referring to FIG. 4, after the deposition of aluminum (Al) or copper (Cu) on the lower substrate 36 by a sputtering method or the like, the first and second storage electrodes Es1 and Es2 are patterned. These are formed spaced apart from each other at regular intervals. Gate insulating layers 34 are formed on the first and second storage electrodes Es1 and Es2. The gate insulating layer 34 is formed by entirely depositing an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) by PECVD (Plasma Enhanced Chemical Vapor Deposition). The data line DL is formed on the gate insulating layer 34. The data line DL is formed by depositing aluminum (Al) or copper (Cu) or the like by a deposition method such as sputtering and patterning the same. The passivation layer 32 is formed on the data line DL. The passivation layer 32 is formed by coating an organic insulating material such as acrylic organic compound, Teflon, etc. by spin coating to cover the data line DL. The pixel electrode 28 is formed on the passivation layer 32. The pixel electrode 28 is formed by depositing any one of ITO, IZO and ITZO, which are transparent conductive materials, and patterning the same.

Referring to FIG. 5, the second storage electrode Es2 is formed by depositing aluminum (Al), copper (Cu), or the like on the lower substrate 36 by a deposition method such as sputtering. The gate insulating layer 34 is formed on the second storage electrode Es2. The gate insulating layer 34 is formed by entirely depositing an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) by PECVD (Plasma Enhanced Chemical Vapor Deposition). The data line DL is formed on the gate insulating layer 34. The data line DL is formed by depositing aluminum (Al) or copper (Cu) or the like by a deposition method such as sputtering and patterning the same. The passivation layer 32 is formed on the data line DL. The passivation layer 32 is formed by coating an organic insulating material such as acrylic organic compound, Teflon, etc. by spin coating to cover the data line DL. The pixel electrode 28 is formed on the passivation layer 32. The pixel electrode 28 is formed by depositing any one of ITO, IZO and ITZO, which are transparent conductive materials, and patterning the same.

6A and 6B are circuit diagrams illustrating first and second adjustment units of FIG. 2, respectively.

6A shows the first adjusting unit 160. Referring to FIG. 6A, the first variable resistor Rf1 of the first adjusting unit 160 changes the level of the first reference voltage Vref1 supplied to the non-inverting terminal (+) of the first op amp 162. Play a role. The first common voltage Vcom1 includes the first reference voltage Vref1 of the non-inverting terminal (+) and the input voltage Vi of the inverting terminal (−) determined by the first variable resistor Rf1. Generated by inverted amplification through 162 and then supplied to the "A" region of the lower substrate.

6B shows the second adjustment unit 170. Referring to FIG. 6B, the second variable resistor Rf2 of the second adjusting unit 170 may change the level of the second reference voltage Vref2 supplied to the non-inverting terminal (+) of the second op amp 172. Play a role. The second common voltage Vcom2 includes the second reference voltage Vref2 of the non-inverting terminal (+) and the input voltage Vi of the inverting terminal (−) determined by the second variable resistor Rf2. Generated by inverted amplification through 172 and then supplied to the "B" region of the lower substrate.

The first and second storage electrodes to which the first and second common voltages Vcom1 and Vcom2 are supplied, respectively, are electrically separated from each other, and the load resistance is reduced by half, thereby greatly reducing the variation of the common voltage for each display position in the liquid crystal display panel. As a result, the common voltage can be easily adjusted.

As described above, the liquid crystal display according to the present invention can reduce the load resistance by dividing the storage electrode, thereby reducing the variation of the common voltage supplied to the storage electrode according to the position of the liquid crystal display panel, thereby improving display quality.

In addition, the liquid crystal display according to the present invention can easily adjust the common voltage by dividing the storage electrodes by dividing the storage electrodes and can greatly reduce the time required for the common voltage adjustment.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. For example, the embodiment of the present invention is described by dividing the storage electrode into two. However, since the technical idea of the present invention is to divide the storage electrode to reduce the load resistance, the number of storage electrodes may be two or more. Do. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (7)

A plurality of gate lines and a plurality of data lines intersect to define a liquid crystal cell. The common electrode constituting the liquid crystal cell together with the pixel electrode and the common electrode forming the equipotential are separated into two or more and are stored together with the pixel electrode. A liquid crystal display panel having a plurality of storage electrodes constituting a capacitor; And And an adjusting unit for independently adjusting each common voltage supplied to the separated storage electrodes. The method of claim 1, The storage electrode, A first storage electrode on the left half of the liquid crystal display panel; And And a second storage electrode separated from the first storage electrode and disposed on a right side of the liquid crystal display panel. The method of claim 2, Wherein, A first adjusting unit for adjusting a first common voltage supplied to the first storage electrode; And And a second adjuster configured to be independent of the first adjuster and to adjust a second common voltage supplied to the second storage electrode. The method of claim 1, The liquid crystal display panel, A first substrate on which the common electrode is formed; And And a second substrate having the storage electrode formed thereon. 5. The method of claim 4, The liquid crystal display panel, And a conductive ball formed between the first substrate and the second substrate to electrically connect the common electrode and the storage electrode. The method of claim 3, wherein And each of the adjusting units includes a variable resistor. The method of claim 1, And the storage electrode is formed of the same metal as the gate line.

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