WO2016106879A1

WO2016106879A1 - Array substrate and display device

Info

Publication number: WO2016106879A1
Application number: PCT/CN2015/071044
Authority: WO
Inventors: 衣志光
Original assignee: 深圳市华星光电技术有限公司
Priority date: 2014-12-31
Filing date: 2015-01-19
Publication date: 2016-07-07
Also published as: CN104464680A; CN104464680B

Abstract

Disclosed are an array substrate and a display device, which relate to the technical field of display and can alleviate the phenomenon of inconsistency in the light outgoing amount of sub-pixel units (1, 2) in the same row. The array substrate comprises a plurality of sub-pixel units (1, 2) that are arranged in an array mode and a gate line driver arranged on one side of the array substrate. The sub-pixel units (1, 2) are correspondingly provided with pixel electrodes and common electrode lines, and the pixel electrodes and the common electrode lines are partially opposite to each other so as to form storage capacitance; the storage capacitance of the sub-pixel units (1, 2) in the same row of sub-pixel units is gradually decreased from the end close to the gate line driver to the end away from the gate line driver. The array substrate can be used for liquid crystal display televisions, liquid crystal displays, mobile phones, tablet computers and other display devices.

Description

Array substrate and display device

The present application claims priority to Chinese Patent Application No. CN201410856588.0, filed on Dec. 31, 2014, which is incorporated herein by reference.

Technical field

The present invention relates to the field of display technologies, and in particular to an array substrate and a display device.

Background technique

TFT (Thin Film Transistor)-LCD (Liquid Crystal Display) is mainly composed of a liquid crystal panel, a gate line driver (also called a gate line driver circuit), a data driver (also called a data driving circuit), and timing control. Composed of a gamma voltage generator and a backlight. The liquid crystal panel is composed of an array substrate, a color filter substrate, and a liquid crystal. The data lines and the gate lines are formed on the array substrate, and the TFTs disposed at the intersections of the data lines and the gate lines are used to transmit the data signals output by the data driver to the pixel electrodes of the array substrate to drive the liquid crystals corresponding to the pixel electrodes.

The gate line driver connects the gate lines through the fan-shaped traces to provide gate line drive signals for the respective gate lines. However, on the same gate line, from the initial segment close to the gate line driver to the end segment away from the gate line driver, the gate line driving signals at each position have a certain RC Delay (resistance and capacitance delay), resulting in the end of the same gate line. The driving time of the TFT is smaller than the driving time of the TFT of the initial stage. Further, the charging amount of the pixel electrode corresponding to the initial segment is larger than the charging amount of the pixel electrode corresponding to the last segment, and the pixel electrode corresponding to the initial segment may even be overcharged, so that the amount of light emitted by each sub-pixel unit in the same row is deviated. , reducing the display effect of the LCD.

Summary of the invention

It is an object of the present invention to provide an array substrate and a display device which can improve the phenomenon that the amount of light emitted by each sub-pixel unit in the same row is inconsistent.

A first aspect of the present invention provides an array substrate including a plurality of sub-pixel units arranged in an array and a gate line driver disposed on one side of the array substrate, wherein each sub-pixel unit is provided with a pixel electrode and a common electrode line. The pixel electrode and the common electrode line portion form a storage capacitor opposite to each other;

In the same sub-pixel unit row, the storage capacitor of each sub-pixel unit is away from the end near the gate line driver One end of the gate line driver is gradually reduced.

Wherein, in the same sub-pixel unit row, for the sub-pixel unit having the smallest distance from the gate line driver and the sub-pixel unit having the largest distance from the gate line driver, the ratio of the storage capacitance of the two is equal to The ratio of the actual charging duration of the pixel electrode is reciprocal.

The ratio of the sub-pixel unit having the smallest distance from the gate line driver and the storage capacitance of the sub-pixel unit having the largest distance from the gate line driver is:

Where T1 is the theoretical charging duration of each sub-pixel unit, T2 is the delay charging period of each sub-pixel unit, and n is the number of sub-pixel units in the sub-pixel unit row.

The theoretical charging duration of each sub-pixel unit is a ratio of the display duration of each frame of image to the number of gate lines of the array substrate.

The delay duration of each sub-pixel unit is a product of a gate line resistance and a parasitic capacitance corresponding to the sub-pixel unit, and the parasitic capacitance is formed by a gate line, a source, and a drain.

Wherein, in the same sub-pixel unit row, a relative area of the pixel electrode and the common electrode line of each sub-pixel unit gradually decreases from an end near the gate line driver to an end away from the gate line driver.

Wherein, in any two adjacent sub-pixel units of the same sub-pixel unit row, a storage capacitor of a sub-pixel unit that is closer to the gate line driver and a storage capacitor of a sub-pixel unit that is farther from the gate line driver The difference is fixed.

Wherein, in any two adjacent sub-pixel units of the same sub-pixel unit row, the ratio of the storage capacitances of the two is the reciprocal of the ratio of the actual charging times of the two.

Wherein, each sub-pixel unit row includes 5760 sub-pixel units.

The present invention brings about the following beneficial effects: in the technical solution of the embodiment of the present invention, in order to ensure that the charging effects of the pixel electrodes of the sub-pixel units in the same sub-pixel unit row are the same or approximately the same, the storage capacitance of each sub-pixel unit It can be gradually reduced from one end close to the gate line driver to one end away from the gate line driver. Although the driving time of the TFT of each sub-pixel unit does not change, the size of the storage capacitor is different, and the storage capacity of the sub-pixel unit in which the driving time of the TFT is longer is larger. The presence of a storage capacitor extends the time the pixel electrode is charged to a specified potential. By adjusting the size of the storage capacitor, the pixel electrodes of each sub-pixel unit in the same sub-pixel unit row can be charged to a specified potential, thereby ensuring the display effect of the display device.

A second aspect of the present invention provides a display device including the above array substrate and a color filter substrate mated with the array substrate.

Other features and advantages of the present invention will be set forth in the description which follows and become apparent from the description. It is easy to see or understand by implementing the invention. The objectives and other advantages of the invention may be realized and obtained by means of the structure particularly pointed in the appended claims.

DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, a brief description of the drawings required in the description of the embodiments will be briefly made below:

1 is a schematic structural view of an array substrate;

2 is a schematic structural view of a sub-pixel unit.

detailed description

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and embodiments, in which the present invention can be applied to the technical problems, and the implementation of the technical effects can be fully understood and implemented. It should be noted that the various embodiments of the present invention and the various features of the various embodiments may be combined with each other, and the technical solutions formed are all within the scope of the present invention.

The present invention provides an array substrate. As shown in FIG. 1, the array substrate includes a plurality of arrayed sub-pixel units and a gate line driver disposed on one side of the array substrate. As shown in FIG. 2, each sub-pixel unit 1 is provided with a pixel electrode 7 and a common electrode line 8, and the pixel electrode 7 and the common electrode line 8 partially form a storage capacitor.

Generally, one gate line 3 is disposed corresponding to one sub-pixel unit row, and drives a thin film transistor (TFT) of each sub-pixel unit in the sub-pixel unit row. Each of the TFTs is driven by the gate line 3 to turn on the source 5 and the drain 6 of the TFT, and the pixel electrode 7 connected to the drain 6 is supplied with an electric signal from the data line 4 perpendicular to the gate line 3 to charge the pixel electrode 7. . After the charging is completed, the pixel electrode 7 and the common electrode have a certain potential difference, which can jointly drive the liquid crystal molecules in the display device to deflect. The potentials of the pixel electrodes 7 are different everywhere, so that the degree of deflection of the liquid crystal molecules throughout the display device is different, and thus the display device can display an image.

Since on the same gate line 3, from the initial segment close to the gate line driver to the end segment away from the gate line driver, the corresponding gate line driving signals of the respective sub-pixel units have a certain resistance-capacitance delay. The resistance-capacitance delay is caused by the resistance of the gate line 3 itself and the parasitic capacitance in the sub-pixel unit, wherein the parasitic capacitance is the overlap of the source 5, the drain 6 and the gate line 3 of the TFT in the sub-pixel unit. Forming. The resistor-capacitor delay will cause the driving time of the TFT of the sub-pixel unit farthest from the gate line driver to be smaller than the driving time of the TFT of the sub-pixel unit closest to the gate line driver, which may result in the farthest distance from the gate line driver. The potential of the pixel electrode 7 of the pixel unit after charging does not reach the specified potential, and the pixel electrode 7 of the sub-pixel unit closest to the gate line driver may continue to charge after charging saturation, which affects the display effect of the display device. Especially when the low gray scale is displayed, there is The brightness of the sub-pixel unit in the same row may be different. Specifically, the display effect of the sub-pixel unit close to the gate line driver is white.

Therefore, in the technical solution of the embodiment of the present invention, in order to ensure that the charging effects of the pixel electrodes of the sub-pixel units in the same sub-pixel unit row are the same or approximately the same, the storage capacitance of each sub-pixel unit may be close to the gate line driver. One end gradually decreases toward the end remote from the gate line driver. Although the driving time of the TFT of each sub-pixel unit does not change, the size of the storage capacitor is different, and the storage capacity of the sub-pixel unit in which the driving time of the TFT is longer is larger. The presence of a storage capacitor extends the time the pixel electrode is charged to a specified potential. By adjusting the size of the storage capacitor, the pixel electrodes of each sub-pixel unit in the same sub-pixel unit row can be charged to a specified potential, thereby ensuring the display effect of the display device.

For convenience of description, the sub-pixel unit having the smallest distance from the gate line driver will be simply referred to as the first sub-pixel unit 1 , and the sub-pixel unit having the largest distance from the gate line driver will be simply referred to as the second sub-pixel unit 2 .

In an embodiment of the present invention, the storage capacitances of the first sub-pixel unit 1 and the second sub-pixel unit 2 in the same row of sub-pixel unit rows may be first determined. Then, according to the storage capacitance of the two sub-pixel units of the first end, the size of the storage capacitor of each sub-pixel unit located between the two sub-pixel units is determined by a gradual design. Specifically, in any two adjacent sub-pixel units of the same sub-pixel unit row, the storage capacitance of the sub-pixel unit closer to the gate line driver and the storage capacitance of the sub-pixel unit farther from the gate line driver The difference is fixed.

Specifically, in the same sub-pixel unit row, for the first sub-pixel unit 1 and the second sub-pixel unit 2, the ratio of the storage capacitances of the two sub-pixel units 1 and the second sub-pixel unit 2 should be the inverse of the ratio of the actual charging durations of the pixel electrodes of the two sub-pixel units 1 and the second sub-pixel unit 2 To adjust the charging effect of the pixel electrodes 7 of the first sub-pixel unit 1 and the second sub-pixel unit 2 by using the storage capacitor.

Wherein, since the distance between the first sub-pixel unit 1 and the gate line driver is the closest, compared with other sub-pixel units, it is not affected by the delay of the resistance and capacitance of the gate line 3. Therefore, it can be considered that the actual charging duration of the first sub-pixel unit 1 is the driving duration of the gate line 3, that is, the theoretical charging duration of each sub-pixel unit. The second sub-pixel unit 2 is away from the gate line driver, and is affected by the resistance-capacitance delay of the gate line 3 corresponding to the plurality of sub-pixel units including the first sub-pixel unit 1, and the actual charging of the second sub-pixel unit 2 is performed. The duration should be the difference between the theoretical charging duration of each sub-pixel unit and the delayed charging duration of each sub-pixel unit. That is, the ratio of the storage capacitances of the first sub-pixel unit 1 and the second sub-pixel unit 2 should be:

Specifically, the theoretical charging duration of each sub-pixel unit is a ratio of the display duration of each frame of image to the number of gate lines 3 of the array substrate. The delay time of each sub-pixel unit is the resistance and the gate line 3 corresponding to the sub-pixel unit The product of the capacitance, the parasitic capacitance is composed of the gate line 3, the source 5, and the drain 6.

Taking the current mainstream high-definition display device as an example, the resolution of the high-definition display device is 1920×1080, that is, each sub-pixel unit row includes 1920×3=5760 sub-pixel units. Assuming that the refresh rate of the high definition display device is 60 Hz, the display time of each frame of the high definition display device is 1/60 second. Since the display driving method is progressive scanning, the theoretical charging time of each sub-pixel unit is 1/(60×1080). When displayed, the second sub-pixel unit 2 at the end of the sub-pixel unit row is affected by the resistance-capacitance delay of the other 5760-1=5759 sub-pixel units in the same row; and the delay time of the resistance-capacitance delay of each sub-pixel unit R × C, where R is the gate line resistance of each sub-pixel unit, C is the storage line formed by the gate line and the source and drain.

Then, the actual charging duration of the second sub-pixel unit 2 is:

Therefore, the ratio of the storage capacitances of the first sub-pixel unit 1 and the second sub-pixel unit 2 is:

Obviously, when the storage capacitance of each sub-pixel unit between the first sub-pixel unit 1 and the second sub-pixel unit 2 is gradually designed, any two adjacent sub-pixel units of the same sub-pixel unit row may also be made. The ratio of the storage capacitors of the two is the reciprocal of the ratio of the actual charging times of the two.

Specifically, the storage capacitance of each sub-pixel unit can be adjusted by adjusting the relative areas of the pixel electrode 7 and the common electrode line 8. That is, in the same sub-pixel unit row, the relative areas of the pixel electrode 7 and the common electrode line 8 of each sub-pixel unit gradually decrease from one end close to the gate line driver to one end away from the gate line driver.

A second aspect of the present invention provides a display device including the above array substrate and a color filter substrate mated with the array substrate. The display device can be a display device such as a liquid crystal television, a liquid crystal display, a mobile phone, or a tablet computer.

While the embodiments of the present invention have been described above, the described embodiments are merely illustrative of the embodiments of the invention and are not intended to limit the invention. Any modification and variation of the form and details of the embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention. It is still subject to the scope defined by the appended claims.

Description of the reference signs:

1-first sub-pixel unit; 2- second sub-pixel unit; 3-gate line;

4-data line; 5-source; 6-drain;

7-pixel electrode; 8- common electrode line.

Claims

An array substrate, comprising: a plurality of arrayed sub-pixel units and a gate line driver disposed on one side of the array substrate, each sub-pixel unit correspondingly provided with a pixel electrode and a common electrode line, the pixel electrode and the common The electrode line portion forms a storage capacitor opposite to each other;

In the same sub-pixel unit row, the storage capacitance of each sub-pixel unit gradually decreases from an end near the gate line driver to an end away from the gate line driver.
The array substrate according to claim 1, wherein, in the same sub-pixel unit row, for a sub-pixel unit having the smallest distance from the gate line driver and a sub-pixel unit having the largest distance from the gate line driver, The ratio of the ratio of the storage capacitance of the two to the actual charging duration of the pixel electrodes of the two is reciprocal.
The array substrate according to claim 2, wherein a ratio of a sub-pixel unit having the smallest distance from the gate line driver and a storage capacitor of a sub-pixel unit having the largest distance from the gate line driver is:

Where T1 is the theoretical charging duration of each sub-pixel unit, T2 is the delay charging period of each sub-pixel unit, and n is the number of sub-pixel units in the sub-pixel unit row.
The array substrate according to claim 3, wherein the theoretical charging duration of each sub-pixel unit is a ratio of a display duration of each frame of image to a number of gate lines of the array substrate.
The array substrate according to claim 3, wherein a delay duration of each sub-pixel unit is a product of a gate line resistance and a parasitic capacitance corresponding to the sub-pixel unit, and the parasitic capacitance is a gate line and a source and a drain. of.
The array substrate according to claim 3, wherein in the same sub-pixel unit row, a relative area of the pixel electrode and the common electrode of each sub-pixel unit is from an end near the gate line driver to an end away from the gate line driver slowing shrieking.
The array substrate according to claim 6, wherein in any two adjacent sub-pixel units of the same sub-pixel unit row, a storage capacitor of a sub-pixel unit closer to the gate line driver and a distance from the gate line The difference in storage capacitance of the sub-pixel unit farther from the driver is fixed.
The array substrate according to claim 6, wherein the ratio of the storage capacitances of the two adjacent sub-pixel units of the same sub-pixel unit row is the reciprocal of the ratio of the actual charging times of the two.
The array substrate of claim 1 wherein each sub-pixel unit row comprises 5760 sub-pixel units.
A display device includes an array substrate and a color filter substrate mated with the array substrate;

The array substrate includes a plurality of arrayed sub-pixel units and a gate line driver disposed on one side of the array substrate, and each of the sub-pixel units is correspondingly provided with a pixel electrode and a common electrode line, and the pixel electrode and the common electrode line portion Phase For forming a storage capacitor; in the same sub-pixel row, the storage capacitor of each sub-pixel unit gradually decreases from an end near the gate driver to an end remote from the gate driver.
The display device according to claim 10, wherein, in the same sub-pixel unit row, for a sub-pixel unit having the smallest distance from the gate line driver and a sub-pixel unit having the largest distance from the gate line driver, The ratio of the ratio of the storage capacitance of the two to the actual charging duration of the pixel electrodes of the two is reciprocal.
The display device according to claim 11, wherein a ratio of a sub-pixel unit having the smallest distance from the gate line driver and a storage capacitor of a sub-pixel unit having the largest distance from the gate line driver is:

Where T1 is the theoretical charging duration of each sub-pixel unit, T2 is the delay charging period of each sub-pixel unit, and n is the number of sub-pixel units in the sub-pixel unit row.
The display device according to claim 12, wherein the theoretical charging duration of each sub-pixel unit is a ratio of a display duration of each frame of image to a number of gate lines of the array substrate.
The display device according to claim 12, wherein a delay duration of each sub-pixel unit is a product of a gate line resistance and a parasitic capacitance corresponding to the sub-pixel unit, and the parasitic capacitance is a gate line and a source and a drain. of.
The display device according to claim 12, wherein in the same sub-pixel unit row, a relative area of the pixel electrode and the common electrode of each sub-pixel unit is from an end near the gate line driver to an end away from the gate line driver slowing shrieking.
The display device according to claim 15, wherein the storage capacitance of the sub-pixel unit closer to the gate line driver and the distance from the gate line in any two adjacent sub-pixel units of the same sub-pixel unit row The difference in storage capacitance of the sub-pixel unit farther from the driver is fixed.
The display device according to claim 15, wherein the ratio of the storage capacitances of the two adjacent sub-pixel units of the same sub-pixel unit row is the reciprocal of the ratio of the actual charging times of the two.
The display device of claim 10, wherein each sub-pixel unit row comprises 5760 sub-pixel units.