KR20010060876A - BGA package comprising circuit board with enhanced solder pad - Google Patents
BGA package comprising circuit board with enhanced solder pad Download PDFInfo
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- KR20010060876A KR20010060876A KR1019990063334A KR19990063334A KR20010060876A KR 20010060876 A KR20010060876 A KR 20010060876A KR 1019990063334 A KR1019990063334 A KR 1019990063334A KR 19990063334 A KR19990063334 A KR 19990063334A KR 20010060876 A KR20010060876 A KR 20010060876A
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- ball
- circuit board
- solder
- pads
- package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
본 발명은 비지에이 패키지(BGA package ; Ball Grid Array package)에 관한 것이며, 더욱 구체적으로는 비지에이 패키지의 솔더 볼이 회로기판(Circuit board)의 하면에서 절연층(Insulation layer)에 형성된 비아(Via)를 통해 노출되는 볼 패드 위로 형성됨에 따라 솔더 결합의 신뢰성이 저하되는 것을 방지하는 것을 특징으로 하는 회로기판의 구조를 개선한 비지에이 패키지에 관한 것이다.The present invention relates to a ball grid array package (BGA package), and more specifically to a via formed in an insulation layer on a lower surface of a circuit board. The present invention relates to a BG package having an improved structure of a circuit board, wherein the structure of the circuit board is prevented from being degraded as a result of being formed over the ball pad exposed through the pad.
일반적으로 반도체 소자(Semiconductor device) 기술의 추세는 초소형화(超小形化), 고밀도화(高密度化) 및 저가격화(低價格化) 등을 특징으로 하며, 이에 따라 다양한 형태의 반도체 소자들이 개발되어 사용되고 있다. 특히, 최근에는 노트북 컴퓨터(Notebook Computer), 디지털 비디오 카메라(Digital Video Camera), 휴대전화(Cellular phone) 등 휴대용 기기 보급의 급증으로 각 반도체 소자의 소형화및 경량화 정도가 중요시되고 있다.In general, the trend of semiconductor device technology is characterized by miniaturization, high density, and low cost, and various types of semiconductor devices have been developed. It is used. In particular, the recent miniaturization and weight reduction of each semiconductor device have become important due to the proliferation of portable devices such as notebook computers, digital video cameras, and cellular phones.
이러한 추세에 맞추어, 반도체 소자들 중 소위 칩 스케일 패키지(CSP ; Chip Scale Package)는 리드 온 칩(LOC ; Lead On Chip) 기술 또는 비지에이(BGA) 기술의 연장선상에 있는 제품들을 중심으로 다양하게 개발되고 있다.In line with this trend, so-called Chip Scale Packages (CSPs) among semiconductor devices are variously focused on products that are an extension of Lead On Chip (LOC) technology or BGA technology. Is being developed.
도 1은 기존의 마이크로 비지에이 패키지(μBGA package ; micro Ball Grid Array package)를 일부분 도시한 단면도이며, 도 1을 참고로 하여 종래의 마이크로 비지에이 패키지(100)의 구조를 간략히 설명하면 다음과 같다.1 is a cross-sectional view partially showing a conventional micro-BGA package (μBGA package; micro Ball Grid Array package), a brief description of the structure of the conventional micro-VISA package 100 with reference to FIG. .
종래의 마이크로 비지에이 패키지는 반도체 칩(10) 위로 탄성중합체(20 ; Elastomer)가 개재되어 마이크로 비지에이용 테이프(50 ; Tape for μBGA package)가 부착된 구조이다.The conventional microvisi package has a structure in which an elastomer 20 (Elastomer) is interposed on the semiconductor chip 10 and a tape for μBGA package 50 is attached.
마이크로 비지에이용 테이프(50)는 폴리이미드 필름(30 ; Polyimide film)의 하면에 빔 리드(40 ; Beam lead)가 형성되고, 반도체 칩(10)의 본딩패드(12)에 대응되는 부분을 따라 빔 리드가 노출되도록 윈도우(Window)가 형성되어 있으며, 테이프의 상면에 격자형으로 개구부(32 ; Opening)들이 형성되어 빔 리드들의 일단을 노출시킴으로써 볼 패드(42 ; Ball pad)들이 형성된 것을 특징으로 한다.The micro-visgi tape 50 has a beam lead 40 formed on the bottom surface of the polyimide film 30 and along a portion corresponding to the bonding pad 12 of the semiconductor chip 10. A window is formed to expose the beam lead, and openings 32 are formed in a lattice shape on the upper surface of the tape, and ball pads 42 are formed by exposing one end of the beam leads. do.
빔 리드(40)는 윈도우를 통해 본딩 툴(Bonding tool ; 도시되지 않음)과 같은 수단에 의해 "S"자 형으로 굴곡되어 본딩패드(12) 위로 본딩되며, 이들 빔 리드가 본딩된 영역이 인캡슐런트(Encapsulant)와 같은 성형수지(70)로 몰딩되고, 개구부(42)를 통해 노출된 볼 패드(42)들 위로 솔더 볼(60)들이 형성된 것을 특징으로 한다.The beam leads 40 are bent into an “S” shape by means such as a Bonding tool (not shown) through the window and bonded onto the bonding pads 12, where the areas where these beam leads are bonded are in The solder balls 60 are formed on the ball pads 42 molded with a molding resin 70 such as an encapsulant and exposed through the opening 42.
이러한 구조의 마이크로 비지에이 패키지는 빔 리드를 "S"자 형으로 굴곡시키는 공정이 어렵고, 또한 마이크로 비지에이용 테이프를 구성함에 제한요소가 많아 자유도를 갖기 어려우며, 탄성중합체 및 인캡슐런트 등을 사용하기 때문에 기존 설비를 활용하기 어렵고 또한 제조원가의 상승을 가져올 수 있다.The microvisi package of such a structure is difficult to bend the beam lead into an "S" shape, and it is difficult to have a degree of freedom due to the many limitations in constructing the microvisiation tape, and an elastomer and an encapsulant are used. This makes it difficult to utilize existing facilities and can lead to an increase in manufacturing costs.
또한, 빔 리드를 사용하기 때문에 빔 리드 본딩 공정의 특성상 반도체 칩 위의 본딩패드들이 2열로 형성되는 경우 이러한 구조를 적용할 수 없다.In addition, since the beam lead is used, this structure cannot be applied when the bonding pads on the semiconductor chip are formed in two rows due to the characteristics of the beam lead bonding process.
도 2는 종래의 비지에이 패키지(BGA package)를 일부분 도시한 단면도이며, 도 2를 참고로 하여 종래의 비지에이 패키지(200)의 구조를 간략히 설명하면 다음과 같다.FIG. 2 is a cross-sectional view partially illustrating a conventional BGA package. Referring to FIG. 2, the structure of the conventional BGA package 200 will be briefly described as follows.
종래의 비지에이 패키지(200)는 반도체 칩(110)이 회로기판(120 ; Circuit board)의 상면(124)에 실장된 후 본딩 와이어(150)를 이용하여 반도체 칩의 본딩패드(112)와 회로기판의 전극패드(126)를 전기적으로 연결시키고, 반도체 칩(110)과 본딩 와이어(150)를 포함하는 영역 - 즉, 회로기판의 상면(124) 부분 - 을 에폭시 몰딩 컴파운드(EMC ; Epoxy Molding Compound)와 같은 성형수지(160)로 몰딩한 것을 특징으로 한다.In the conventional BG package 200, the semiconductor chip 110 is mounted on the top surface 124 of the circuit board 120, and then the bonding pad 112 and the circuit of the semiconductor chip are bonded using the bonding wire 150. The electrode pad 126 of the substrate is electrically connected to each other, and an area including the semiconductor chip 110 and the bonding wire 150, that is, a portion of the upper surface 124 of the circuit board, is epoxy molding compound (EMC). It is characterized in that molded into a molding resin 160, such as).
또한, 회로기판(120)의 하면(122)에 형성된 볼 패드(128) 위로 솔더 볼(140)이 형성된다.In addition, the solder balls 140 are formed on the ball pads 128 formed on the bottom surface 122 of the circuit board 120.
비지에이 패키지(200)에 사용되는 회로기판(120)은 상면(124)의 중앙부에 접착제(114 ; Adhesive)가 개재되어 반도체 칩(110)이 실장되고 반도체 칩이 실장된 주변을 따라 본딩패드(112)에 대응되는 전극패드(126)들이 형성되어 있으며, 회로기판의 하면(122)에 상면의 전극패드(126)와 전기적으로 연결되는 볼 패드(128)들이 형성된 것을 특징으로 한다. 또한, 회로기판의 하면(122)에는 볼 패드(128)들이 노출되도록 비아(132)들이 형성된 절연층(130)이 형성되어 있다.The circuit board 120 used in the BG package 200 has an adhesive 114 interposed in the center of the upper surface 124 so that the semiconductor chip 110 is mounted and a bonding pad is formed along the periphery of the semiconductor chip. The electrode pads 126 corresponding to the 112 are formed, and the ball pads 128 electrically connected to the electrode pads 126 on the upper surface are formed on the lower surface 122 of the circuit board. In addition, an insulating layer 130 having vias 132 formed thereon is formed on the bottom surface 122 of the circuit board to expose the ball pads 128.
이러한 구조의 비지에이 패키지(200)에서, 형성되는 솔더 볼들의 크기가 작아질수록 솔더 볼(140)과 볼 패드(128) 사이의 결합에 대한 신뢰성이 저하될 수 있다. 즉, 솔더 볼(140)이 일정한 높이(A)로 형성되는 과정에서 솔더 볼(140)이 비아(132)를 통해 노출되는 볼 패드(128)에만 결합되기 때문에 솔더 결합의 신뢰성이 저하될 수 있다.In the visualization package 200 having such a structure, the smaller the size of the solder balls formed, the lower the reliability of the coupling between the solder balls 140 and the ball pads 128. That is, since the solder ball 140 is bonded only to the ball pad 128 exposed through the via 132 in the process in which the solder ball 140 is formed at a constant height A, the reliability of solder bonding may be reduced. .
본 발명의 목적은 솔더 볼과 볼 패드 사이의 결합력을 향상시킬 수 있는 구조의 회로기판을 포함하는 비지에이 패키지를 제공하는 것이다.SUMMARY OF THE INVENTION An object of the present invention is to provide a BG package including a circuit board having a structure capable of improving a bonding force between a solder ball and a ball pad.
본 발명의 다른 목적은 솔더 볼의 결합력을 향상시키기 위하여 볼 패드에 더하여 솔더 접합부가 구비된 회로기판을 제공하는 것이다.Another object of the present invention is to provide a circuit board having a solder joint in addition to the ball pad in order to improve the bonding force of the solder ball.
도 1은 기존의 마이크로 비지에이 패키지를 일부분 도시한 단면도,1 is a cross-sectional view showing a portion of a conventional microvisi package;
도 2는 종래의 비지에이 패키지를 일부분 도시한 단면도,2 is a cross-sectional view showing a portion of a conventional BG package;
도 3은 본 발명의 일 실시예에 따른 비지에이 패키지를 일부분 도시한 단면도,Figure 3 is a cross-sectional view showing a portion of a busy package according to an embodiment of the present invention,
도 4는 본 발명의 다른 실시예에 따른 비지에이 패키지를 일부분 도시한 단면도이다.Figure 4 is a cross-sectional view showing a portion of a busy package according to another embodiment of the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
10, 110, 210 : 반도체 칩 12, 112, 212 : 본딩패드10, 110, 210: semiconductor chip 12, 112, 212: bonding pad
20 : 탄성중합체 30 : 폴리이미드 필름20: elastomer 30: polyimide film
32 : 비아(Via) 40 : 빔 리드32: Via 40: beam lead
42 : 볼 패드42: ball pad
50 : 마이크로 비지에이용 테이프50: Micro Visor Tape
60, 140, 240 : 솔더 볼 70, 160, 260 : 성형수지60, 140, 240: solder balls 70, 160, 260: molding resin
100 : 마이크로 비지에이 패키지(μBGA package)100: micro BGA package
120, 220, 220' : 회로기판(Circuit board)120, 220, 220 ': Circuit board
122, 222 : 하면 124, 224 : 상면122, 222: bottom surface 124, 224: top surface
126, 226 : 전극패드 128, 228 : 볼 패드126 and 226: electrode pads 128 and 228: ball pads
130, 230 : 절연층 132, 232 : 비아130, 230: insulation layer 132, 232: via
150, 250 : 본딩 와이어150, 250: bonding wire
200, 300, 300' : 비지에이 패키지(BGA package)200, 300, 300 ': BGA package
270 : 솔더 접착부(Enhanced solder pad)270: enhanced solder pad
272 : 표면영역 274 : 비아영역272: surface area 274: via area
이러한 목적들을 달성하기 위하여 본 발명은 본딩패드들이 구비된 반도체 칩과; 중앙에 반도체 칩이 실장되고 본딩패드에 대응되는 전극패드들이 주변에 구비된 상면과, 각 전극패드와 전기적으로 연결되는 볼 패드들이 구비된 하면, 및 볼 패드들이 노출되는 비아들이 형성되며 하면을 덮는 절연층을 포함하는 회로기판과; 본딩패드와 전극패드를 전기적으로 연결하는 본딩 와이어들; 및 볼 패드들 위로 형성되는 솔더 볼들;을 포함하는 비지에이 패키지에 있어서, 절연층의 표면에서 비아를 중심으로 볼 패드보다 넓게 솔더 볼이 부착되는 표면영역을 형성하는 솔더 접합부;를 더 포함하는 것을 특징으로 하는 솔더 접합부를 구비한 회로기판을 포함하는 비지에이 패키지를 제공한다.In order to achieve these objects, the present invention provides a semiconductor chip including bonding pads; The upper surface of the semiconductor chip is mounted in the center and the electrode pads corresponding to the bonding pads are provided, the lower surface of the ball pads electrically connected to the electrode pads, and the vias to which the ball pads are exposed are formed to cover the lower surface. A circuit board including an insulating layer; Bonding wires electrically connecting the bonding pads and the electrode pads; And solder balls formed over the ball pads, comprising: a solder joint formed on a surface of the insulating layer to form a surface area to which the solder balls are attached to the via pads rather than the ball pads. Provided is a BG package including a circuit board having a solder joint.
또한 본 발명에 따른 비지에이 패키지에 있어서, 전술한 솔더 접합부는 절연층 위로 확장되어 형성된 표면영역에 더하여 비아의 내벽을 따라 형성된 비아영역을 더 포함하는 것을 특징으로 한다.In addition, in the BG package according to the present invention, the solder joint may further include a via region formed along an inner wall of the via, in addition to the surface region formed to extend over the insulating layer.
이하, 첨부도면을 참고로 하여 본 발명의 바람직한 실시예들을 설명한다.Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
도 3은 본 발명의 일 실시예에 따른 비지에이 패키지(BGA package)를 일부분 도시한 단면도이며, 도 3을 참고로 하여 본 발명에 따른 비지에이 패키지(300)의 구조를 간략히 설명하면 다음과 같다.3 is a cross-sectional view partially showing a BGA package according to an embodiment of the present invention. Referring to FIG. 3, the structure of the BGA package 300 according to the present invention will be briefly described as follows. .
본 발명에 따른 비지에이 패키지(300)는 종래와 마찬가지로 반도체 칩(210)이 회로기판(220)의 상면(224)에 실장된 후 본딩 와이어(250)를 이용하여 반도체 칩의 본딩패드(212)와 회로기판의 전극패드(226)를 전기적으로 연결시키고, 반도체 칩(210)과 본딩 와이어(250)를 포함하는 영역을 에폭시 몰딩 컴파운드(EMC)와 같은 성형수지(260)로 몰딩한 것을 특징으로 한다.In the BG 300 according to the present invention, the semiconductor chip 210 is mounted on the upper surface 224 of the circuit board 220 as in the related art, and then the bonding pads 212 of the semiconductor chip are bonded using the bonding wire 250. And the electrode pads 226 of the circuit board are electrically connected to each other, and a region including the semiconductor chip 210 and the bonding wire 250 is molded with a molding resin 260 such as an epoxy molding compound (EMC). do.
회로기판(220)은 상면(224)의 중앙부에 접착제(214)가 개재되어 반도체 칩(210)이 실장되고 반도체 칩이 실장된 주변을 따라 본딩패드(212)에 대응되는 전극패드(226)들이 형성되어 있으며, 회로기판의 하면(222)에 상면의 전극패드(226)와 전기적으로 연결되는 볼 패드(228)들이 형성된 것을 특징으로 한다. 회로기판의 하면(222)에는 볼 패드(228)들이 노출되도록 비아(232)들이 형성된 절연층(230)이 형성되어 있다.The circuit board 220 includes the electrode pads 226 corresponding to the bonding pads 212 along the periphery where the semiconductor chip 210 is mounted and the semiconductor chip 210 is interposed with the adhesive 214 interposed in the center of the upper surface 224. The ball pads 228 electrically connected to the electrode pads 226 on the upper surface of the circuit board are formed on the lower surface 222 of the circuit board. An insulating layer 230 having vias 232 formed thereon is formed on the bottom surface 222 of the circuit board to expose the ball pads 228.
이러한 구조에 더하여 본 발명의 일 실시예에 따른 회로기판(220)은 절연층(230)의 표면에서 비아(232)를 중심으로 볼 패드(228)보다 넓게 솔더 볼이 부착될 수 있도록 금속 등의 재질로 확장되어 형성된 표면영역(Surface area)을 포함하는 솔더 접합부(270 ; Enhanced solder pad)가 형성된 것을 특징으로 한다.In addition to such a structure, the circuit board 220 according to the exemplary embodiment of the present invention may be formed of a metal or the like so that solder balls may be attached to the via pads 228 on the surface of the insulating layer 230. An enhanced solder pad (270) including a surface area formed by extending a material is formed.
이와 같이, 볼 패드(228)와 볼 패드보다 넓게 형성된 솔더 접합부(270) 위로 솔더 볼(240)이 형성되며, 이때 솔더 볼(240)이 형성되는 높이(B)는 종래의 경우(도 2의 A)보다 낮게 형성된다. 즉 동일한 양의 솔더를 공급하여 솔더 볼을 형성하는 경우, 솔더가 직접 접촉되는 표면적이 넓게 되기 때문에 솔더 볼의 높이는 낮아지게 된다. 따라서, 비지에이 패키지를 실장함에 있어 패키지 전체의 실장 높이가 낮아지는 효과를 가져올 수 있다.As such, the solder ball 240 is formed on the ball pad 228 and the solder joint 270 that is formed wider than the ball pad, and the height B at which the solder ball 240 is formed is a conventional case (see FIG. 2). It is formed lower than A). That is, when the solder balls are formed by supplying the same amount of solder, the height of the solder balls is lowered because the surface area where the solders are in direct contact is increased. Therefore, in mounting the package, the mounting height of the entire package can be reduced.
도 4는 본 발명의 다른 실시예에 따른 비지에이 패키지(BGA package)를 일부분 도시한 단면도이며, 도 4를 참고로 하여 본 발명의 다른 실시예에 따른 비지에이 패키지(300')의 구조를 본 발명의 일 실시예에 따른 비지에이 패키지(300)와 비교 설명하면 다음과 같다.4 is a cross-sectional view partially showing a BGA package according to another embodiment of the present invention. Referring to FIG. 4, the structure of the BGA package 300 ′ according to another embodiment of the present invention is shown. When compared with the BG 300 according to an embodiment of the present invention.
본 발명의 다른 실시예에 따른 비지에이 패키지(300')는 도 3의 비지에이 패키지(300)와 거의 동일한 구조를 가지며, 동일한 구성요소는 설명의 편의상 동일한 부호를 사용하여 도시하였으며, 자세한 설명은 생략하기로 한다.The BG package 300 ′ according to another embodiment of the present invention has a structure substantially the same as that of the BG package 300 of FIG. 3, and the same components are illustrated using the same reference numerals for convenience of description. It will be omitted.
도 4의 비지에이 패키지(300')는 회로기판(220')의 솔더 접합부(270')의 형상이 도 3의 솔더 접합부에 비하여 다른 것을 특징으로 한다. 즉, 도 3의 솔더 접합부(270)는 절연층(230)의 표면에서 비아를 중심으로 볼 패드보다 넓게 확장되어 형성된 표면영역으로 구성됨에 비해, 도 4의 솔더 접합부(270')는 표면영역(272)에 더하여 비아의 내벽을 따라 형성된 비아영역(274)을 더 포함하는 것을 특징으로 한다.4, the shape of the solder joint 270 ′ of the circuit board 220 ′ is different from that of the solder joint of FIG. 3. That is, the solder joint 270 of FIG. 3 has a surface area formed to be wider than the ball pad around the via on the surface of the insulating layer 230, whereas the solder joint 270 ′ of FIG. 4 has a surface area ( In addition to 272, it further comprises a via region 274 formed along the inner wall of the via.
도 3의 솔더 접합부(270)가 솔더가 결합되는 영역을 확장시킴으로써 솔더 결합력의 신뢰성을 향상시킴에 비해, 도 4의 솔더 접합부(270')는 솔더 결합력의 신뢰성을 향상시키고, 그에 더하여 솔더 볼(240)과 볼 패드(228) 사이의 전기 전도도를 향상시킬 수 있다.While the solder joint 270 of FIG. 3 improves the reliability of the solder bonding force by expanding the area where the solder is bonded, the solder joint 270 'of FIG. 4 improves the reliability of the solder bonding force, and in addition, the solder ball ( Electrical conductivity between the 240 and the ball pads 228 may be improved.
즉, 도 3의 솔더 접합부(270)는 볼 패드(228)와 전기적으로 단절된 형태로 형성되지만, 도 4의 솔더 접합부(270')는 비아영역(274)이 볼 패드(228)와 표면영역(272)을 전기적으로 연결하기 때문에, 솔더 접합부(270')가 볼 패드(228)와 전기적으로 연결되어 결국 솔더 볼(240)과 볼 패드(228) 사이의 전기 전도도를 향상시킬 수 있다.That is, although the solder joint 270 of FIG. 3 is formed to be electrically disconnected from the ball pad 228, the solder joint 270 ′ of FIG. 4 has a via area 274 having a ball pad 228 and a surface area ( Because of electrical connection of 272, solder joint 270 ′ may be electrically connected with ball pad 228 to ultimately improve electrical conductivity between solder ball 240 and ball pad 228.
도 3과 도 4의 솔더 접합부는 금속 패턴(Metal pattern)으로 형성되며, 솔더 접합부를 절연층에 형성하는 방법으로는 비아들이 형성된 절연층 위로 금속막을 도포한 후 감광막을 이용하여 금속막을 부분적으로 제거하는 방법을 적용할 수 있다.The solder joints of FIGS. 3 and 4 are formed in a metal pattern, and the solder joints are formed on the insulating layer by applying a metal film over the insulating layer on which the vias are formed, and then partially removing the metal film using the photosensitive film. Can be applied.
이상에서 설명한 바와 같이, 본 발명에 따른 비지에이 패키지는 솔더 볼이 형성되는 영역인 볼 패드에 더하여 볼 패드보다 넓게 절연층 위로 형성된 표면영역을 포함하는 솔더 접합부가 구비된 회로기판을 포함하는 것을 특징으로 하며, 이러한 구조를 통하여 솔더 볼과 볼 패드 사이의 솔더 결합력의 신뢰성을 확보할 수 있고, 또한 솔더가 접촉되는 영역이 확대됨에 따라 솔더 볼의 높이가 낮아지게 되어 결국 비지에이 패키지의 전체적인 패키지 높이가 낮아지는 등의 효과를 가져올 수 있다.As described above, the BG package according to the present invention includes a circuit board having a solder joint including a surface area formed on the insulating layer wider than the ball pad in addition to the ball pad which is the area where the solder ball is formed. Through this structure, the reliability of the solder bonding force between the solder ball and the ball pad can be ensured, and the height of the solder ball decreases as the area where the solder contacts are enlarged, resulting in the overall package height of the BG package. The effect can be lowered.
본 발명에 따른 비지에이 패키지는 회로기판에서 솔더 볼이 형성되는 영역인 볼 패드에 더하여 볼 패드보다 넓게 절연층 위로 형성된 표면영역을 포함하는 솔더 접합부가 구비된 것을 특징으로 하는 회로기판을 제공하고, 이러한 회로기판을 포함하는 비지에이 패키지의 구조를 제공하며, 이러한 구조를 통하여 솔더 볼과 볼 패드 사이의 솔더 결합력의 신뢰성을 확보할 수 있고, 또한 솔더가 접촉되는 영역이 확대됨에 따라 솔더 볼의 높이가 낮아지게 되어 결국 비지에이 패키지의 전체적인 패키지 높이가 낮아지는 등의 효과를 가져올 수 있다.The bus package according to the present invention provides a circuit board comprising a solder joint including a surface area formed on an insulating layer wider than a ball pad in addition to a ball pad which is a region where solder balls are formed in the circuit board. The structure of the BG package including such a circuit board provides the reliability of the solder bonding force between the solder ball and the ball pad, and also increases the height of the solder ball as the area where the solder contacts are enlarged. This will result in a lower overall package height of the BG package.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990063334A KR20010060876A (en) | 1999-12-28 | 1999-12-28 | BGA package comprising circuit board with enhanced solder pad |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990063334A KR20010060876A (en) | 1999-12-28 | 1999-12-28 | BGA package comprising circuit board with enhanced solder pad |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010060876A true KR20010060876A (en) | 2001-07-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990063334A KR20010060876A (en) | 1999-12-28 | 1999-12-28 | BGA package comprising circuit board with enhanced solder pad |
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| Country | Link |
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| KR (1) | KR20010060876A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9305895B2 (en) | 2013-11-25 | 2016-04-05 | SK Hynix Inc. | Substrates having ball lands, semiconductor packages including the same, and methods of fabricating semiconductor packages including the same |
-
1999
- 1999-12-28 KR KR1019990063334A patent/KR20010060876A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9305895B2 (en) | 2013-11-25 | 2016-04-05 | SK Hynix Inc. | Substrates having ball lands, semiconductor packages including the same, and methods of fabricating semiconductor packages including the same |
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